Technical data

vsim
100
-
ModelSim Command Reference ModelSim EE/PLUS Reference Manual
Examples
vsim -gedge=”low high” -gVCC=4.75 cpu
Invokes VSIM on the entity
cpu
and assigns values to the generic parameters
edge
and
VCC
.
vsim -view my_design.i03
Instructs VSIM to view the results of a previous simulation run stored in the log file,
my_design.i03
. Use the
-wav
option to specify the name of the signal log file to create if
you plan to create many files for later viewing. For example:
vsim -wav my_design.i01 my_asic structure
vsim -wav my_design.i02 my_asic structure
...
vsim -sdfmin asic.sdf -sdfnowarn my_asic
Annotates VHDL VITAL models. Invokes the simulator using the minimum timing from
the SDF file
asic.sdf
. In addition, the SDF reader’s warnings are turned off. When
annotating a Verilog design the <region> option is the module instance to be annotated. For
example, to annotate
top.u1
with minimum timing from the SDF file
mysdf
:
vsim -sdfmin /top.u1=mysdf top
Set the PathSeparator variable (p254) to "." in the
modelsim.ini
file if you choose
to use Verilog style pathnames for
<region>
:
vsim -sdfmin /top.u1=mysdf top
Use multiple switches to annotate multiple Verilog regions:
vsim -sdfmin /top.u1=sdf1 -sdfmin /top.u1=sdf2 top
Note that ’/’ is a super root, above the top level design unit.
vsim ’mylib.top(only)’ gatelib.cache_set
This example searches the libraries for
mylib top(only)
and
gatelib
for
cache_set
. If the
design units are not found, the search continues to the
work
library. Specification of the
architecture (
only
) is optional.
Note the single quotes surrounding the (); this prevents special parsing by the
UNIX shell.