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ModelSim EE/PLUS

Reference Manual

The ModelSim Elite Edition for

VHDL, Verilog, and Mixed-HDL Simulation

Summary of content (570 pages)

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ModelSim EE/PLUS Reference Manual The ModelSim Elite Edition for VHDL, Verilog, and Mixed-HDL Simulation
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ModelSim /VHDL, ModelSim /VLOG, ModelSim /LNL, and ModelSim /PLUS are produced by Model Technology Incorporated. Unauthorized copying, duplication, or other reproduction is prohibited without the written consent of Model Technology. The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology.
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Software License Agreement This is a legal agreement between you, the end user, and Model Technology Incorporated (MTI). By opening the sealed package, or by signing this form, you are agreeing to be bound by the terms of this agreement. If you do not agree to the terms of this agreement, promptly return the unopened package and all accompanying items to the place you obtained them for a full refund. Model Technology Software License 1. LICENSE.
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from MTI. All copies of the SOFTWARE, whether provided by MTI or made by you, shall remain the property of MTI or its licensors. You will maintain a record of the number and location of all copies of the SOFTWARE made, including copes that have been merged with other software, and will make those records available to MTI or its applicable licensor upon request. 5. TRADE SECRET. The source code of the SOFTWARE is trade secret or confidential information of MTI or its licensors.
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Limited Warranty LIMITED WARRANTY. MTI warrants that the SOFTWARE will perform substantially in accordance with the accompanying written materials for a period of 30 days from the date of receipt. Any implied warranties on the SOFTWARE are limited to 30 days. Some states do not allow limitations on duration of an implied warranty, so the above limitation may not apply to you. CUSTOMER REMEDIES.
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Table of Contents Software License Agreement . . . . Model Technology Software License . Important Notice . . . . . . . . . Limited Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii iii iv v 1 - Introduction (p23) Software versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Alternate IEEE libraries supplied Rebuilding supplied libraries . . Regenerating your design libraries Verilog resource libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 . 43 . 43 . 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5 - ModelSim Command Reference (p67) Syntax conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 dumplog64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 modelsim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 tssi2mti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 vcom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 vdel . . . . . . . . . . . . . . . . . . . .
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The Main window menu bar . . . . . . . . . . . . . . The Main window tool bar . . . . . . . . . . . . . . . The Main window status bar . . . . . . . . . . . . . . Editing the command line, the current source file, and notepads Dataflow window . . . . . . . . . . . . . . The Dataflow window menu bar . . . . . . Tracing HDL items with the Dataflow window . Saving the Dataflow window as a Postscript file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Wave window action list . . . . . . . . . . . . The Wave window menu bar . . . . . . . . . . . Wave window tool bar . . . . . . . . . . . . . Setting Wave window display properties . . . . . . Adding HDL items in the Wave window . . . . . . Editing and formatting HDL items in the Wave window Sorting a group of HDL items . . . . . . . . . . Finding items by name or value in the Wave window . Searching for item values in the Wave window . . . . Using time cursors in the Wave window . . . . . .
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Logic type display preferences . . . . . . . . . . . . . . . . . . . . . . . . . 228 Force mapping preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 ModelSim tools . . . The Button Adder The Macro Helper The Tcl Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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add button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 add list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 add_menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 add_menucb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 add_menuitem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 add_separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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down | up drivers echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 enablebp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 enable_menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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power report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 printenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 property list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 property wave pwd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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vcd checkpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 vcd comment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 vcd file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 vcd flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 vcd limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 vcd off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Project file variables [Library] section [vcom] section [vlog] section . [vsim] section . [lmc] section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11 - Standard Delay Format (SDF) Timing Annotation (p435) Specifying SDF files for simulation Instance specification . . . . SDF specification with the GUI Errors and warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 436 437 438 VHDL VITAL SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Using checkpoint/restore with the FLI . . . . . . . . . . . . . . . . . . . . . . . . 463 Support for Verilog instances . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Callback functions for sockets - Windows platforms VSIM function descriptions . . . Mapping to VHDL data types Enumerations . . . . . . . Reals and time . . . . . . Arrays . . . . . . . . . . VHDL FLI examples . . . . . . . . . . . . . . . . Using the Verilog PLI . . . . . . . Specifying the PLI file to load . .
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14 - Logic Modeling Library and Hardware Modeler (p501) VHDL SmartModel interface SM_ENTITY . . . . . Entity details . . . . . Architecture details . . . Vector ports . . . . . Simulation . . . . . . SPARCstation note . . . Command channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Technical support - electronic support services . . . . . . . . . . . . . . . . . . . . . 522 Technical support - other channels . . . . . . . . . . . . . . . . . . . . . . . . . 523 Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Licenses - ModelSim EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Online References . . . . Books and publications Partners . . . . . . Training partners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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C - Using the FLEXlm License Manager (p547) Starting the license server daemon . . . . . . . Locating the license file . . . . . . . . . . Controlling the license file search . . . . . . Manual start . . . . . . . . . . . . . . Automatic start at boot time . . . . . . . . What to do if another application uses FLEXlm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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- Table of Contents ModelSim EE/PLUS Reference Manual
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1 - Introduction Chapter contents Software versions . . . . . . . . . . . . . . . . . . 23 ModelSim’s graphic interface . . . . . . . . . . . . . . . . 24 Standards supported . . . . . . . . . . . . . . . . . . . 24 Assumptions . . . . . . . . . . . . . . . . . . . 25 Sections in this document . . . . . . . . . . . . . . . . . 25 Simulation action list . . . . . . . . . . . . . . . . .
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ModelSim’s graphic interface While your operating system interface provides the window-management frame, ModelSim controls all internal-window features including menus, buttons, and scroll bars.
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Assumptions Assumptions We assume that you are familiar with the use of your operating system. You should be familiar with the window management functions of your graphic interface: either OpenWindows, OSF/Motif, or Microsoft Windows NT/95/98. We also assume that you have a working knowledge of VHDL and Verilog. Although ModelSim is an excellent tool to use while learning HDL concepts and practices, this document is not written to support that goal. If you need more information about HDLs, check out our.
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6 - ModelSim EE Graphic Interface (p103) This chapter describes the graphic interface available while operating VSIM, the ModelSim simulator. ModelSim’s graphic interface is designed to provide consistency throughout all operating system environments. 7 - Simulator Command Reference (p245) The simulator commands used to control the VSIM simulator are described in this chapter. These commands are only valid after loading a design with the vsim command (p91) or the via the ModelSim graphical interface.
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Simulation action list Additional Tcl and Tk (Tcl’s toolkit) can be found through several Tcl online references (p514). A - Technical Support, Updates, and Licensing (p521) How and where to get tech support, updates and licensing for ModelSim. B - Tips and Techniques (p529) An extended collection of ModelSim usage examples taken from our manuals, and tech support solutions. C - Using the FLEXlm License Manager (p547) This appendix covers Model Technology’s application of FLEXlm for ModelSim licensing.
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Simulation step 4 - Simulate a design 5 - Advanced simulation options Refer to these chapters and their associated sections chapter 6 - Setting default simulation options (p207), and Simulator preference variables (p210) chapter 8 - Variable functions (p421) chapter 3 - Simulating VHDL and Verilog designs (p48) chapter 5 - vsim (p91) chapter 6 - Simulating with the graphic interface (p198) chapter 7 - run (p361), force (p319), and step (p371) chapter 9 - Using the TextIO package (p425) chap
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Text conventions Text conventions Text conventions used in this manual include: italic text provides emphasis and sets off file and path names bold text indicates commands, command options, and menu choices, as well as package and library logical names monospaced type monospace type is used for program and command examples The right angle (>) is used to connect menu choices when traversing menus as in: File > Save path separators examples will show either UNIX or Windows path separators - use sepa
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Where to find our documentation Model Technology’s documentation is available in the following formats and locations: Document Format How to get it Start Here for ModelSim (installation & support reference) paper shipped with ModelSim PDF online find "ee_start_here.pdf" in the "/ /docs" directory; also available from the Support page of our web site: www.model.com Documentation Index PDF online find "ee_doc_index.
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Comments Download a free PDF reader with Search Model Technology’s PDF documentation requires an Adobe Acrobat Reader for viewing. The Reader may be installed from the ModelSim CD. It is also available without cost from Adobe at http://www.adobe.com. Be sure to download the Acrobat Reader with Search to take advantage of the index file supplied with our reference manuals; the index makes searching the documentation much faster.
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ModelSim EE/PLUS Reference Manual Introduction - 32
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2 - Design Libraries Chapter contents Design library contents . . Design unit information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 . 34 Design library types . . . . . . . . . . . . . . . . . 34 Library management commands. . . . . . . . . . . . . . . . 35 Working with design libraries . . . . . Creating a library . . . . . . . Viewing and deleting library contents . . Assigning a logical name to a design library Moving a library . .
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Design library contents Design library contents A design library is a directory that serves as a repository for compiled design units. The design units contained in a design library consist of VHDL entities, packages, architectures, configurations, and Verilog modules and UDPs (user defined primitives). The design units are classed as follows: • Primary design units Consists of entities, package declarations, configuration declarations, modules, and UDPs.
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Library management commands Library management commands These library management commands are available from the UNIX/DOS command line, or from the ModelSim graphic interface. Only brief descriptions are provided here; for more information and command syntax see the "ModelSim Command Reference" (p67). Command Description vdel (p76) deletes a design unit from a specified library vdir (p78) selectively lists the contents of a library.
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Working with design libraries Creating a working library with the graphic interface To create a new library with the ModelSim graphic interface, use the Main VSIM window menu selection: Library > Create a New Library. This brings up a dialog box that allows you to specify the library name along with several mapping options. The Create a New Library dialog box includes these options: Create • a new library and a logical mapping to it Type the new library name into the Library field.
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Working with design libraries When you click OK, ModelSim creates the specified library directory and writes a specially-formatted file named _info into that directory. The _info file must remain in the directory to distinguish it as a ModelSim library. Note: It is important to remember that a design library is a special kind of directory; the only way to create a library is to use the ModelSim GUI, or the vlib command (p81). Do not create libraries using UNIX or Windows.
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Working with design libraries The Library Contents dialog box includes these options: • Library Select the library you wish to view from the drop-down list. • Name/Details list Entity/architecture pairs are indicated by a box prefix; select a plus (+) box to view the associated architecture, or select a minus (–) box to hide the architecture. You can delete a package, configuration, or entity by selecting it and clicking Delete. This will remove the design unit from the library.
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Working with design libraries Library mappings with the GUI To associate a logical name with a library, you select the Library > Browse Libraries command. This brings up a dialog box that allows you to view, add, edit, and delete mappings, as shown below: The Library Browser dialog box includes these options: • Show Choose the mapping and library scope to view from drop-down list. • Library/Type list To view the contents of a library Select the library, then click the View button.
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Working with design libraries To edit an existing library mapping Select the desired mapping entry, then click the Edit button. This brings up a dialog box that allows you to modify the logical library name and the pathname to which it is mapped. Selecting Delete removes an existing library mapping, but it does not delete the library (delete the library via UNIX, DOS, or Windows).
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Specifying the resource libraries Library search rules The system searches for the mapping of a logical name in the following order: • First the system looks for a modelsim.ini file. • If the system doesn’t find a modelsim.ini file, or if the specified logical name does not exist in the modelsim.ini file, the system searches the current working directory for a subdirectory that matches the logical name.
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Specifying the resource libraries Predefined libraries Certain resource libraries are predefined in standard VHDL. The library named std contains the packages standard and textio, which should not be modified. The contents of these packages and other aspects of the predefined language environment are documented in the IEEE Standard VHDL Language Reference Manual, Std 1076-1987 and ANSI/IEEE Std 1076-1993. See also, "Using the TextIO package" (p425).
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Specifying the resource libraries Rebuilding supplied libraries Resource libraries are supplied precompiled in the modeltech installation directory. If you need to rebuild these libraries, the sources are provided in the vhdl_src directory; shell scripts are also provided (rebuild_libs.csh and rebuild_libs.sh).
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Verilog resource libraries ModelSim supports and encourages separate compilation of distinct portions of a Verilog design. This approach provides more rapid simulation loading and much simpler commands to invoke the simulator. The VLOG compiler is used to compile one or more source files into a specified library. The library thus contains pre-compiled modules and UDPs (as well as VHDL design units) that are drawn from by the simulator as it loads the design. See "Instantiation bindings" (p51).
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3 - Compilation and Simulation Chapter contents Compiling VHDL and Verilog designs Creating a design library . . Invoking the VHDL compiler . Invoking the Verilog compiler . Design checking . . . . Dependency checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 . 46 . 46 . 47 . 47 . 47 Simulating VHDL and Verilog designs . . . . . . . Invoking the simulator from the Main transcript window . . . . . . . . . . . . . . 48 .
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Compiling VHDL and Verilog designs Compiling VHDL and Verilog designs Compiling is nothing new to VHDL simulation. Unlike most Verilog tools, however, ModelSim provides a compiled Verilog environment – a design is first compiled, and then simulated. This process provides significant speed improvement over an interpreted approach and yet maintains flexibility when you modify your design. You can compile a complete design or subset of a design in one or more invocations of the compiler.
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Compiling VHDL and Verilog designs modelsim.ini file (see "System Initialization/Project File" (p413) for more information). See "ModelSim Command Reference" (p67) for more information on the vcom command (p71). Invoking the Verilog compiler ModelSim compiles one or more Verilog design units (modules and UDPs) – in any combination – with a single invocation of vlog (p83), the Verilog compiler.
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Simulating VHDL and Verilog designs entity compilation results will remain unchanged and you will not have to recompile design units that depend on the entity. Simulating VHDL and Verilog designs After compiling the design units, you can proceed to simulate your designs with VSIM. This section includes a discussion of simulation from the UNIX or Windows/DOS command line. You can also use the graphic interface for simulation, see "Simulating with the graphic interface" (p198).
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Simulating VHDL and Verilog designs The default time resolution can also be changed by modifying the Resolution variable (p420) in the modelsim.ini file. You can view the current resolution by invoking the report command (p354) with the simulator state option. See "System Initialization/Project File" (p413) for more information on modifying the modelsim.ini file. VSIM will set the simulation time resolution to the minimum time precision specified by the ’timescale directives.
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Verilog-specific simulation issues VHDL By default, the timing checks within VITAL models are enabled. They are also disabled with the +notimingchecks option. For example: vsim +notimingchecks topmod Verilog-specific simulation issues Verilog object names in commands VERILOG By default, VSIM requires the "/" character as separators in hierarchical names. You can use the "." character instead by setting the PathSeparator variable (p254) to "." in the modelsim.ini file.
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Verilog-specific simulation issues You can use this feature to help you write code that ports more easily among Verilog simulators. VSIM matches the event ordering of Cadence's Verilog simulator in many, but not all, cases. VSIM's hazard detection is useful in porting models that rely on Cadence Verilog event ordering. The vsim command (p91) detects the following kinds of hazards: • WRITE/WRITE: Two processes writing to the same variable at the same time.
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Verilog-specific simulation issues • VSIM will search inferred libraries from any ‘uselib's in effect at compilation time. • VSIM will search libraries provided by any -L option provided on the VSIM command line. (See vsim (p91) for more information on the –L option.) • VSIM will examine the current work library. • If the referenced design unit is an escaped identifier of the form "library.name", it will search "library" for the design unit "name".
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Verilog-specific simulation issues into a specified library. The library thus contains pre-compiled modules and UDPs (as well as VHDL design units) that are drawn from by the simulator as it loads the design. Within a library, distinct modules/UDPs are distinguished by name. Thus it's not possible for two distinct parts to have the same name and at the same time in a single library. From the previous example, it's not possible for both vendors' NAND2 modules to exist within the same library.
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Environment variables The additional benefit of this option is that it also allows symbolic library names to be referenced and configured via ModelSim's vmap command (p89). Since this option is unlikely to be supported by other environments, it might be best to protect it with an ‘ifdef: ‘ifdef MODEL_TECH ‘uselib lib=vendorA_lib ‘else ‘uselib dir=/h/vendorA/FPGAlib libext=.
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Environment variables Variable Description MODEL_TECH_TCL used by VSIM to find Tcl libraries for: Tcl/Tk 8.0, Tix, and VSIM; defaults to /..
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Environment variables Once the variable is set, you can use it for library mappings in the following manner. If using the vmap command (p89) command from DOS prompt: vmap MY_VITAL %MY_PATH% If using vmap from ModelSim/VSIM prompt: vmap MY_VITAL \$MY_PATH (The "\" followed by a "$" will substitute the variable using Tcl syntax.) If you used DOS vmap, the modelsim.ini will appear as below. MY_VITAL = c:\temp\work If you used vmap from ModelSim/VSIM prompt, the modelsim.ini will appear as below.
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4 - Mixed VHDL and Verilog Designs Chapter contents Separate compilers, common libraries . . . . . . . . . . . . . . 58 Mapping data types . . . VHDL generics . . . Verilog parameters . . VHDL and Verilog ports Verilog states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 . 58 . 59 . 59 . 60 VHDL instantiation of Verilog design units. Verilog instantiation criteria . . . Component declaration . .
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Separate compilers, common libraries Separate compilers, common libraries VHDL source code is compiled by VCOM and the resulting compiled design units (entities, architectures, configurations, and packages) are stored in a library. Likewise, Verilog source code is compiled by VLOG and the resulting design units (modules and UDPs) are stored in a library.
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Mapping data types Type time is treated specially: the Verilog number is converted to a time value according to the ‘timescale directive of the module. Physical and enumeration types receive a value that corresponds to the position number indicated by the Verilog number. In VHDL this is equivalent to T'VAL(P), where T is the type, VAL is the predefined function attribute that returns a value given a position number, and P is the position number.
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Mapping data types full Verilog state set. For example, you may wish to convert between vl_logic and your own user-defined type. The vl_logic type is defined in the vl_types package in the pre-compiled verilog library. This library is provided in the installation directory along with the other pre-compiled libraries (std and ieee). The source code for the vl_types package can be found in the files installed with ModelSim. See "Installed technotes" (p28).
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Mapping data types Verilog std_logic bit St1 '1' '1' StX 'X' '0' Su0 '0' '0' Su1 '1' '1' SuX 'X' '0' For Verilog states with ambiguous strength: • bit receives '0' • std_logic receives 'X' if either the 0 or 1 strength components are greater than or equal to strong strength • std_logic receives 'W' if both the 0 and 1 strength components are less than strong strength VHDL type bit is mapped to Verilog states as follows: bit Verilog '0' St0 '1' St1 VHDL type std_logic is mapped to Ve
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VHDL instantiation of Verilog design units std_logic Verilog 'L' Pu0 'H' Pu1 '–' StX VHDL instantiation of Verilog design units Once you have generated a component declaration for a Verilog module, you can instantiate the component just like any other VHDL component. In addition, you can reference a Verilog module in the entity aspect of a component configuration – all you need to do is specify a module name instead of an entity name.
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VHDL instantiation of Verilog design units VHDL and Verilog identifiers The identifiers for the component name, port names, and generic names are the same as the Verilog identifiers for the module name, port names and parameter names. If a Verilog identifier is not a valid VHDL 1076-1987 identifier, it is converted to a VHDL 1076-1993 extended identifier (in which case you must compile the VHDL with the -93 switch).
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VHDL instantiation of Verilog design units Verilog identifier VHDL identifier TopMod \TopMod\ top_mod top_mod _topmod \_topmod\ \topmod topmod \\topmod\ \topmod\ vgencomp component declaration vgencomp (p79) generates a component declaration according to these rules: Generic clause A generic clause is generated if the module has parameters. A corresponding generic is defined for each parameter that has an initial value that does not depend on any other parameters.
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Verilog instantiation of VHDL design units A port clause is generated if the module has ports. A corresponding VHDL port is defined for each named Verilog port. The VHDL port type is selected by the user from among bit, std_logic, and vl_logic. If the Verilog port has a range, then the VHDL port type is bit_vector, std_logic_vector, or vl_logic_vector. If the range does not depend on parameters, then the vector type will be constrained accordingly, otherwise it will be unconstrained.
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Verilog instantiation of VHDL design units Port associations may be named or positional. Use the same port names and port positions that appear in the entity. Named port associations Named port associations are not case sensitive – unless a VHDL port name is an extended identifier (1076-1993). If the VHDL port is an extended identifier, the association is case sensitive and the VHDL identifier’s leading and trailing backslashes are removed before comparison.
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5 - ModelSim Command Reference The Model Technology system commands allow you to perform tasks such as creating and manipulating the contents of a HDL design library, compiling HDL source code, and invoking the VSIM simulator on a design unit. These commands are entered from the host operating system command line and must be in lower case.
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dumplog64 dumplog64 The dumplog64 command dumps the contents of the vsim.wav file in a readable format. Syntax dumplog64 Arguments The name of the dump file created. Required.
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modelsim modelsim The modelsim command starts the ModelSim GUI without prompting you to load a design. This command is valid only for Windows platforms, and may be invoke in one of two ways: • from the DOS prompt, or • from a ModelSim shortcut. To use modelsim arguments with a shortcut, add them to the target line of the shortcut’s properties. (Arguments work on the DOS command line too, of course.
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tssi2mti tssi2mti The tssi2mti command is used to convert a vector file in Summit Design Standard Events Format into a sequence of VSIM force (p319) and run (p361) commands. The stimulus is written to the standard output. The source code for tssi2mti is provided in the file tssi2mti.c in the examples directory.
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vcom vcom The vcom command is used to invoke VCOM, the Model Technology VHDL compiler. Use VCOM to compile VHDL source code into a specified working library (or to the work library by default). This command may also be invoked from within the simulator with all of the options shown below.
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vcom compiler to resolve ambiguous function overloading in favor of the explicit function definition. See additional discussion in the examples. -f Specifies a file with more command line arguments. Allows complex arguments to be reused without retyping. Optional. -just eapbc Directs the compiler to “just” include: e - entities a - architectures p - packages b - bodies c - configurations Any combination in any order can be used, but one choice is required if you use this optional switch.
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vcom -nodebug[=ports] Hides the internal data of the compiled design unit. Optional. The design unit’s source code, internal structure, signals, processes, and variables will not display in ModelSim’s windows. In addition, none of the hidden objects may be accessed through the Dataflow window or with VSIM commands. This also means that you cannot set breakpoints or single step within this code. Don’t compile with this switch until you’re done debugging.
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vcom -quiet Disable 'loading' messages. Optional. -refresh Regenerates a library image. Optional. By default, the work library is updated; use -work to update a different library. See vcom "Examples" (p74) for more information. -s Instructs the compiler not to load the standard package. Optional. This argument should only be used if you are compiling the standard package itself. -source Displays the associated line of source code before each error message that is generated during compilation.
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vcom vcom -nodebug example.vhd Hides the internal data of example.vhd. Models compiled with -nodebug cannot use any of the ModelSim debugging features; any subsequent user will not be able to see into the model. vcom -nodebug=ports level3.vhd levle2.vhd vcom -nodebug top.vhd The first line compiles and hides the internal data, plus the ports, of the lower-level design units, level3.vhd and level2.vhd. The second line compiles the top-level unit, top.vhd, without hiding the ports.
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vdel vdel The vdel command deletes a design unit from a specified library. Syntax vdel [-help] [-verbose] [-lib ] [-all] | [ ...] Arguments -help Displays the command’s options and arguments. Optional. -verbose Displays progress message. Optional. -lib Specifies the logical name or pathname of the library that holds the design unit to be deleted. Optional; by default, the design unit is deleted from the work library. -all Deletes an entire library.
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vdel Examples vdel -all Deletes the work library. vdel -lib synopsys -all Deletes the synopsys library. vdel xor Deletes the entity named xor and all its architectures from the work library. vdel xor behavior Deletes the architecture named behavior of the entity xor from the work library. vdel base Deletes the package named base from the work library.
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vdir vdir The vdir command selectively lists the contents of a design library. Syntax vdir [ -help ] [-l] [ -lib ] [ ] Arguments -help Displays the command’s options and arguments. Optional. -l Prints the version of vcom or vlog that each design unit was compiled under. Also prints the object-code version number that indicates which versions of vcom/vlog and ModelSim are compatible.
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vgencomp vgencomp Once a Verilog module is compiled into a library, you can use the vgencomp command to write its equivalent VHDL component declaration to standard output. Optional switches allow you to generate bit or vl_logic port types; std_logic port types are generated by default. Syntax vgencomp [ -help ] [ - ] [ -s ] [ -b ] [ -v ] Arguments -help Displays the command’s options and arguments. Optional. - Specifies the pathname of the working library.
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vgencomp Examples This example uses a Verilog module that is compiled into the work library. The module begins as Verilog source code: module top(i1, o1, o2, io1); parameter width = 8; parameter delay = 4.5; parameter filename = "file.
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vlib vlib The vlib command creates a design library. Syntax vlib [ -help ] [ -dos | -short ] [ -unix | -long ] Arguments -help Displays the command’s options and arguments. Optional. -dos Specifies that subdirectories in a library have names that are compatible with DOS. Not recommended if you use the vmake (p88) utility. Optional. Default for ModelSim PE. -short Interchangeable with the -dos argument. Optional.
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vlib Examples vlib design Creates the design library called design. You can define a logical name for the library using the vmap command (p89) or by adding a line to the library section of the modelsim.ini file that is located in the same directory. The vlib command must be used to create a library directory. Operating system commands cannot be used to create a library directory or index file.
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vlog vlog The vlog command is used to invoke VLOG, the Model Technology Verilog compiler. Use vcom (p71) to compile Verilog source code into a specified working library (or to the work library by default). The vlog command is used just like vcom (p71), except that you do not need to compile a module before it is referenced (unless the module is referenced from VHDL). This command may also be invoked from within the simulator with all of the options shown below.
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vlog +libext+ Specifies the suffix of files in library directory. Multiple suffixes may be used, for example: +libext+.v+.u. Optional. +librescan Scan libraries in command-line order for all unresolved modules. Optional. -line Specify the starting line number. Optional. +incdir+ Search directory for files included with the ‘include filename compiler directive. Optional. -nodebug[=ports | =pli] Hides the internal data of the compiled design unit. Optional.
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vlog -R Causes VSIM to be invoked on the top-level Verilog modules immediately following compilation. VSIM is invoked with the arguments specified by (any arguments available for vsim (p91)). -refresh Regenerates a library image. Optional. By default, the work library is updated; use -work to update a different library. See vlog examples for more information. -source Displays the associated line of source code before each error message that is generated during compilation.
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vlog Specifies the name of the Verilog source code file to compile. One filename is required. Multiple filenames can be entered separated by spaces. Examples vlog example.vlg The example compiles the Verilog source code contained in the file example.vlg. vcom -nodebug example.v Hides the internal data of example.v. Models compiled with -nodebug cannot use any of the ModelSim debugging features; any subsequent user will not be able to see into the model. vcom -nodebug=ports level3.v levle2.
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vlog implies filenames with a .v or .u suffix (any combination of suffixes may be used). Only referenced definitions will be compiled. vlog -work mylib -refresh The -work option specifies mylib as the library to regenerate. -refresh rebuilds the library image without using source code, allowing models delivered as compiled libraries without source code to be rebuilt for a specific release of ModelSim (4.6 and later only).
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vmake vmake The vmake utility allows you to use a UNIX or Windows MAKE program to maintain libraries. The vmake utility is run on a compiled design library, and outputs a makefile that can be used to reconstruct the library.The resulting makefile can then be run with a version of MAKE (not supplied with ModelSim); a MAKE program is included with Microsoft’s Visual C/C++, as well as many other program development environments.
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vmap vmap The vmap command defines a mapping between a logical library name and a directory by modifying the modelsim.ini file. It also can be used to display all known mappings or just the current mapping of a specified logical name. Syntax vmap [-help] [-c] [-del] [] [] Arguments -help Displays the command’s options and arguments. Optional. -c Copies the default modelsim.ini file from the ModelSim installation directory to the current directory. Optional.
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vmap Examples vmap design /modelsim/designs/wrg101 Establishes the logical name design and maps it to the directory /modelsim/designs/ wrg101. vmap Without any arguments, the vmap command displays all current mappings (based on the contents of the current project file, the modelsim.ini file). vmap my_asic If just a logical name is given, the vmap command will display the current mapping. vmap -del old_asic Used with the -del option, vmap deletes a mapping from the current project file.
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vsim vsim The vsim command is used to invoke the VSIM simulator, or to view the results of a previous simulation run (when invoked with the -view switch). You can specify a configuration, an entity/architecture pair, or a module for simulation. If a configuration is specified, it is invalid to specify an architecture. If all arguments are omitted, the Load Design dialog box appears. During elaboration VSIM determines if the source has been modified since the last compile.
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vsim Arguments, VHDL and Verilog -help Displays the command’s options and arguments. Optional. -c Specifies that the simulator is to be run in command line mode. Optional. If used, must be the first argument. Also see "Running command-line and batch-mode simulations" (p532) for more information. -i Specifies that the simulator is to be run in interactive mode. Optional. If used, must be the first argument.
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vsim Description -lic_nomgc excludes any MGC licenses from the search -lic_nomti excludes any MTI licenses from the search -lic_vlog searches only for ModelSim EE/VLOG licenses -lic_vhdl searches only for ModelSim EE/VHDL licenses -lic_plus searches only for ModelSim EE/PLUS licenses -lic_noqueue do not wait in queue when license is unavailable The options may also be specified with the License variable (p420) in the modelsim.
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vsim -restore Specifies that VSIM is to restore a simulation saved with the checkpoint command (p291). Optional. Use the -nocompress switch (above) if compression was turned off when the checkpoint command (p291) was used or if VSIM was initially invoked with nocompress. See additional discussion in "How to use checkpoint/restore" (p530); nocompress is also an option of the restore command (p357).
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vsim -trace_foreign Creates two kinds of foreign interface traces: a log of what functions were called, with the value of the arguments, and the results returned; and a set of C-language files to replay what the foreign interface side did. The purpose of the log file is to aid the debugging of your FLI and/or PLI code.
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vsim Note: Make sure the Value you specify is appropriate for the declared data type. Type mismatches will cause the specification to be ignored (including no error messages). No spaces are allowed anywhere in the specification, except within quotes when specifying a string value. Multiple -g options are allowed, one for each generic parameter. Name may be prefixed with a relative or absolute hierarchical path to select generics in an instance-specific manner.
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vsim Name may be prefixed with a relative or absolute hierarchical path to select generics in an instance-specific manner. For example, Specifying -G/top/u1/tpd=20ns on the command line would only affect the tpd generic on the /top/u1 instance, overriding it with a value of 20ns. Specifying -Gu1/tpd=20ns affects the tpd generic on all instances named u1. Specifying -Gtpd=20ns affects all generics named tpd. If more than one -G option selects a given generic the most explicit specification takes precedence.
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vsim -vital2.2b Select SDF mapping for VITAL 2.2b (default is VITAL 95). Optional. Arguments, Verilog -hazards Enables hazard checking in Verilog modules. Optional. -L ... Specifies the design library to search for the specified configuration, entity or module. Optional, if omitted the work library is used. If multiple libraries are specified, each must be preceded by the -L option. -Lf ... Same as -L but libraries are searched before ‘uselib. Optional.
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vsim -pli "