Technical data

ModelSim EE Tutorial ModelSim EE Lessons -
91
3 -
Model
Sim
EE Lessons
Chapter contents
Choose the lessons appropriate for your simulator version:
PLUS, and VHDL lessons
Basic VHDL simulation . . . . . . . . . . . . . . . . 94
Debugging a VHDL design. . . . . . . . . . . . . . . 103
Running a batch-mode simulation . . . . . . . . . . . . . 112
Executing commands at startup. . . . . . . . . . . . . . 114
Tcl/Tk and ModelSim . . . . . . . . . . . . . . . . 115
PLUS, and VLOG lesson
Basic Verilog simulation . . . . . . . . . . . . . . . 129
PLUS lesson
Mixed VHDL/Verilog simulation . . . . . . . . . . . . . 143
PLUS, VHDL, and VLOG practice
Finding names, and searching for values . . . . . . . . . . . 150
Using the Wave window . . . . . . . . . . . . . . . 153
Assumptions
We assume that you are familiar with the your platform’s operating system and
graphical interface. Preparation for some of the examples leaves certain details up
to you - you will decide the best way to create directories, copy files and execute
programs within your operating system. (When you are operating the simulator
within Model
Sim
’s GUI, the interface is consistent for all platforms.)
We also assume that you have a working knowledge of HDL design. Although
Model
Sim
is an excellent tool to use while learning HDL concepts and practices,
this guide is not written to support that goal.
Additional details for VHDL, Verilog, and mixed VHDL/Verilog simulation can
be found in the
ModelSim EE/PLUS Reference Manual
. (See "Where to find our
documentation" (p15).)
Examples may show either UNIX or Windows path separators - use separators
appropriate for your operating system when trying the examples.