Technical data

ModelSim EE Tutorial Index -
167
Index
A
Assertion errors 105
B
Breakpoints
continuing simulation after
101
deleting
61
setting
61
viewing
61
C
Compile
the order of Verilog modules
132
Verilog
129
VHDL
95
Conventions
text and command syntax
14
Cursors
adding and deleting in the Wave window
87
D
Dataflow window (see also, Windows) 35
Debugging a VHDL design
103
Delay
specifying stimulus delay
58
Delta
collapse deltas in the List window
42
Descriptions of HDL items
65
Design hierarchy
viewing in Structure window
67
Design library
creating for Verilog
130
creating for VHDL
95
Design units
viewing hierarchy
22
DO files
executing a DO file in batch-mode
112
using a DO file at startup
114
using the transcript as a DO file
E
Editing
in notepad windows
33
in the Main window
33
in the Source window
33
Email
Model Technology’s email address
16
Errors
breaking on assertion
106
finding in VHDL design
105
viewing in Source window
107
examples
Tcl example solutions
120
F
Finding
a cursor in the Wave window
87
,
154
a marker in the List window
50
Finding names, and searching for values in windows
21
,
150
H
HDL items
defined
14
Hierarchy
of a mixed VHDL/Verilog design
147