Technical data

Mixed VHDL/Verilog simulation
ModelSim EE Tutorial ModelSim EE Lessons
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147
9
This time you will use the VSIM command line to add all of the HDL items in the
region to the List and Wave windows:
add list *
add wave *
(Signals MENU: View > List > Signals in Region)
(Signals MENU: View > Wave > Signals in Region)
10
Take a look at the Structure window.
Notice the hierarchical mixture of VHDL and Verilog in the design. VHDL levels
are indicated by a square “prefix”, while Verilog levels are indicated by a circle
“prefix.” Try expanding (+) and contracting (-) the structure layers. You’ll find
Verilog modules have been instantiated by VHDL architectures, and similar
instantiations of VHDL items by Verilog.
Let’s take another look at the design.
11
In the Structure window, click on the Verilog module
c: cache
. The source code for the Verilog module is
now shown in the Source window.