Technical data

Mixed VHDL/Verilog simulation
146
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ModelSim EE Lessons ModelSim EE Tutorial
6
Depending on the design, the compile order of VHDL files can be very specific. In the
case of this lesson, the file
top.vhd
must be compiled last.
Stay in the Compile HDL Source Files dialog box and compile the VHDL files in
this order (this invokes the VHDL compiler,
vcom
):
•
util.vhd
•
set.vhd
• top.vhd
Compiling is now complete, click
Done
to dismiss the dialog box.
7
Now it’s time to simulate. Start the simulator by selecting the
Load Design
button
from the Main toolbar:
(PROMPT: vsim top)
This returns the Load Design dialog box.
On the Design tab select the
top
entity and click
Load
.
8
From the Main menu select
View > All
to open all Model
Sim
windows.
(PROMPT: view *)