Technical data

Mixed VHDL/Verilog simulation
ModelSim EE Tutorial ModelSim EE Lessons
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145
This opens the Edit Library
dialog box; where you can
set the library mapping
between work and mixed.
Type
mixed
into the
Path:
field, then click
OK
. Now
you’re ready to compile the
design.
5
Compile the HDL files by selecting the
Compile
button on the toolbar:
(PROMPT: vlog cache.v memory.v proc.v)
(PROMPT: vcom util.vhd set.vhd top.vhd)
This opens the Compile HDL Source Files dialog box.
A group of Verilog files
can be compiled in any
order. Note, however, in
a mixed VHDL/Verilog
design the Verilog files
must be compiled before
the VHDL files.
Compile the source, by
double-clicking each of
these Verilog files in the
file list (this invokes the
Verilog compiler,
vlog
):
• cache.v
•
memory.v
• proc.v