Technical data

Mixed VHDL/Verilog simulation

ModelSim EE Tutorial ModelSim EE Lessons

143

Mixed VHDL/Verilog simulation

You must be using Model

Sim

EE/PLUS for this lesson.

The goals for this lesson are:

• compile multiple VHDL and Verilog files

• simulate a mixed VHDL and Verilog design

• list VHDL signals and Verilog nets and registers

• view the design in the Structure window

• view the HDL source code in the Source window

First, return to the directory you created in "Basic VHDL simulation" (p94).

cd <directory_name>

Next copy the VHDL and Verilog example files to the directory:

<install_dir>/<modelsim_dir>/examples/mixedHDL/*.vhd

<install_dir>/<modelsim_dir>/examples/mixedHDL/*.v

Start ModelSim with this command from the UNIX/DOS prompt (or

modelsim.exe

for

Windows):

vsim -gui

This opens the Model

Sim

Main window without loading a design.