Technical data

Basic Verilog simulation
132
-
ModelSim EE Lessons ModelSim EE Tutorial
Note:
The order in which you compile the two Verilog modules is not important. This may again seem
strange to Verilog XL users who understand the possible problems of interface checking between design
units, or compiler directive inheritance. Model
Sim
defers such checks until the design is loaded by VSIM (the
HDL simulator). So it doesn't matter here if you choose to compile
counter.v
before or after
tcounter.v
.
6
Start the simulator by selecting the
Load Design
button from the toolbar:
(PROMPT: vsim test_counter)
The Load Design dialog box comes up, as shown below.