Technical data

Basic Verilog simulation
ModelSim EE Tutorial ModelSim EE Lessons
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131
Note:
Remember, a library directory should not be created using UNIX/DOS commands - always use the
Main Library menu or the
vlib
command.
Next, you’ll compile the Verilog design.
The example design consists of two Verilog source files, each containing a unique
module. The file
counter.v
contains a module called
counter
, which implements
a simple 8-bit binary up-counter. The other file,
tcounter.v
, is a testbench module
(
test_counter
) used to verify
counter
. Under simulation you will see that these
two files are configured hierarchically with a single instance (instance name
dut
)
of module
counter
instantiated by the testbench. You'll get a chance to look at the
structure of this code later. For now, you need to compile both files into the
work
design library.
5
Compile the
counter.v
, and
tcounter.v
files into the
work
library by selecting the
Compile
button on the toolbar:
(PROMPT: vlog counter.v)
This opens the Compile HDL Source Files dialog box.
Complete the
compilation by
selecting both files.
Control+click
(left
mouse button) on
counter.v
, then
tcounter.v
from the
file list and choose
Compile
, then
Done
.