Technical data

Basic Verilog simulation
ModelSim EE Tutorial ModelSim EE Lessons
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129
Basic Verilog simulation
You must be using Model
Sim
EE/PLUS or Model
Sim
EE/VLOG for this lesson.
The goals for this lesson are:
• compile a Verilog design
• examine the hierarchy of the design
• list signals in the design
• change list attributes
• set a breakpoint
• add and remove cursors in the waveform display
If you’ve completed any previous VHDL lesson you’ll notice that the Verilog and
VHDL simulation processes are almost identical.
1
Create, and change to a new directory to make it the current directory.
2
Copy the Verilog files from the
/<install_dir>/<modelsim_dir>/examples
directory
into the current directory.
Before you can compile a Verilog design, you need to create a design library in
the new directory. If you are only familiar with interpreted Verilog simulators
such as Cadence Verilog XL this will be a new idea for you. Since Model
Sim
is a
compiled Verilog, it requires a target design library for the compilation. Model
Sim
can compile both VHDL and Verilog code into the same library if desired.
3
Invoke ModelSim:
for UNIX at the shell prompt:
vsim -gui
for Windows - your option - DOS prompt, shortcut, or Start menu:
modelsim.exe
This opens the Model
Sim
Main window without loading a design.