Technical data

Debugging a VHDL design
ModelSim EE Tutorial ModelSim EE Lessons
-
103
Debugging a VHDL design
The goals for this lesson are:
• show an example of a VHDL testbench - a VHDL architecture that instantiates
the VHDL design units to be tested, provides simulation stimuli, and checks the
results
• map a logical library name to an actual library
• change the default run length
• recognize assertion messages in the command window
• change the assertion break level
• restart the simulation run using the
restart
command
• examine composite types displayed in the VSIM Variables window
• change the value of a variable
• use a strobe to trigger lines in the VSIM List window
• change the radix of signals displayed in the VSIM List window
1
Return to the directory you created in "Basic VHDL simulation" (p94), and invoke
Model
Sim
:
for UNIX at the shell prompt:
vsim -gui
for Windows - your option - from the DOS prompt, a shortcut, or the Start menu:
modelsim.exe
2
Enter the following command at the Model
Sim
prompt to create the a new library:
vlib library_2
3
Compile the source files into the new library by entering this command at the system
prompt:
vcom -work library_2 gates.vhd adder.vhd testadder.vhd
4
Now let’s map the new library to the work library. To create a mapping you can edit
the [Library] section of the
modelsim.ini
file, or you can create a logical library name
with the
vmap
command:
vmap work library_2