Technical data

GUI_expression_format
CR-252 Command Syntax and Conventions ModelSim EE/SE Command Reference
&{<signalOrSliceName1>, <signalOrSliceName2>, ... }
&{<count>{<signalOrSliceName1>}, <signalOrSliceName2>, ... }
&{<count>{<signalOrSliceName1>}, <signalOrSliceName2>, ...}, ... }
The concatenation directive (as illustrated below) can be used to constrain the
resulting array range of a concatenation or influence how compound objects are
treated. By default, the concatenation will be created with descending index range
from (n-1) to 0, where n is the number of elements in the array. The "range"
directive completely specifies the index range. The "ascending" directive
specifies that the index start at zero and increment upwards, and the "descending"
directive specifies (n-1) downto 0.
Concatenation directives
(range [31:0])<concatenationExpr> # Verilog syntax
(range (31 downto 0))<concatenationExpr> # VHDL syntax
(ascending) <concatenationExpr>
(descending)<concatenationExpr>
(flatten)<concatenationExpr> # no hierarchy
Examples in Verilog and VHDL syntax:
top.chip.vlogsig
/top/chip/vhdlsig
vlogsig[3]
vhdlsig(9)
vlogsig[5:2]
vhdlsig(5 downto 2)
VHDL record field support
Arbitrarily-nested arrays and records are supported, but operators will only
operate on one field at a time. That is, the expression {a == b} where a and b are
records with multiple fields, is not supported. This would have to be expressed as:
{(a.f1 == b.f1) && (a.f2 == b.f2)...}
Examples:
vhdlsig.field1
vhdlsig.field1.subfield1
vhdlsig.(5).field3
vhdlsig.field4(3 downto 0)
Grouping and precedence
Operator precedence generally follows that of the C language, but we recommend
liberal use of parentheses.