Technical data

GUI_expression_format
ModelSim EE/SE Command Reference Command Syntax and Conventions CR-251
either UNSIGNED or SIGNED, as in the IEEE std_logic_arith package.
Normally, referencing a signal array causes it to be treated as UNSIGNED by the
expression evaluator; to cause it to be treated as SIGNED, use casting as described
below. Numeric operations supported on arrays are performed by the expression
evaluator via ModelSim’s built-in numeric_standard (and similar) package
routines. The expression evaluator selects the appropriate numeric routine based
on SIGNED or UNSIGNED properties of the array arguments and the result.
The enumeration types supported are any VHDL enumerated type. Enumeration
literals may be used in the expression as long as some variable of that enumeration
type is referenced in the expression. This is useful for subexpressions of the form:
(/memory/state == reading)
Signal and sub-element naming conventions
ModelSim supports naming conventions for VHDL and Verilog signal pathnames,
VHDL array indexing, Verilog bit selection, VHDL subrange specification, and
Verilog part selection.
Concatenation of signals and/or sub-elements
Elements in the concatenation that are arrays are expanded so that each element in
the array becomes a top-level element of the concatenation. But for elements in
the concatenation that are records, the entire record becomes one top-level
element in the result. To specify that the records be broken down so that their
subelements become top-level elements in the concatenation, use the "flatten"
directive. Currently we do not support leaving full arrays as elements in the result.
(Please let us know if you need that option.)
If the elements being concatenated are of incompatible base type, a VHDL-style
record will be created. The record object can be expanded in the signals and wave
window just like an array of compatible type elements.
Concatenation syntax for VHDL
<signalOrSliceName1> & <signalOrSliceName2> & ...
Note that the concatenation syntax (below) begins with "&{" rather than just "{".
Repetition multipliers are supported, as illustrated in the second line. The third
line shows that the repetition element itself may be an arbitrary concatenation
subexpression.
Concatenation syntax for Verilog