Technical data

HDL item pathnames
ModelSim EE/SE Command Reference Command Syntax and Conventions CR-247
Names in VSIM commands are case sensitive when matched against case
sensitive identifiers, otherwise they are not case sensitive.
Extended identifiers
The following are supported formats for extended identifiers for any command
that takes an identifier.
{\ext ident!\ } # Note trailing space. Compatible with 5.2
\\ext\ ident\!\\ # All non-alpha characters escaped
Naming fields in VHDL signals
Fields in VHDL record signals can be specified using the form:
signal_name.field_name
Examples:
Syntax Description
clk specifies the item clk in the current environment
/top/clk specifies the item clk in the top-level design unit.
/top/block1/u2/clk specifies the item clk, two levels down from the top-level design unit
block1/u2/clk specifies the item clk, two levels down from the current environment
array_sig(4) specifies an index of an array item
array_sig(1 to 10) specifies a slice of an array item in VHDL syntax
mysignal(31:0) specifies a slice of an array item in partial Verilog syntax
record_sig.field specifies a field of a record