Technical data

HDL item pathnames
ModelSim EE/SE Command Reference Command Syntax and Conventions CR-245
Verilog numbering conventions
Verilog numbers are expressed in the style:
[ - ] [ size ] [ base ] value
Examples
‘b11111110
8‘b11111110
‘Hffca23
21‘H1fca23
-23749
HDL item pathnames
VHDL and Verilog items are organized hierarchically. Each of the following HDL
items creates a new level in the hierarchy:
• VHDL
component instantiation statement, block statement, and package
• Verilog
module instantiation, named fork, named begin, task and function
Multiple levels in a pathname
Multiple levels in a pathname are separated by the character specified in the
PathSeparator variable. The default is "/", but it can be set to any single character,
such as "." for Verilog naming conventions, or ":" for VHDL IEEE 1076-1993
naming conventions. See the PathSeparator
(B-400) for more information.
Element Description
- indicates a negative number; optional
size the number of bits in the number; optional
base specifies the base; binary: ‘b or ‘B, octal: ‘o or ‘O, decimal: ‘d or ‘D, hex:
‘h or ‘H; optional
value specifies digits in appropriate base with optional underscore separators;
default is decimal, required