Technical data

vsim
ModelSim EE/SE Command Reference ModelSim Commands CR-211
+no_tchk_msg
Disables timing constraint error messages. Optional.
+notimingchecks
Disables Verilog and VITAL timing checks for faster simulation. Optional. By
default, Verilog timing check system tasks ($setup, $hold,...) in specify blocks are
enabled. For VITAL, the timing check default is controlled by the ASIC or FPGA
vendor, but most default to enabled.
-quiet
Disable ’loading’ messages during batch-mode simulation. Optional.
-restore <filename>
Specifies that VSIM is to restore a simulation saved with the checkpoint
command
(CR-53). Optional. Use the -nocompress switch (above) if compression
was turned off when the checkpoint command
(CR-53) was used or if VSIM was
initially invoked with -nocompress. See additional discussion in "How to use
checkpoint/restore"
(E-438); -nocompress is also an option of the restore
command
(CR-134).
-sdfmin | -sdftyp | -sdfmax [<instance>=]<sdf_filename>
Annotates VITAL or Verilog cells in the specified SDF file (a Standard Delay
Format file) with minimum, typical, or maximum timing. Optional. The use of
[<instance>=] with <sdf_filename> is also optional.; this is used when the back
annotation it is not being done at the top level. See "Specifying SDF files for
simulation"
(11-282).
-sdfnoerror
Errors issued by the SDF annotator while loading the design prevent the
simulation from continuing, whereas warnings do not. Changes SDF errors to
warnings so that the simulation can continue. Optional.
-sdfnowarn
Disables warnings from the SDF reader. Optional.
See Chapter 4 - VHDL Simulation for an additional discussion of SDF.
+sdf_verbose
Turns on the verbose mode during SDF annotation. The Main window transcript
provides detailed warnings and summaries of the current annotation. Optional.
-t [<multiplier>]<time_unit>
Specifies the simulation time resolution. Optional; if omitted, the value specified
by the Resolution
(B-400) in the modelsim.ini file will be used. If Verilog