Technical data
vlog
ModelSim EE/SE Command Reference ModelSim Commands CR-201
cannot set breakpoints or single step within this code. Don’t compile with this
switch until you’re done debugging.
Note that this is not a speed switch like the “nodebug” option on many other
products.
The optional =ports switch hides the ports for the lower levels of your design; it
should only be used to compile the lower levels of the design. If you hide the ports
of the top level you will not be able to simulate the design.
The optional =pli switch prevents the use of pli functions to interrogate individual
modules for information; this switch may be used at any level of the design.
Combine both switches with =ports+pli or =pli+ports.
Note: -nodebug provides protection for proprietary model information. The Verilog ’protect compiler
directive provides similar protection, but uses a Cadence encryption algorithm that is unavailable to Model
Technology.
See additional discussion in "Source code security and -nodebug"
(E-443).
+nolibcell
Do not automatically define library modules as cells. Optional.
-nolock
Overrides the library lock file. The lock file prevents mulitple users from
concurrently accessing the same library. If you are a single user, disabling the lock
file should not present a problem. Optional. Default is locked.
-O0 | -O1 | -O4 | -O5
Lower the optimization to a minimum with -O0 (capital oh zero). Optional. Use
this to work around bugs, increase your debugging visibility on a specific cell, or
when you want to place breakpoints on source lines that have been optimized out.
Enable PE-level optimization with -O1. Optional.
Enable standard EE optimizations with -O4. Default.
Enable maximum optimization with -O5. Optional. Use caution with this switch.
We recommend use of this switch with large sequential blocks only, other uses
may signifcantly increase compile times. Optional.
-quiet
Disables 'loading' messages. Optional.