Technical data

virtual function
ModelSim EE/SE Command Reference ModelSim Commands CR-185
<name>
The name you define for the virtual signal. Required. Case is ignored unless
installed in a Verilog region. It is recommended to use alpha, numeric and
underscore characters only. Or, use VHDL extended identifier notation, in which
case <name> needs to be quoted with double quotes or with curly braces.
Examples
virtual function { not /chip/section1/clk } clk_n
Creates a signal /chip/section1/clk_n which is the inverse of /chip/section1/clk.
virtual function -install /chip { (std_logic_vector) chip.vlog.rega } rega_slv
Creates a std_logic_vector equivalent of a verilog register "rega" and installs it as
/chip/rega_slv.
virtual function { /chip/addr[11:0] == 0xfab } addr_eq_fab
Creates a boolean signal /chip/addr_eq_fab that is true when /chip/addr[11:0] is
equal to hex "fab", and false otherwise. It is ok to mix VHDL signal path notation
with Verilog part-select notation.
virtual function { gate:/chip/siga XOR rtl:/chip/siga) } siga_diff
Creates a signal that is non-zero only high during times at which a signal /chip/
siga of the gate-level version of a design does not match /chip/siga of the rtl
version of a design. Because there is no common design region for the inputs to
the expression, siga_diff is installed in region virtuals:/Functions. The virtual
function siga_diff can be added to the wave window, and when expanded will
show the two original signals that are being compared.
virtual function { | (gate:/chip/outbus XOR rtl:/chip/outbus) } outbus_diff
This example creates a one-bit signal "outbus_diff" which is non-zero during
times at which any bit of a vector signal /chip/outbus of the gate-level version of
a design does not match the corresponding bit of the signal in the rtl version of a
design.
This expression uses the "OR-reduction" operator, which takes the logical OR of
all the bits of the vector argument.
The following is an example of a series of commands that reconstruct a bus in a
gate level design, and creates a comparison between a gate and RTL design:
virtual signal -env gate:chip { (range 7:0)&{a_07, a_06, a_05, a_04, a_03, a_02,