Technical data

vcd file

CR-164 ModelSim Commands ModelSim EE/SE Command Reference

-map <mapping pairs>

Affects only VHDL signals of type std_logic. Optional. It allows you to override

the default mappings. The mapping is specified as a list of character pairs. The

first character in a pair must be one of the std_logic characters UX01ZWLH- and

the second character is the character you wish to be recorded in the VCD file. For

example, to map L and H to z:

vcd file -map "L z H z"

Note that the quotes in the example above are a Tcl convention for command

strings that include spaces.

-direction

Affects only VHDL ports. Optional. It specifies that the variable type recorded in

the VCD header for VHDL ports shall be one of the following:

in, out, inout, internal, ports (includes in, out, and inout); the default is all ports

This option results in a non-standard VCD file, but is necessary if the VCD file is

to be used to stimulate a VHDL design with the vsim command

(CR-208) with the

-vcdread option.

Note that the port type is specified with options to the vcd add command

(CR-160)

when the VCD file is created.

-dumpports

Capture detailed port driver data for Verilog ports and VHDL std_logic ports.

Optional. This option only works on ports, and subsequent vcd add

(CR-160) will

only accept qualifying ports (silently ignoring all other specified items).