Technical data

Debugging a VHDL design
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Tutorial: Using ModelSim PE Getting Started with ModelSim PE
Step 13.
Select the Design tab and perform the following steps:
• make sure that the simulator resolution is
ns
• look in the design unit scrollbox and select the configuration named
test_adder_structural
(because this design unit is a configuration, no architectures are
displayed in the architecture scrollbox at the bottom of the dialog)
• click
OK
to accept the settings
Now open the other eight Model
Sim
windows with the
View > All
menu sequence. The
windows will appear in the sizes and positions in which we left them in the previous lesson.
We’ll first use the Source and Structure windows to examine the design.
Step 14.
Double-click in the title bar of the Structure window to maximize it. Model
Sim
automatically
generates this view from your VHDL code. Click on the minus sign in the box for
testbench(adder8)
at the top level.
Now you can explore the design by collapsing and expanding the levels of hierarchy shown in
the window. A level of hierarchy is created by each component instantiation, generate
statement, block statement, and package.