Technical data

Debugging a VHDL design

Tutorial: Using ModelSim PE Getting Started with ModelSim PE

And four, you could compile multiple files using a single

vcom

command, as in the following

example:

vcom gates.vhd adder.vhd testadd.vhd

Let’s use the tool bar and the Compile VHDL Source dialogue box. Press the

VCOM

button

on the tool bar.

Step 9.

Once you have the Compile VHDL Source dialog box on the screen, note the Compile More

check box.

When Compile More is checked, the dialog box stays open until you click on Done. If the box

is unchecked, each time you compile, the dialog box is closed. This is handy on smaller screens

because then you can see the compiler messages in the Transcript window.

Check

Compile More

now.

Now compile the source files. Note that the order you do this is important because

testadd.vhd

uses

adder.vhd

and

adder.vhd

in turn uses

gates.vhd

, so compile them in this order:

• gates.vhd

• adder.vhd

• testadd.vhd

When you’re finished, click

Done