Technical data

Debugging a VHDL design
Getting Started with ModelSim PE Tutorial: Using ModelSim PE
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93
Debugging a VHDL design
The goals for this lesson are:
• use a VHDL testbench (a
testbench
is a VHDL architecture that instantiates the VHDL
design units to be tested, provides simulation stimuli, and checks the results)
• map a logical library name to an actual library
• change the default run length
• recognize assertion messages in the command window
• change the assertion break level
• restart the simulation run using the
restart
command
• change the value of a variable
• use a strobe to trigger lines in the Model
Sim
List window
• list signals in different radixes in the List window
Step 1.
Restart Model
Sim
if necessary, then change to the tutorial file directory by pulling down the
File
menu and selecting
Directory
.
This brings up the Change Directory To dialog box. Double-click the subdirectory
examples
and click
OK
.
Step 2.
To create the new library, pull down the
Library
menu and select
New
. This brings up a dialog
box asking you the name of library you want to create.
Step 3.
Enter the name
lib2
and click
Create
. This creates a new library directory under the current
working directory. In the Model
Sim
window, you will see the following command echoed:
vlib lib2