Technical data

Text conventions
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Introduction Getting Started with ModelSim PE
Text conventions
Text conventions used in this manual include:
HDL and HDL item defined
“HDL” refers to either VHDL or Verilog when a specific language reference is not needed.
Depending on the context, “HDL item” can refer to any of the following:
•
VHDL
block statement, component instantiation, constant, generate statement, generic,
package, signal, or variable
•
Verilog
function, module instantiation, named fork, named begin, net, task, or register variable
Syntax conventions
The syntax elements of Model
Sim
commands are signified as follows:
italic text
provides emphasis and sets off file and path names
bold text indicates commands, command options, and menu choices, as well as package
and library logical names
monospaced type monospace type is used for program and command examples
The right angle (>) is used to connect menu choices when traversing menus as in: File > Save
< > angled brackets surrounding a syntax item indicate a user-defined argument; do
not enter the brackets in commands
[ ] square brackets indicate an optional item; if the brackets surround several
words, all must be entered as a group; the brackets are not entered
... an ellipsis indicates items that may appear more than once; the ellipsis itself
does not appear in commands.
| the vertical bar indicates a choice between items on either side of it. Do not
include the bar in the command
# comments are preceded by the number sign (#)