Technical data

Mixed VHDL/Verilog simulation
Getting Started with ModelSim PE Tutorial: Using ModelSim PE
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Let’s take another look at the design.
Step 10.
Click on the Verilog module,
c: cache
.
The source code for the Verilog module is now shown in the Source window. Scroll down to
line #25. Note the declaration of cache_set; this is a VHDL entity instantiated within the
Verilog file
cache.v.