Technical data

Mixed VHDL/Verilog simulation
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Tutorial: Using ModelSim PE Getting Started with ModelSim PE
Step 7.
From the menu bar select the
Window > Restore All
option. Arrange the windows so the
List, Wave, Source and Structure windows are within view.
Step 8.
This time you will use the VSIM command line to add all of the HDL items in the region to the
List and Wave windows:
list *
wave *
Step 9.
The Structure window is hierarchical. Notice the mixture of VHDL and Verilog in the design.
VHDL levels are indicated by a square “prefix” in the Structure window, while Verilog levels
are indicated by a circle “prefix.” Try expanding (+) and contracting (-) the structure layers.
You’ll find Verilog modules have been instantiated by VHDL architectures and VHDL by
Verilog.