Technical data

Mixed VHDL/Verilog simulation
Getting Started with ModelSim PE Tutorial: Using ModelSim PE
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121
Note:
A project file will already exist if someone has done this exercise before. Again, Model
Sim
will
just give you a message that you can safely ignore.
Step 4.
Now you can compile the Verilog files using the
File > Compile_Verilog
menu sequence.
Model
Sim
displays the Compile Verilog Source dialog box:
Compile
cache.v
,
memory.v
and
proc.v
in any order you choose
.
Note that a group of Verilog
files can be compiled in any order. In a mixed VHDL/Verilog design, however, the Verilog
files must be compiled before the VHDL files.
Step 5.
Depending on the design, the compile order of VHDL files can be very specific. In the case of
this lesson, the file
top.vhd
must be compiled last. Compile the VHDL files from the Transcript
window command line with this command:
vcom util.vhd set.vhd top.vhd
Step 6.
Begin simulation from the
VSIM
button on the tool bar. Invoke
vsim
with the name of the
top-level design (
top
) from the Simulate a Design dialog box: