Technical data

Mixed VHDL/Verilog simulation
120
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Tutorial: Using ModelSim PE Getting Started with ModelSim PE
Mixed VHDL/Verilog simulation
You must be using Model
Sim
PE/PLUS for this lesson.
Thanks to Model
Sim
’s single kernel simulator, the VHDL and Verilog simulation procedures
you learned in the previous lessons apply directly to mixed VHDL/Verilog simulation.
The goals for this lesson are:
• compile multiple VHDL and Verilog files
• simulate a mixed VHDL and Verilog design
• list VHDL signals and Verilog nets and registers
• view the design in the Structure window
• view the HDL source code in the Source window
Step 1.
Restart Model
Sim
. Using the
File > Directory
menu sequence, and the
Change Directory To:
dialog box, move to the
\example\mixedHDL
directory (within the install directory).
In the Transcript window, Model
Sim
echoes the
cd
command.
Step 2.
Before you can compile an HDL source file, you need to create a new
work
library. Type this
command in the Transcript window (or use the
Library > New
menu sequence):
vlib work
Note:
If this tutorial has already been run on your system, a message will report that the
work
subdirectory already exists in the current directory. You can ignore the message and proceed.
Step 3.
Now you need to create a new project file in your current working directory. Select
Project >
New
and type in
modelsim.ini
.