Technical data

Basic Verilog simulation
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Tutorial: Using ModelSim PE Getting Started with ModelSim PE
Notice how this window describes the hierarchical structure of the design. In the illustration the
Structure window shows three hierarchical levels: test_counter, counter and the function called
increment.
You can navigate within the hierarchy by clicking on a line within the window.
Step 11.
Click on
FUNCTION increment
and notice how other VSIM windows are automatically
updated as appropriate.
Specifically, the Source window displays the Verilog code at whichever hierarchical level you
selected in the Structure window. Using the Structure window in this way is analogous to
scoping commands in interpreted Verilogs. For now, make sure the
test_counter
module is
showing in the Source window by clicking on the top line in the Structure window.
Step 12.
Before we run the simulation, let's put some signals in the List and Wave windows. You can
do this either by typing a command, or using the pull down menus. Let's do one of each. First,
type:
wave *
This causes the Wave window to display the signals clk, rst and count. The
*
is a wildcard and
here it means all signals at the current hierarchical level. (Typing
wave -r *
would have
displayed all signals throughout the design hierarchy.) In a moment, when you run the
simulation you will see the Wave window update with signal values.
Step 13.
Secondly, pull down
Signals > Add to List > Signals in Design
.