Technical data

Basic Verilog simulation
Getting Started with ModelSim PE Tutorial: Using ModelSim PE
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Now select any Verilog source file and click
Compile
.
When you click Compile, VLOG (the Verilog compiler) is invoked and should generate output
messages similar to these:
Notice that the order in which you compile the two Verilog modules is not important. This may
again seem strange to Verilog XL users who understand the possible problems of interface
checking between design units, or compiler directive inheritance. Model
Sim
defers such checks
until the design is loaded by VSIM (the HDL simulator), so it doesn't matter if you choose to
compile
counter.v
before or after
tcounter.v
.
Select the next Verilog file and click
Compile
.
During compilation, the Model
Sim
prompt is not displayed. When the compiler finishes the
prompt returns. When all files have been compiled, click
Done
.
Now that the design files have been compiled, you are ready to simulate. Before you move on
however, it is interesting to pull down the
Library > Contents
menu. This shows the a list of
the current contents of the active library (
work
in this case). You should see the two modules
of this design: counter, and test_counter. One option available to you here is to delete one or
more of the design modules from the library - but don't do that now. Instead click
Done
.
Step 8.
Now let’s start the simulation. You can either pull down the
File
menu and select
Simulate
, or
click the menu button labeled
VSIM
.