Technical data

Basic Verilog simulation
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Tutorial: Using ModelSim PE Getting Started with ModelSim PE
The example design we'll be using consists of two Verilog source files, each containing a
unique module. The file
counter.v
contains a module called counter that implements a simple
8-bit binary up-counter. The other file (
tcounter.v
) is a testbench module (test_counter) used to
verify counter. Under simulation you will see that these two files are configured hierarchically
with a single instance (instance name dut) of module counter instantiated by the testbench.
You'll get a chance to look at the structure of this code later.
For now, you need to compile both files into your
work
design library. There are two ways to
compile design units with Model
Sim
’s graphic interface: from the menu bar, or from the tool
bar. We’ll look at both options.
Step 6.
Pull down the
File
menu and select
Compile Verilog
.
This brings up the Compile Verilog Source dialog box. Notice this dialog box lists all files in
the current directory with a
.v
suffix which is a useful convention for naming Verilog source
files. You could select a file here and click Compile but don't do that just yet. Instead click
Done
.
Step 7.
Click the
VLOG
menu button.
The same Compile Verilog Source dialog box appears. Notice in the compile dialog box a
selector box called
Compile More
, select it now. When this is selected, the dialog box remains
active after you click Compile so you can compile more than one source file.