Technical data

Debugging a VHDL design
Getting Started with ModelSim PE Tutorial: Using ModelSim PE
-
101
Step 22.
Under the
Assertions
tab, change the selection for
Break on Assertion
to
Error
and click
OK
,
then
Yes
. This will cause the simulator to stop at the VHDL statement after the assertion is
displayed.
Step 23.
To restart the simulation, pull down the
File
menu and select
Restart
.
For now, leave all the options as they are and select
OK
.