Getting Started with ModelSim PE VHDL, Verilog, and Mixed-HDL Simulation for PCs Running Windows 95 & Windows NT Version 4.
ModelSim /VHDL, ModelSim /PLUS, and ModelSim /VLOG are produced by Model Technology Incorporated. Unauthorized copying, duplication, or other reproduction is prohibited without the written consent of Model Technology. The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology.
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Table of Contents Software License Agreement . . . . Model Technology Software License . Important Notice . . . . . . . . . Limited Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 5 1 - Introduction (p11) Software versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Simulate a Design dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Tree windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Window overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Transcript window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Transcript window status bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Transcript window keyboard actions . . . . . . . . . . . . . .
Variables window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Variables window status bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Variables window mouse actions . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Wave window . . . . . . . . . . . . Wave window menu bar . . . . . . . Wave window status bar . . . . . . . Wave window mouse actions . . . . . Adding HDL items to the Wave window Editing HDL items in the Wave window Formatting the Wave window . .
Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 ModelSim PE Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Getting help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 B - Resources (p135) Books . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Corporations & Consultants . . . . . . . . . . . .
- Table of Contents Getting Started with ModelSim PE
1 - Introduction Chapter contents Software versions . . . . . . . . . . . . . . . . . 11 Standards supported . . . . . . . . . . . . . . . . . 12 Assumptions . . . . . . . . . . . . . . . . . . 13 Sections in this guide . . . . . . . . . . . . . . . . 13 HDL and HDL item defined . . . . . . . . . . . . . . . 14 Where to find our documentation . . . . . . . . . . . . . 15 .
Standards supported Standards supported ModelSim VHDL supports both the IEEE 1076-1987 and 1076-1993 VHDL standards. Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with either IEEE Standard 1076-1987 or 1076-1993. ModelSim Verilog is based on the IEEE Std 1364-1995 (IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language). The Open Verilog International Verilog LRM version 2.0 is also applicable to a large extent.
Assumptions Assumptions We assume that you are familiar with the use of your operating system. If you are not familiar with Microsoft Windows, we recommend that you work through the tutorials provided with MS Windows before using ModelSim. In addition, we assume that you have a working knowledge of VHDL and Verilog. Although ModelSim is an excellent tool to use while learning HDL concepts and practices, this guide is not written to support that goal.
Text conventions Text conventions Text conventions used in this manual include: italic text provides emphasis and sets off file and path names bold text indicates commands, command options, and menu choices, as well as package and library logical names monospaced type monospace type is used for program and command examples The right angle (>) is used to connect menu choices when traversing menus as in: File > Save HDL and HDL item defined “HDL” refers to either VHDL or Verilog when a specific langu
Where to find our documentation Where to find our documentation Model Technology’s documentation is available in the following formats and locations: Document Format How to get it Getting Started (installation & tutorial) paper shipped with the product; additional copies at $50 each (for customers with current maintenance) Getting Started PE PDF online find "getstart.
Comments Comments Comments and questions about this manual and ModelSim software are welcome. Call, write, or fax or email: Model Technology Incorporated 8905 SW Nimbus Avenue, Suite 150 Beaverton OR 97008-7100 USA phone: 503-641-1340 fax: 503-526-5410 email: manuals@model.com home page: http://www.model.
2 - ModelSim PE Installation Chapter contents Current customers information . . . . . . . . . . . . . 18 System requirements for ModelSim PE . . . . . . . . . . . . 18 Installation procedure . . . . . . . . . . Install ModelSim on Your Hard Drive - From CD-ROM Install the Security Key . . . . . . . . . Authorization Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 . 19 . 19 . 19 To Run from the CD-ROM . . . . . . . 20 . . . . . . . . .
Current customers information Current customers information If you are using V-System PC version 4.4 or older, you should install ModelSim 4.7 in different directory. You will also need to regenerate your design libraries with -refresh before running any simulations. By default, the work library is updated; use -work to update a different library.
Installation procedure Installation procedure Install ModelSim on Your Hard Drive - From CD-ROM The CD-ROM will auto-start when you put it in your reader; then follow the directions that appear on your screen. Or if the CD-ROM is already in the reader, double-click on the ModelSim CD icon to start. Install the Security Key ModelSim version 4.7 requires a hardware security key with an authorization code. Install the key on the parallel printer port.
To Run from the CD-ROM Authorization Codes: updates If you receive a new programmable key to replace an old-style, non-programmable key, your new key is delivered ready to run for 30 days from when you first invoke ModelSim. You can get a permanent code for the product you purchased by returning your old key along with your new key’s serial number and your email address. We will send you a permanent code via email.
3 - ModelSim PE Graphic Interface Chapter contents ModelSim application window . . . . . . . . . . . . . . 22 The Simulate a Design dialog box . . . . . . . . . . . . . 28 Tree windows . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ModelSim application window ModelSim application window The ModelSim application window and Transcript window are pictured below as they appear when ModelSim is first started. Note that typical window parts are used in ModelSim. The control-menu icon, title bar, minimize, maximize and close buttons appear across the top. A menu bar appears immediately under those items. Scroll bars are available when necessary at the right side and bottom of the window.
ModelSim application window In addition to the Transcript window, the ModelSim application window also accommodates eight other windows for use during your design compilation, simulation, and debugging. They are the Dataflow, List, Signals, Source, Structure, Process, Variables, and Wave windows. A portion of each window is shown below.
ModelSim application window ModelSim menu bar The menu bar at the top of the application window lets you access all the ModelSim commands and features. The menus are listed below with brief descriptions of the command’s use.
ModelSim application window Project New create a new modelsim.ini project file Change change to another project file shows up to three former modelsim.ini files name of current modelsim.
ModelSim application window Edit Breakpoints modify or delete source code breakpoints Macro Options Echo or Hide the macro commands in the Transcript window Processes view Active processes, or All processes in the current region Window Cascade cascade windows Tile Horizontal tile windows horizontally Tile Vertical tile windows vertically Arrange Icons arrange icons at bottom of application window Restore All restore all icons to windows Colors change colors of window features Fonts chang
ModelSim application window ModelSim tool bar In addition to the functions accessed through the menu bar, you can use the ModelSim tool bar for several frequently-used commands:: Button Menu equivalent VSIM command equivalent VCOM File > Compile VHDL vcom VLOG File > Compile Verilog vlog VSIM File > Simulate vsim RUN Run > Run … run CONT Run > Cont…. continue BREAK none * STEP Run > Step…. step OVER Run > Step Over….
The Simulate a Design dialog box The Simulate a Design dialog box When you first invoke VSIM you will see the Simulate a Design dialog box below. This dialog box has four tabs to select simulation options: • The first, labeled Design, allows you to select a library and top-level design unit to simulate. • The second tab, labeled VHDL, allows setting of several VHDL-specific options.
Tree windows Tree windows In many windows, ModelSim provides a hierarchical or “tree view” of your design. For example, in the Structure window, one level of the hierarchy is created by each VHDL and Verilog HDL item. This type of view is used in the Structure (shown), Signals, Variables, and Wave windows.
Tree windows When you see this view, you can use the mouse to collapse and expand levels by clicking on the plus and minus boxes. Note - within the Structure window only - VHDL items are indicated with a box and Verilog items are indicated with a circle. [+] A plus box or circle before a name indicates that you can expand the item to view the lower level elements it contains. You do this by clicking the box containing the plus sign.
Window overview Window overview Once you invoke VSIM nine windows become available for use during simulation. These windows are: • Transcript window (p32) The command-line window; displays a transcript of all command activity. • Dataflow window (p35) Lets you trace signals and nets through your design by showing related processes. • List window (p37) Shows the simulation values of selected VHDL signals, and Verilog nets and register variables in tabular format.
Transcript window Transcript window The Transcript window is the first window to appear when you use ModelSim. If you tend to use the menus to control ModelSim, you can almost ignore the Transcript window; just think of it as the place where your menu commands are recorded. If on the other hand, you are command-line oriented, then you can use the Transcript window to control most ModelSim functions.
Transcript window • the number of the top line visible in the Transcript window and the total number of lines in the right most field When a circuit is compiled, the status bar shows: • the filename being compiled • the line number of the current line being compiled (updated every 100 lines) • the Transcript window line information The status bar shown above indicates that a circuit is loaded for simulation; it reads from left to right: • the current region (and1 in this case), • the current simulation tim
Transcript window Transcript window command line shortcuts On the Transcript window command line, you can also use these shortcuts: Key Action Move to beginning of the line. Move to the end of the line. Retrieves the previous command. You can press this key repeatedly to back up through the command history. Retrieves the next command.
Dataflow window Dataflow window The Dataflow window provides a graphic view of HDL items flowing in and out of processes during your simulation run, which allows you to trace HDL items through your design.
Dataflow window To put a particular process in the Dataflow window, just click on that process in the Process window. The Dataflow window will also show the current process when single-stepping or when VSIM hits a breakpoint. To put a particular signal or net in the window, just click on the item in the Signal window. Tracing HDL items with the Dataflow window The Dataflow window is linked with the Signals and Process windows.
List window List window Two windows in ModelSim provide views of your simulation run. The List window shows you the results in a table format.
List window List window menu bar The following commands are available from the List window menu bar.
List window List window status bar The List window status bar is illustrated below. Only two fields are used in the List window status bar: • the current simulation time and delta (300 ns and 3 in the this case) • the line number of the list line visible at the top of the List window and the total number of lines in the list (line 4 of 12 in the illustration) List window mouse actions Use the mouse to select HDL items for cutting, pasting, or editing by clicking on the item names at the top of the list.
List window Selecting HDL items to list You can select the items to list with the menu bar: Signals > Add to List as described in "Adding HDL items to other windows" (p51). You can also type list * to include every HDL item in the current region specified by what’s selected in the Structure window. And you can use the list command. Selecting List window triggering options Use the List window’s menu bar command Options > Triggering Options to open the Triggers dialog box.
List window Use the OK button when you’ve finished selecting your trigger options. Formatting a list Use List window’s menu bar command Options > Default Options to bring up this List Defaults dialog box. The List Defaults dialog box allows you to specify the default list attributes of HDL items that you add to the list window. • Radix Allows you to specify the radix (base) in which the HDL item value is expressed.
List window specified HDL item. The label may be either just the item name (Short Name) or the item path (Full Name). • Trigger Allows you to specify whether or not a change in the value of the selected item is to trigger a new line in the listing. You can also change the format of the HDL items after they have been added to the List window. Use the List window’s menu bar command Options > Signal Options to bring up the List Signals dialog box.
List window • Radix Change the radix for the selected signal; overrides the radix default set in the List Defaults dialog box. • Width The specification you enter in this text box determines the number of spaces the item’s column occupies in the listing. • Trigger Specify whether or not a change in the value of the selected item is to trigger a new line in the listing ; overrides the Trigger default set in the List Defaults dialog box.
List window Restoring a List window configuration Use the ModelSim menu bar command File > Execute Macro to restore your List window configuration. Updating the List window You can determine when the List window is updated (either during or after simulation runs) with the List window menu bar command: Display Options > Update During Run | Update After Run.
Process window Process window The Process window displays a list of processes that are scheduled to run during the current simulation cycle and indicates the hierarchical pathname of the instance in which the process is located. If you select View Active Processes with the menu bar commands, the Process window displays all the processes that are scheduled to run during the current simulation cycle.
Process window You can debug your design (or explore someone else’s) by using the Process window.
Signals window Signals window The Signals window shows the names and values of HDL items in the current region (selected in the Structure window). Items are shown in the order they are declared in the HDL source code. The names of any composite types (arrays and record types) are shown in a hierarchical fashion, and you can expand and contract the display to view the structure of these elements.
Signals window Signals window mouse actions In the Signals window, you can use the mouse to: • select an HDL item by clicking on its name • adds/subtracts individual selections • extends the selections • collapse and expand levels by clicking on the plus and minus boxes • move a selected HDL item to the Dataflow window Selecting HDL item types to view Use the Signals > View menu bar sequence and the View Signals dialog box to select the HDL items y
Signals window The names of any VHDL composite types (arrays and record types) are shown in a hierarchical fashion. Hierarchy also applies to Verilog nets and vector memories. (Verilog vector registers do not have hierarchy because they are not internally represented as arrays.) To indicate hierarchy, each name is preceded by a box that contains a plus sign (+), a minus sign (-), or may be empty. You can expand and contract the display to view the items by clicking on the boxes at the left of the Window.
Signals window • Value: Initially displays the current value, which can be changed by entering a new value into the field. A value can be specified in radixes other than decimal by using the form (for VHDL and Verilog, respectively): base#value -or- b|o|d|h’value For example, 16#EE or h’EE specifies the hexadecimal value EE. • Delay: Allows you to specify how many time units from the current time the stimulus is to be applied.
Signals window Freeze is the default for Verilog nets and unresolved VHDL signals and Drive is the default for resolved signals. If you prefer Freeze as the default for resolved and unresolved signals, you can change the default force kind in the modelsim.ini file.
Source window Source window The Source window allows you to view your VHDL or Verilog source code in read-only mode. A marker at the left side of the window pane points to the next line to be executed. If any breakpoints have been set, they are signified by a colored dot next to a line number. To set a breakpoint, double-click at or near the right side of the line number. The breakpoints toggle, so you can double-click again to delete an existing breakpoint.
Source window Source window status bar The Source window status bar is illustrated below. The status bar for the Source window shows (from left to right): • the name of the current source file, • the current simulation time and delta (100 ns and 2 in this case), • the current line number of the source code line displayed at the top of the Source window and the total number of lines in the source code. Selecting the source file The Source window default file is the design you selected to simulate.
Source window Editing breakpoints You can double-click anywhere in a line to set or remove a breakpoint. Besides using the mouse to set and remove breakpoints, there is also the Options > Edit Breakpoints menu command. It brings up Breakpoints dialog box. With the Breakpoints dialog box you can delete or modify any breakpoint in the VHDL or Verilog source code.
Source window This dialog box sets the context of the information shown in the Source window. When ModelSim scrolls to a line of source code, Top Margin sets the minimum number of lines displayed above the active line. Bottom Margin sets the number of lines shown below the active line when you single-step the simulator.
Structure window Structure window The Structure window provides a hierarchical view of the structure of your design. A level of hierarchy is created by each HDL item within the design.
Structure window Within the Structure window, VHDL items are indicated by a box and Verilog items are indicated by a circle.You can expand and contract the display to view the elements by clicking on the boxes or circles at the left of the Window. The first line of the VSIM Structure window indicates the top-level design unit being simulated.
Structure window Structure window status bar The Structure window status bar is illustrated below. Only two fields are used in the Structure window status bar: • the pathname of the selected design unit, • the simulation time and delta. Structure window mouse actions Use the mouse to: • select a design entity by clicking on its name, • collapse and expand levels by clicking on the plus and minus boxes.
Variables window Variables window The Variables window lists the names of HDL items within the current process, followed by the current value(s) associated with each name. The pathname of the current process is displayed at the bottom of the window.
Variables window Variables window status bar The Variables window status bar uses two fields: • the current process, • the simulation time and delta. Variables window mouse actions In the Variables window, you can use the left mouse button to: • select an HDL item by clicking on its name, • collapse and expand levels by clicking on the plus and minus boxes.
Wave window Wave window The Wave window — like the List window — is another look into your simulation results. It has two panels or windowpanes; the left pane lists HDL item names and current values, while the right pane is a waveform display across a simulation time axis.
Wave window The data in the item values windowpane is very similar to the Signals window, except that values change dynamically whenever the cursor in the waveform windowpane is moved. At the bottom of the waveform windowpane you can see a timeline, tick marks, and a readout of the cursor(s) position(s). To move a cursor, use the mouse. The time value at the cursor location is displayed at the bottom of the cursor.
Wave window Zoom In 2X show more detail and less simulation time Out 2x show more simulation time and less detail Last return to window view before last zoom Range specify range of simulation times to be shown Cursor Add add a cursor to the display Remove remove the selected cursor Options Waveform Options specify maximum length of HDL item name and snap distance Signal Options specify HDL item formatting Wave window status bar The Wave window status bar shows: • the current simulation tim
Wave window In the right windowpane: If you want to: Use the: And do this: select an item left button click on the item’s waveform - the nearest cursor (if any) is repositioned (delete cursors with Cursor > Remove from the Wave window menu) move a cursor left button click on waveform in desired location - the nearest cursor is repositioned (add cursors with Cursor > Add from the Wave window menu) zoom the display right button click and drag (rubberband) to zoom the display - the time expands to
Wave window Adding HDL items to the Wave window To add HDL items to the window, enter wave Separate the item names with a space. You can add all the items in the current region with this command: wave * Or add all the items in the design with: wave -r /* You can also add items to the Wave window with the Signals menu. See "Adding HDL items to other windows" (p51).
Wave window • Max Signal Name Sets the HDL item name width. This is especially useful for items that have a long pathname. Choose a maximum name width setting, say 10 characters, and then item pathnames longer than 10 characters are truncated. All truncations take place at the slash boundary so you will never see a partial item name. The default value for this field is 0, which means to display the full path. The default value can be changed with a .ini file setting.
Wave window • Signal: Shows the current HDL item name. • Color This command button expands the dialog box to the size shown in the illustration. Color formatting can apply to any HDL item. When you choose one of the colors shown, the Color Value shows you the color’s red, green, and blue values. • Height: This specification (in pixels) controls the spacing between HDL items in the Wave window. • Format Depending on the HDL item’s type, one or more formats will be available for formatting the display.
Wave window Analog formatting • Analog Integer and floating point HDL items can be formatted as analog in the Wave window. ModelSim then plots the item value on the screen as shown above for a_analog, b_analog, and sum_analog. Compare the first b_analog item (formatted as analog) with the same item at the bottom of the display (formatted as literal). • Pixels = These two text boxes can only be used with HDL items formatted as analog. They let you customize the Wave window display to make it easier to use.
Wave window • octal • decimal • hexadecimal. See vector in the illustration for an example of symbolic. Logic Formatting Choose Logic to format a HDL item display in logic representation (1, 0, X, etc.). Zooming the Wave window You can change the amount of time shown in the waveform display windowpane of the Wave window with the mouse or with menu commands. Zoom in on an area of the display by holding down the and dragging through the area of the display you want expanded.
Wave window Another method of zooming is with the function keys: Key Action full zoom zoom in zoom out last zoom For additional ModelSim shortcuts see: "Keyboard shortcuts" (p76) Using the Wave window cursors You can add or remove cursors with Cursor > Add | Remove menu command. Up to five cursors can be present at the same time. Cursors are displayed with a time box showing the precise simulation time at the bottom.
Wave window When you add a cursor, it is drawn in the middle of the display. Once you have more than one cursor, ModelSim adds a delta measurement showing the time difference between the two cursor positions. The selected cursor is drawn as a solid line; all other cursors are drawn with dotted lines. Tip: If you click in the waveform display, the cursor closest to the mouse position is selected and then moved to the mouse position.
Customizing ModelSim windows Use the Waveform Postscript dialog box to change paper size and orientation, or scale the output to meet your needs. Note that the Margin, Scale, or Number of Pages specifications are interactive. If you change one of these, tab to or click in another box to see the updated specs. The PostScript file includes a file named vsim.ps that is included with ModelSim.
Customizing ModelSim windows Changing window colors The Window > Colors menu bar command returns the Color dialog box. In the color dialog box, you can specify a color for each type of object in each of the ModelSim windows. For example, in the illustration, the Wave window is selected. And in that window, you can set the color of objects like the background, the cursors, text, etc.
Customizing ModelSim windows In the Font dialog box, first you select the ModelSim windows in which you want to change fonts. The Transcript, Source, and List windows can be selected separately. The other six windows (Signals, Variables, Process, Structure, Dataflow and Wave) are grouped. Once you’ve chosen the windows, you can specify fonts with the typical list boxes. Note that monospaced fonts are best for the Source and List windows.
Customizing ModelSim windows Depending on the task you were performing with ModelSim, you might have different window sizes, positions, fonts, and colors with each modelsim.ini project file you define. If you want ModelSim to change its window settings to match a new project file, use the check boxes in Reload with New Project File.
Keyboard shortcuts Keyboard shortcuts The following keyboard shortcuts are available in ModelSim PE: Key Action scroll up one screen scroll down one screen scroll left one screen scroll right one screen move to beginning of window move to end of window scroll up one line scroll down one line scroll left one column scroll righ
4 - Tutorial: Using ModelSim PE Chapter contents After you complete the "Tutorial setup" (p78), choose the lessons appropriate for your simulator version: PLUS, and VHDL lessons Basic VHDL simulation . . . . . . . . . . . . . . . . 79 Debugging a VHDL design . . . . . . . . . . . . . . . 93 . . . . . . . . . . . . . 105 Mixed VHDL/Verilog simulation . . . . . . . . . . . . 120 Learning more about ModelSim’s windows. . . . . . . . . .
Tutorial setup Tutorial setup Before we turn you loose with ModelSim, let’s set up your application windows and save their settings so that if you are interrupted and restart, you will find the windows like you left them. In this setup you will learn how to start the application, and save your window settings. Step 1. Start by invoking ModelSim: Double-click the ModelSim icon. The ModelSim application window will come up with the Transcript window showing.
Basic VHDL simulation Basic VHDL simulation The goals for the first lesson are: • create a library • create a new project file • compile a VHDL file • start the simulator • use the RUN command • list some signals • use the waveform display • force the value of a signal • single-step through a simulation run • set a breakpoint • save the listing from the List window to a file • quit the simulator Step 1. For this exercise you need to change directories to locate the tutorial files.
Basic VHDL simulation If you click Cancel, the dialog box is closed and you remain in the same working directory as before. You must click the OK button to actually change to a different directory. Using the File > Directory menu command is the same as entering the cd (change directory) command at the ModelSim prompt in the Transcript window. In fact, the following command is echoed in the Transcript window: cd C:\modelsim\examples Step 3.
Basic VHDL simulation This creates a VHDL library named work under the current directory. Even though this command creates a DOS directory called work, it is important to realize that it is more than just a directory. You must use only the Library > New option or a vlib ModelSim command to create a new ModelSim library.
Basic VHDL simulation Step 6. Next, compile the VHDL source file named counter.vhd. To do this, pull down the File menu and select Compile VHDL. This brings up the Compile VHDL Source dialog box. For now, click Done. Step 7. Press the VCOM button on the tool bar. The same dialog box appears. Now select the VHDL source file for the counter, named counter.vhd, and then click Compile. When you click Compile, the VHDL compiler is invoked and generates the messages shown below unless it encounters errors.
Basic VHDL simulation Step 8. After the VHDL source file is compiled, close the dialog box by selecting Done. Now start the simulator by pulling down the File menu and selecting Simulate. This brings up the Simulate a Design dialog box, where you select the library and the top-level design unit to simulate. You can also select the simulation time resolution. But select Cancel for now. See "The Simulate a Design dialog box" (p28) for more detail about this dialog box. Step 9.
Basic VHDL simulation arrangement if the tutorial has already been used. For now, select Window > Tile Vertically. The order of the windows might be different on your screen, but you should be able to see all nine as in the illustration. Note that the Transcript window has echoed “view *” for your window command. Step 11. At this point, let’s put signals in both the List and the Wave windows.
Basic VHDL simulation Notice that no matter which ModelSim window is active, anything you type is automatically entered on the Transcript window command line. The commands you typed made signals appear in the List and Wave windows. If you desired to, you could list or view only specified signals by entering the signal names after the command instead of the asterisk. (When you do that, separate the names with spaces.) Step 12. An alternative would be to use the menu bar.
Basic VHDL simulation Step 14. Use the Window > Settings menu sequence to be sure all your changes will be saved. Make sure these boxes are checked: Sizes, Colors, Fonts and Save sizes on exit. Step 15. Now let’s apply some stimulus to the clock input of our circuit.
Basic VHDL simulation This force command means: • Force clk to the value “1” at 50 ns (nanoseconds) after the current time, • then to “0” 100 ns from now, and • repeat this cycle every 100 ns. Step 16. Select RUN on the tool bar. This causes the simulation run for the default simulation length, which is 100 ns. (The default simulation run length can be modified with Options > Simulation Options from the menu bar.
Basic VHDL simulation run @ Use the run command with @ to run to time 5000: run @5000 Step 20. To see the effect of the break feature, you are now going to start a long simulation run and then click the BREAK button during the run to stop the simulator. On the menu bar, select Run > Run Forever. (The run -a command produces the same effect.) Step 21. To stop the simulator while it is running, click the BREAK button.
Basic VHDL simulation Step 23. Next, set a breakpoint on line 35, which has a call to the VHDL function named increment. To do this, move the pointer to the Source window and find line 35. Use the vertical scroll bar if necessary. Double-click on line 35 to set the breakpoint. You will see a dot next to the line number when the breakpoint is set. A breakpoint can be toggled on and off by double-clicking on the line. Step 24. Select CONT (continue) on the tool bar to resume the run that you interrupted.
Basic VHDL simulation Step 25. Examine the current value of the signal count by entering the command: examine count You can also see this information in the Signals window. Step 26. You can find out what kind of variable or signal count is by using the ModelSim command describe. To see this, enter: describe count The system should report (in the Transcript window) that count is an 8-bit array of an enumerated type: Step 27. Click OVER (for Step Over) in the tool bar to step over this instruction.
Basic VHDL simulation Step 30. On your own, try setting and deleting breakpoints at different points in the counter.vhd source file, and using the STEP and OVER buttons until you feel comfortable with these commands. Step 31. When you are ready, you can record the simulation values by writing the contents of the ModelSim List window to a file (CAUTION, this is optional, this could be a huge file). To do this, enter the following command in the Transcript window: write list counter.
Basic VHDL simulation At this point you can confirm the action with the Yes button.
Debugging a VHDL design Debugging a VHDL design The goals for this lesson are: • use a VHDL testbench (a testbench is a VHDL architecture that instantiates the VHDL design units to be tested, provides simulation stimuli, and checks the results) • map a logical library name to an actual library • change the default run length • recognize assertion messages in the command window • change the assertion break level • restart the simulation run using the restart command • change the value of a variable • use a
Debugging a VHDL design Note: If this tutorial has already been run on your system, a message will report that the lib2 subdirectory already exists in the current directory. You can ignore the message and proceed. Step 4. The next step is to set your work library to be the lib2 library you just created. In the last tutorial, you created a work library called work, but now you will map the work library to lib2.
Debugging a VHDL design In this case, type in work for the library name and lib2 for the directory name. This tells ModelSim that whenever it sees a reference to the work library, use the lib2 library instead. Click on OK to accept the new library mapping. Step 7. None of the changes you've made to the library mapping take effect until you click on OK in the Library Mapping dialog box. This way you can add, edit, and delete mappings as much as you like and then discard the changes by clicking Cancel.
Debugging a VHDL design And four, you could compile multiple files using a single vcom command, as in the following example: vcom gates.vhd adder.vhd testadd.vhd Let’s use the tool bar and the Compile VHDL Source dialogue box. Press the VCOM button on the tool bar. Step 9. Once you have the Compile VHDL Source dialog box on the screen, note the Compile More check box. When Compile More is checked, the dialog box stays open until you click on Done.
Debugging a VHDL design Step 10. You can confirm that these design units have been compiled into the library by pulling down the Library menu and selecting Contents. This brings up a dialog box that displays the names of all the design units in the library. Step 11. Scroll through the list of configurations and entities to see what has been compiled into the work library. Choose an entity and click on it, and all of its architectures will be shown in the lower list box.
Debugging a VHDL design Step 13. Select the Design tab and perform the following steps: • make sure that the simulator resolution is ns • look in the design unit scrollbox and select the configuration named test_adder_structural (because this design unit is a configuration, no architectures are displayed in the architecture scrollbox at the bottom of the dialog) • click OK to accept the settings Now open the other eight ModelSim windows with the View > All menu sequence.
Debugging a VHDL design The plus sign means other levels exist below it. The minus sign is used on fully-expanded items. An empty box has no lower levels. Step 15. When you finish exploring, return the Structure window to its original size by clicking on the restore button (the one in the upper right - with small overlapping windows). Step 16. Now click on a name (as opposed to a box) in the Structure window.
Debugging a VHDL design On the VSIM tab, change the Default Run Length to 1000. Do not change the other settings for now. Click OK, then Yes, to accept the new settings. Step 20. Next, you will run the simulator. Click RUN on the ModelSim tool bar. A message in the Transcript window will notify you that there was an assertion error. Let's find out what's wrong. Perform the following steps to track down what caused the assertion message. Step 21. Select Options > Simulation Options.
Debugging a VHDL design Step 22. Under the Assertions tab, change the selection for Break on Assertion to Error and click OK, then Yes. This will cause the simulator to stop at the VHDL statement after the assertion is displayed. Step 23. To restart the simulation, pull down the File menu and select Restart. For now, leave all the options as they are and select OK.
Debugging a VHDL design Step 24. Next, click RUN on the tool bar. Notice that the arrow in the Source window is pointing to the statement after the assertion. Step 25. The assertion occurred because the signal sum does not equal vector.sum, which is derived from the sum field in test_patterns. The sum of the inputs a, b, and cin should be equal to the output sum. The error is in the test vectors. Step 26.
Debugging a VHDL design Step 28. Select Restart from the File menu. Restart resets the values to those that were set when you first entered the simulator. Click OK. Step 29. Now we can change the value of the sum record; type: change test_patterns(6).sum 00000111 Note that this is a temporary edit, you must use your text editor to permanently change the source code. Step 30. Select RUN on the tool bar. At this point, the simulation will run without any errors. Step 31.
Debugging a VHDL design Note that since you used the list -decimal command, the a, b, and sum signals appear twice in the List window, once in binary and then again in decimal format. Step 32. This brings you to the end of this lesson. Feel free to experiment further with the menu system if you wish. (You may also want keep this simulation running for the following keyboard and mouse practice session.
Basic Verilog simulation Basic Verilog simulation The goals for this lesson are: • compile a Verilog design • examine the hierarchy of the design • list signals in the design • change list attributes • set a breakpoint Step 1. First, you need to change directory to the folder where the tutorial files are located. To do this, pull down the File menu and select Directory.
Basic Verilog simulation Step 2. Move inside the examples folder by double-clicking the examples entry in the directories list box. Click OK If you click Cancel, the dialog box is closed and you remain in the working directory you were in before. You must click OK to actually change to a new directory. Using the File > Directory menu command is the same as entering the change directory (cd) command at the ModelSim prompt in the Transcript window.
Basic Verilog simulation Note: If this tutorial has already been run on your system, or you’ve just completed Lesson 1, a message will report that the work subdirectory already exists in the current directory. You may safely ignore this message and proceed. Step 4. Next you need to create a new project file in your current working directory. This project file will be used by ModelSim to remember your environment settings (such as window sizes and positions, etc.
Basic Verilog simulation The example design we'll be using consists of two Verilog source files, each containing a unique module. The file counter.v contains a module called counter that implements a simple 8-bit binary up-counter. The other file (tcounter.v) is a testbench module (test_counter) used to verify counter. Under simulation you will see that these two files are configured hierarchically with a single instance (instance name dut) of module counter instantiated by the testbench.
Basic Verilog simulation Now select any Verilog source file and click Compile. When you click Compile, VLOG (the Verilog compiler) is invoked and should generate output messages similar to these: Notice that the order in which you compile the two Verilog modules is not important. This may again seem strange to Verilog XL users who understand the possible problems of interface checking between design units, or compiler directive inheritance.
Basic Verilog simulation Either action brings up the Simulate a Design dialog box. This dialog box has four tabs to select simulation options: Design, VHDL, Verilog, and SDF. At this point, you can accept the defaults in each case. Click the Design tab, make sure work is the targeted library and select the top-most module in the design test_counter.
Basic Verilog simulation The order of the windows may be different on your machine but you should see all nine. See "ModelSim PE Graphic Interface" (p21) for a detailed description of each window. Although you have invoked the simulator, and runtime checking of the code has occurred, the simulation is halted at time zero waiting for your command. Step 10. Click inside the Structure window.
Basic Verilog simulation Notice how this window describes the hierarchical structure of the design. In the illustration the Structure window shows three hierarchical levels: test_counter, counter and the function called increment. You can navigate within the hierarchy by clicking on a line within the window. Step 11. Click on FUNCTION increment and notice how other VSIM windows are automatically updated as appropriate.
Basic Verilog simulation This causes the List window to display the signals clk, rst and count as well as the current simulation time. (The same effect could be achieved by typing list -r * .) If you desired, you could invoke these commands to display individual signals by specifying the signal names instead of the * wildcard or by selecting Signals > Add to List > Selected Signals from the pulldown menus. Notice that whenever you type a command in ModelSim it appears in the Transcript window.
Basic Verilog simulation Instead of clicking the RUN button you could also type the run command. To try it now, type: run 500 Now the simulation has run for a total of 600ns (the default 100ns plus the 500 you just asked for). See the status bar at the bottom of the ModelSim window. It should show something like this illustration. If your status bar is different it is because the status bar changes depending upon the active ModelSim window.
Basic Verilog simulation Your windows won't look exactly like the illustration because your simulation very likely stopped at a different point. Also, we are showing only two windows in this illustration. Next we'll take a brief look at some interactive debug features of the ModelSim environment. To start with, let's see what we can do about the way the List window presents its data. Step 20. In the List window select the signal named count.
Basic Verilog simulation Step 21. ModelSim includes an extensive breakpoint feature. Make sure the second line (dut:counter) in the Structure window is selected, then set a breakpoint at line 30 in the Source window. To set the breakpoint, simply move the cursor to the Source window and scroll the window to display line 30, and double-click on line 30. You will see a dot appear next to the line number. This indicates that a breakpoint has been set for that line.
Basic Verilog simulation Step 22. Select CONT from the toolbar to resume execution of the simulation. When the simulation hits the breakpoint, it stops running, highlights the Source window and issues a message in the Transcript window. Step 23. Typically when a breakpoint is reached you will be interested in one or more signal values. There are a few ways to determine this.
Basic Verilog simulation Step 24. Pull down Options > Edit Breakpoints from the main menu bar. This brings up the Breakpoints dialog box. This dialog box should look like the illustration. Notice that the breakpoint we entered is displayed. Highlight the breakpoint for line 30 by clicking on it. Now click the Modify button in this dialog box. The Command field becomes active and you can type into it: examine count This command will be executed every time the breakpoint on line 30 is reached.
Basic Verilog simulation Step 26. Click OVER on the toolbar. This causes the simulator to step over the function call on line 30. The STEP button on the toolbar would have single-stepped the simulator, including each line of the increment function. Step 27. Experiment by yourself for a while; setting and clearing breakpoints as well as STEP’ing and OVER’ing function calls until you feel comfortable with the operation of these commands. Step 28.
Mixed VHDL/Verilog simulation Mixed VHDL/Verilog simulation You must be using ModelSim PE/PLUS for this lesson. Thanks to ModelSim’s single kernel simulator, the VHDL and Verilog simulation procedures you learned in the previous lessons apply directly to mixed VHDL/Verilog simulation.
Mixed VHDL/Verilog simulation Note: A project file will already exist if someone has done this exercise before. Again, ModelSim will just give you a message that you can safely ignore. Step 4. Now you can compile the Verilog files using the File > Compile_Verilog menu sequence. ModelSim displays the Compile Verilog Source dialog box: Compile cache.v, memory.v and proc.v in any order you choose. Note that a group of Verilog files can be compiled in any order.
Mixed VHDL/Verilog simulation Step 7. From the menu bar select the Window > Restore All option. Arrange the windows so the List, Wave, Source and Structure windows are within view. Step 8. This time you will use the VSIM command line to add all of the HDL items in the region to the List and Wave windows: list * wave * Step 9. The Structure window is hierarchical. Notice the mixture of VHDL and Verilog in the design.
Mixed VHDL/Verilog simulation Let’s take another look at the design. Step 10. Click on the Verilog module, c: cache. The source code for the Verilog module is now shown in the Source window. Scroll down to line #25. Note the declaration of cache_set; this is a VHDL entity instantiated within the Verilog file cache.v.
Mixed VHDL/Verilog simulation Step 11. Click on the line "s0:cache_set(only)" in the Structure window. The Source window now shows the VHDL code for the cache_set entity.
Mixed VHDL/Verilog simulation Step 12. Try experimenting with some of the toolbar commands you’ve used in previous lessons: RUN, BREAK, CONT, STEP and OVER. Note that in this design, clk is already driven, so you won’t need to use the force command. Step 13. Now let’s get a Wave window view of the simulation; activate the Wave window. When the Wave window is first drawn, there is one cursor in it at time zero. Clicking anywhere in the waveform display brings that cursor to the mouse location.
Mixed VHDL/Verilog simulation positions. The selected cursor is drawn as a solid line; all other cursors are drawn with dotted lines. Step 15. Click in the waveform display. Notice how the cursor closest to the mouse position is selected and then moved to the mouse position. Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display. Clicking anywhere in a track selects that cursor and brings it to the mouse position.
Learning more about ModelSim’s windows Learning more about ModelSim’s windows The more you use ModelSim for your own purposes, the better you will understand how it works; hence this unstructured practice session. To begin your practice session simply start a simulation (you can use one of the previous lesson simulations if you wish). Once you’re simulating, select a practice subject from the references below.
Learning more about ModelSim’s windows Source window practice • Selecting the source file (p53) • Editing breakpoints (p54) • Examining values at breakpoints (p54) • Customizing the Source window (p54) Structure window practice • Structure window mouse actions (p58) Variables window practice • Variables window mouse actions (p60) Wave window practice • Wave window menu bar (p62) • Wave window mouse actions (p63) • Adding HDL items to the Wave window (p65) • Editing HDL items in the Wave window (p65) • Form
Continuing with ModelSim PE Continuing with ModelSim PE More information on ModelSim commands, functions and techniques for use can be found in the following locations: • The ModelSim PE/PLUS Reference Manual, and • the Tips and Techniques appendix of the ModelSim PE/PLUS Reference Manual.
- Tutorial: Using ModelSim PE Getting Started with ModelSim PE
A - Help, Updates, and Licensing Help Technical Support for Mentor Graphics Customers For customers who purchased from Mentor Graphics in North America, the support line number is 800-547-4303. The web site is http://supportnetweb.mentorg.com. For customers who purchased from Mentor Graphics outside of North America, please contact your local support organization.
Updates • Lucent Technologies Bell Labs Design Automation email: info@blda.lucent.com telephone: 800-875-6590 web site: http://www.bell-labs.com/org/blda • Synplicity email: support@synplicity.com telephone: 408-617-6000 web site: http://www.synplicity.com Updates Getting the latest version information If you want the latest version information via email from Model Technology, make sure your email address is current in our customer database. If you think it is not, send email to license@model.com.
ModelSim PE Licensing expiration date. The key code permits the use of any ModelSim PE software with a build date on or before the maintenance expiration date. PE Maintenance Renewals When maintenance is renewed, Model Technology will send a new key code that incorporates the new maintenance expiration date. If maintenance is not renewed, the key will still permit the use of any version of the software built before the maintenance expired. Note: PE users should protect the key.
ModelSim PE Licensing Getting help The best thing is to email us a test case. Our email address is support@model.com. The next best thing is to copy/print the following form, fill it out, and fax it to us at 503-526-5473. ===================================================================== Model Technology Fax Support Form Your name: Your company: Your phone number: Your FAX number: Your email address: ModelSim Version: (Use the Help About dialog box with Windows; type vcom for workstations.
B - Resources Appendix contents Books . . . . . . . . . . . . . . . . . . . 135 Organizations . . . . . . . . . . . . . . . . . 137 Corporations & Consultants . . . . . . . . . . . . . . 138 Online resources . . . . . . . . . . . . . . 141 . . . Books Applications of VHDL to Circuit Design Randolph E. Harr and Alec G. Stanculescu, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061, USA. 1991.
Books Practical Programming in Tcl and Tk Brent Welch, Prentice Hall, Englewood Cliffs, New Jersey 07632, USA. 1995. Tcl and the Tk Toolkit John K. Ousterhout, published by Addison-Wesley Publishing Company, Inc. (ISBN 0-20163337-X). Verilog Language Reference Manual 2.0 Open Verilog International, 15466 Los Gatos Blvd., Suite 109-071, Los Gatos CA 95032 Phone: (408) 353-8899 , fax: (408) 353-8869 , email: ovi@netcom.com, Contact: Lynn Horobin VHDL, 2nd Edition Douglas L. Perry, McGraw-Hill, Inc.
Organizations Organizations IEEE The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, New York 10017-2394, USA. Fax:212-705-7453. Open Verilog International 15466 Los Gatos Blvd., Suite 109-071, Los Gatos CA 95032 Phone: (408) 353-8899 , fax: (408) 353-8869 , email: ovi@netcom.com, web: http:// www.ovi.org Contact: Lynn Horobin The SDF mapping rules described in the Model Development Specification are based on version 2.1 of OVI's Standard Delay Format Specification.
Corporations & Consultants Corporations & Consultants Automata Publishing Company 1072 South Saratoga-Sunnyvale Road, BLDG A107, San Jose CA 95129 USA. Phone: 800-8VIPER1 or 408-255-0705, fax 408-253-7916, email: info@apco.com. PCI VHDL simulation models. Contact: Mona Singh. CAST Computer Aided Software Technologies, Inc. 24 White Birch Drive, Pomona NY 10970 USA. Phone: 914-354-4945, Fax: 914-354-0325; email: info@cast-inc.com, web: http://www.cast-inc.
Corporations & Consultants Hardi Electronics AB Box 966, S220 09 Lund, Sweden. Phone: (46) 11-77-90; fax: (46) 13-15-99. Provides VHDL training, consulting services, and product distribution. Contact: Lars-Eric Lundgren. LEDA SA 35 Avenue du Granier, 38240 Meylan, France. Phone: (33) 76-41-92-43. fax: (33) 76-41-9244. Provides VHDL training, consulting services, and product distribution. Contact: Francis Sourbier. Logic Modeling 19500 NW Gibbs Drive, Beaverton OR 97006 USA.
Corporations & Consultants Seva Technologies Inc. 200 Brown Road, Suite 103, Fremont, CA 94539 USA. Phone: 510-249-9085, fax: 510-249-9082, email: lfs@seva.com. VHDL training, consulting services. Contact: Larry Saunders. System Simulation Solutions 1100 NW Compton Drive, Beaverton, OR 97006, USA. Phone: 503-690-1200. VHDL modeling services. Contact: James B. Morris. Topdown Design Solutions 71 Spit Brook Road, Suite 301, Nashua, NH 03060, USA. Phone: 603-888-8811, fax: 603-888-7694, email: sales@topdown.
Online resources Willamettte HDL, Inc. 14314 SW Allen Blvd. Suite 625, Beaverton, OR 97005 USA. Phone: 503-590-8499, fax 503-645-9728, email: info@whdl.com, internet: http://www.whdl.com. Top-down design methodologies for system, board, and ASIC design. Online resources email: omf_info@cfi.org newsnet news groups: sci.electronics.cad comp.arch.fpga comp.lang.tcl comp.lang.verilog comp.lang.vhdl comp.lsi comp.lsi.testing home pages: http://www.model.com http://www.vhdl.org/vhdl_intl http://www.e2w3.
- Resources Getting Started with ModelSim PE
Index A Adding signals or nets to windows 51 Application window 22 Authorization codes 19 entering your permanent code 20 Model Technology direct sales 19 Model Technology OEM sale 19 protect your investment 17 time-based code 17 updates 20 B Breakpoints editing 54 examining values at 54 setting 52, 89 viewing 52 adding a process to 36, 46 adding a signal to 36, 48 mouse actions 36 tracing signals and nets 36 Debugging a VHDL design 127 Default simulation run length 99 describe ModelSim command 90 Design
defined 14 Home page Model Technology’s home-page URL 16 P Keyboard shortcuts 76 PostScript file from waveform display 71 Process window 45 mouse actions 46 status bar 46 Processes displaying values and pathnames of 59 Project file creating new file 81 L Q Library, creating 80 List window 37 change display radix 115 editing a list 43 formatting a list 41 mouse actions 39 restoring formats 44 save listing 91 saving the format of 43 status bar 38, 39 triggering options 40 Quitting the simulator 91 I I
Simulation changing default run length 99 error correction 102 mixed VHDL/Verilog 120 restart 101 Verilog 109 VHDL 79 Source file selecting 53 Source window 52 customizing 54 status bar 53 Status bar 87 Stimulus, apply to a design 86 Structure window 53, 56 mouse actions 58 status bar 58 System requirements 18 T Tracing HDL items with the Dataflow window 36 Transcript window 32 keyboard actions 33 menu bar 24 status bar 32 Tutorial setup 78 U Verilog simulation 105 VHDL simulation 79 View Active Processe
- Index Getting Started with ModelSim PE
