Data Sheet

Everestek Inc.
www.everestek.biz Page 12
7. I2C Timing
Parameter
Symbol
Min
Max
unit
SCL clock frequency
F
SCL
200
KHz
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
t
HD;STA
4
us
LOW period of the SCL clock
t
LOW
2.2
us
HIGH period of the SCL clock
t
HIGH
2.2
us
Set-up time for a repeated START
condition
t
SU;STA
4
us
Data hold time:
t
HD;DAT
0
us
Data set-up time
t
SU;DAT
100
ns
Rise time of both SDA and SCL signals
t
r
500
ns
Fall time of both SDA and SCL signals
t
f
300
ns
Set-up time for STOP condition
t
SU;STO
4
us
Bus free time between a STOP and START
condition
T
BUF
10
us
Please also refer to Everestek_I2C_200KHz_and_USB_HID_desciption.pdf for deail.