Hardware manual

4 Allen-Bradley PLCs
2-127
Chap.2
4.5.1 MicroLogix, SLC 500 (Full Duplex)
・ Bit Device
Device Symbol
Device Name
HG PLC
Address Range
Read
/Write
Address
Gradual
Output O O
0 - 1625515 R 10(*1)
Input I I
0 - 1625515 R 10(*1)
Binary B B
300000 - 325515,
900000 - 25525515
R/W 10(*2)
Timer Enable Bit TEN T(EN)
4000 - 4255, 9000 - 255255 R 10(*3)
Timer Timing Bit TTT T(TT)
4000 - 4255, 9000 - 255255 R 10(*3)
Timer Done Bit TDN T(DN)
4000 - 4255, 9000 - 255255 R 10(*3)
Counter Up Enable
Bit
CCU C(CU)
5000 - 5255, 9000 - 255255 R 10(*3)
Counter Down Enable
Bit
CCD C(CD)
5000 - 5255, 9000 - 255255 R 10(*3)
Counter Done Bit CDN C(DN)
5000 - 5255, 9000 - 255255 R 10(*3)
Counter Overflow Bit COV C(OV)
5000 - 5255, 9000 - 255255 R 10(*3)
Counter Underflow Bit CUN C(UN)
5000 - 5255, 9000 - 255255 R 10(*3)
Counter Update
Accumulator
CUA C(UA)
5000 - 5255, 9000 - 255255 R 10(*3)
Control Enable Bit REN R(EN)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Queue Bit REU R(EU)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Asynchronous
Bit Done Bit
RDN R(DN)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Synchronous
Done Bit
REM R(EM)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Error Bit RER E(ER)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Unload Bit RUL R(UL)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Running Bit RIN R(IN)
6000 - 6255, 9000 - 255255 R 10(*3)
Control Found Bit RFD R(FD)
6000 - 6255, 9000 - 255255 R 10(*3)