User`s manual

350
15.3 I/O Signals for Handshake with Programmable
Controller CPU and Buffer Memory
This section describes the I/O signals for handshake and the buffer memories used when mode switching is
performed.
(1) I/O signals for handshake with programmable controller CPU
Remark
The following signals can also be used as I/O signals, in addition to the above.
Refer to User's Manual (Basic) for the programmable controller CPU I/O signals.
• Q series C24 ready signal (X1E): Turned ON when the Q series C24 can be accessed from the programmable
controller CPU
• Watchdog timer error signal (X1F): Turned ON when the Q series C24 does not operate normally
• CH1 ERR. signal (XE): Turned ON when the CH1 ERR. has occurred
• CH2 ERR. signal (XF): Turned ON when the CH2 ERR. has occurred
(2) Buffer memory
Item
I/O signal
Signal name
Device turned
ON/OFF
Timing
CH1 CH2 CPU C24
Mode
switching
X6 XD
Mode switching in
progress

Y2 Y9
Mode switching
request

Address (Decimal
(hexadecimal))
Name Setting value/Stored value
CH1 CH2
144 (90H) 304 (130H)
For specifying mode
switching
Switching mode No. designation
( Page 351, Section 15.3 (2)
(a))
0001H: MC protocol (Format 1)

0007H: Bidirectional protocol
0009H: Pre-defined protocol
00FFH: GX Developer connection
145 (91H) 305 (131H)
Transmission specification setting
after switching
( Page 351, Section 15.3 (2)
(b))
0000H: Matched to the settings at the GX Developer
8000H to 8FFFH: Matched to the settings of this area
515 (203H)
For confirming mode
switching and switch
setting
Switch setting error, mode switching
error condition
0: Normal
Other than 0: Switch setting error, mode switching error
( User's manual (Basic))
(Switching)
Complete