User`s manual

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MELSEC-Q
3 SPECIFICATIONS
3.2.2 Analog output test during PLC CPU STOP
When the PLC CPU stops, an analog output test as shown in Table 3.4 can be
performed.
The analog output test performs the following operations in GX Developer device
testing or GX Configurator-DA selection testing described in Section 5.6.1.
(1) Set D/A Conversion enable/disable setting (buffer memory address 0: Un\G0) of
the channel to be tested to enable.
(2) Switch the operating condition setting request (Y9) from OFF to ON to OFF.
(Refer to Section 3.3.2.)
(3) Sets the output enable/disable flag (Y1, Y2) for the channel to be tested to enable
(OFF
ON).
(4) Writes a digital value equivalent to the analog value to be output in CH
digital
value (see Table 3.6 in Section 3.4.1) in the buffer memory.
Table 3.4 List of analog output test
D/A conversion enable/
disable Setting
(buffer memory address
0: Un\G0)
Enable Disable
Setting
combination
CH
output enable/
disable flags (Y1, Y2)
Enable Disable Enable disable
Analog output test Allowed Not allowed
Not allowed
1
1 Perform the analog output test after changing the D/A conversion enable/disable setting
(buffer memory address 0: Un\G0) to enable.
POINT
When the digital value storage device has been set in the automatic refresh setting
of GX Configurator-DA, the buffer memory is overwritten since automatic refresh is
performed if the PLC CPU is during STOP.
In this case, write a digital value to the digital value storage device instead of the
buffer memory.