Specifications

20 GX Configurator-PN

5. The PROFINET Controller reads the output data from buffer memory

6. The PROFINET Controller signals that the output buffer is free by toggling its bit to equal that of

the PLC CPU (1 -> 0 for cycle 2)

7. The cycle 2 is completed

2.1.3 Acyclic Communication Area

The acyclic communication is an exchange of request and response messages between the

PROFINET Controller and each IO-device station. The message exchange must be initiated by the

controller.

Acyclic Request/Response Buffers

The shared memory area contains two pairs of buffers (vPN_ACYCLIC_REQ1/2 and

vPN_ACYCLIC_RES1/2) allowing two acyclic requests to be performed simultaneously.:

- vPN_ACYCLIC_REQ1 and vPN_ACYCLIC_REQ2 allow PLC to deposit a request.

- vPN_ACYCLIC_RES1 and vPN_ACYCLIC_RES2 allows to get the respective answers

To manage synchronization, some handshake bits are used. A request buffer can be used to send a

request to any of the configured stations; there is no relation between a request buffer and a particu-

lar station.

Acyclic Handshake Bits

Each request/response buffer pair is associated with a set of handshake bits.

Global Variable Identifier

Description

vPN_MGMT_OUTPUTS.ACYC_HSK_Y_RE

Q1_EXECUTE

execution req. flag for buffer 1

vPN_MGMT_OUTPUTS.ACYC_HSK_Y_RE

Q2_EXECUTE

execution req. flag for buffer 2

vPN_MGMT_INPUTS.ACYC_HSK_X_RES1

_COMPLETED

request in buffer 1 completed, respon-

se is in corresponding buffer

vPN_MGMT_INPUTS.ACYC_HSK_X_RES2

_COMPLETED

request in buffer 2 completed, respon-

se is in corresponding buffer

vPN_MGMT_INPUTS.ACYC_HSK_X_RES1

_ACCEPTED

request in buffer 1 accepted

vPN_MGMT_INPUTS.ACYC_HSK_X_RES2

_ACCEPTED

request in buffer 2 accepted

Once the response has been read by the PLC from the response buffer, the PLC must clear the

ACYC_HSK_Y_REQ<n>_EXECUTE bit corresponding to the request. The PROFINET Controller will

then clear the two corresponding bits ACYC_HSK_X_RES<n>_ACCEPTED and

ACYC_HSK_X_RES<n>_COMPLETED.

The following diagram shows the request/response handshake between PLC program and the

PROFINET Controller for acyclic communication.