Specifications

161User Interface

Data

Check

CPU position

The CPU position is checked for QnU-CPUs and PN controller. QnU-

CPUs must be on the left of every other CPU type including PN con-

troller, QMotion and Q17nNC CPUs. The PN controller must always

be the last CPU on the rack. Only one PN controller is supported.

Even word size of refresh

block

The size of each refresh block must be an even number of words. The

following message is displayed and allows to return and correct the si-

ze or to continue closing the dialog:

Sequence when configuring Multiple PLC Settings

The 'Multiple CPU Settings' dialog allows the configuration of high speed transmission settings on

the CPUs in the PLC rack. However the PLC I/O assignment, which includes the number and slots

of CPUs, must be set in the first QnU-CPU using GX Works2 (GXW2), GX Developer (GD) or GX

IEC Developer (GID). The following screenshots demonstrate, how the I/O assignment is set with

GXW2.

In the 'Q Parameter Setting' dialog the number of slots reserved for CPUs is entered in the tab 'Mul-

tiple CPU Setting'.

After this the tab 'I/O Assignment' can be used to set empty slots and assign the controlling CPU for

additional intelligent modules.

The I/O assignment must be consistent between the CPUs in the same PLC rack. GX Configurator-

PN attempts to set a consistent I/O assignment with the following steps:

1. if the first QnU-CPU has a PLC project path assigned and the PLC project contains an I/O assi-

gnment with at least the same number of CPUs as in the GXPN configuration