Specifications

6 GX Configurator-PN
(c) 2013 MITSUBISHI ELECTRIC CORPORATION
Block
Description
Management Outputs
Control and request flags from the Q-CPU to the PROFINET
Controller
Management Inputs
Status and response flags from the PROFINET Controller to
the Q-CPU
Acyclic Outputs
Request buffer for acyclic communication
Acyclic Inputs
Response buffer for acyclic communication
Cyclic Outputs
Outputs for I/O devices sent during cyclic data exchange
Cyclic Inputs
Inputs from I/O devices received during cyclic data exchange
Access to Shared Memory From PLC Program
GX Configurator-PN generates PLC code for the interaction of the application program with the
PROFINET Controller. The PLC code contains global variables mapped to buffer devices, which are
automatically exchanged between Qn-CPU and PROFINET Controller.
The following diagram shows the principal structure. For details see the section 'Global Variables'.
Addresses in High Speed Area
The settings for the high speed transfer in both the controlling Qn-CPU as well as the ME1PN1FW-Q
are updated by the GX Configurator-PN software. The address range occupied in the high speed area
depends on the size of the cyclic data exchanged between the controller and the I/O devices.
The two following tables list the used high speed memory area addresses for outputs and inputs. Be-
cause the size of the memory areas used for management and for acyclic communication are fixed,
the total size of required high speed buffers depends only on the size of the cyclic data.
For outputs:
Profinet
manage-
ment
Acyclic
Buffer Si-
ze
Max Cy-
clic Out-
put Size
(words)
High Speed Area
Calculated
Minimal Size
Address
Start
Address
End