Specifications

Process Images Appendix
Quick Start Guide for the MELSEC STlite Series A - 15
Control byte C0
Fig. A-17: Control byte C0 of the STL-ENC
Bit Name Description
0EN_LATC
The encoder zero mark is released.
앫 Capture Mode:
With a positive edge at input C the counter reading is transferred to the latch register.
앫 Preload Mode:
With a positive edge at input C the counter reading is transferred to the latch register.
The counter is loaded with the set value.
The confirmation is de-selected for the negative edge of EN_LATC.
EN_LATC is dominant against EN_LAT_EXT.
1EN_LAT_EXT
The external latch input is released.
앫 Capture Mode:
With a positive edge at the input LATCH, the counter reading is transferred to the
latch register.
앫 Preload Mode:
With a positive edge at the input LATCH, the counter reading is transferred to the
Latch register. The counter is loaded with the set value.
The confirmation is de-selected for the negative edge of EN_LAT_EXT.
2 CNT_SET With a positive edge of this bit the counter is initialized on the set value.
3 Reset Underflow With a positive edge of this bit the status bit UNDERFLOW (status byte 0, bit 3) is reset.
4 Reset Overflow With a positive edge of this bit the status bit OVERFLOW (status byte 0, bit 4) is reset.
5 SetLoad Ext
With a positive edge of this bit, the set value to which the counter is to be set in the case
of an external event, will be transferred to the process data.
6OpMode
0 = Capture Mode (The counter is latched by a trigger signal.)
1 = Preload Mode (The counter is latched by a trigger signal. Subsequently, the counter
is loaded with the set value.)
Tab. A-15: Description of the control byte C0 of the STL-ENC
b7 b6 b5 b4 b3 b2 b1 b0
0/10/10/10/10/10/10/10Control byte C0
EN_LATC
EN_LAT_EXT
CNT_SET
Reset Underflow
Reset Overflow
SetLoad Ext
OpMode
Reserved