Specifications

98AEtypMMSspec_RevB.doc

SP-0011 Rev. B 9/5/09

a. Field Programmable Gate Array (FPGA) Control

b. DSP based Control

c. DSP Sampling Frequency is 30 kHz, therefore the control samples 500

times in 1 cycle of output voltage. Output voltage is controlled with high

precision.

B. Voltage Regulation

The inverter output voltage shall not deviate by more than +/- 1% RMS with the

following steady state conditions:

1. 0 to 100% loading.

2. Inverter DC input varies from maximum to minimum.

3. Environmental condition variations within the specifications defined herein.

C. Voltage Adjustments

1. The inverter shall have the ability to manually control and adjust the output

voltage to within +/-5% of the nominal value.

D. Voltage Transient Response

1. The dynamic regulation and transient response shall not exceed +/-2% for

100% step load (applied or removed), +/-1% for loss or return of AC input

and +/-5% for inverter to bypass and vice versa transfer.

E. Transient Recovery

1. Voltage transient response shall not exceed the above specification and

shall recover to within nominal voltage regulation tolerance within 16.7 ms

F. Frequency Control

1. The output frequency of the inverter shall be controlled according to the

unique synchronization control system incorporated in the UPS MMS

Control and the UPS MMS Parallel Operation Control.

2. The main synchronization reference for the Synchronization Master UPS

Module Inverter will be derived from either the bypass source or from the

UPS Modules own internal oscillator – clock (depending on bypass source

availability). All other system Synchronization Slave UPS Modules will

utilize the cross current control signals between the UPS Modules for

synchronization reference by means of fast simultaneous inverter

reference voltage and phase waveform control.

3. The lowest number UPS Module operating in the system will be designated

as the Synchronization Master. The Synchronization Master UPS Module

shall track the bypass source within the selected bypass synchronous

range (default 1% - selectable from 1% to 5% in 1% increments).

4. When the Synchronization Master UPS Module is running in asynchronous

mode (own oscillator), output frequency specification shall be within

nominal +/-0.05%. The inverter output frequency shall not vary during

steady state or transient operation due to the following conditions:

a. 0 to 100% loading.