Specifications
2033D Specification
10
4.2 Inverter
4.2.1 General
The Inverter shall generate AC power that is derived from DC power supplied
from the Converter or the system battery. The Inverter shall be capable of
providing rated output as stated in section 3.4 while operating from any DC
voltage within the battery operating range. The Inverter shall utilize the following
technologies:
a. Solid state PWM controlled IGBT power transistors switching at 8 kHz.
Switching shall be defined as IGBT turn on and turn off rate. Doubling of
frequency at inverter output shall not be considered as the true switching
frequency.
b. DSP based control logic.
4.2.2 Voltage Regulation
The Inverter output voltage shall not deviate by more than +/- 1% RMS due to the
following steady state conditions:
a. 0 to 100% loading.
b. Inverter DC input varies from maximum to minimum.
c. Environmental condition variations within the limitations set in section 3.5.
4.2.3 Frequency Control
The Inverter output frequency shall be controlled by an oscillator internal to the
UPS module logic. It shall be capable of synchronizing to an external reference
(e.g.; the bypass source) or operating asynchronously. The oscillator shall
maintain synchronization with the external reference within the limitations set in
section 3.3.3. A message located on the touch screen shall identify the loss of
synchronization. Synchronization shall be maintained at 60 Hz r 0.05%
continuously. The Inverter output frequency shall not vary during steady state or
transient operation due to the following conditions:
a. 0 to 100% loading.
b. Inverter DC input varies from maximum to minimum.
c. Environmental condition variations within the limitations set in section 3.5.
4.2.4 Output Harmonic Distortion
The Inverter output shall limit the amount of harmonic content to the values stated
in section 3.4.8. The use of excessive or additional filtering shall not be required
to limit the harmonic content thus maintaining a high level of efficiency, reliability
and original equipment footprint.
4.2.5 Output Overload Capability