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FXCPU

Structured Programming Manual

Basic & Applied Instruction

Summary of content (838 pages)

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FXCPU Structured Programming Manual Basic & Applied Instruction
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FXCPU Structured Programming Manual [Basic & Applied Instruction] FXCPU Structured Programming Manual [Basic & Applied Instruction] Manual number JY997D34701 Manual revision L Date 9/2013 Foreword This manual contains text, diagrams and explanations which will guide the reader through the safe and correct installation, use, and operation of the FX Series programmable controller function for structured programs. It should be read and understood before attempting to install or use the unit.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Outline Precautions • This manual provides information for the use of the FX Series Programmable Controllers. The manual has been written to be used by trained and competent personnel.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Table of Contents Table of Contents Positioning of This Manual..................................................................................................... 11 Related Manuals ...................................................................................................................... 14 Generic Names and Abbreviations Used in Manuals .......................................................... 17 1. Outline 18 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Table of Contents 5.13 END............................................................................................................................................. 91 5.14 NOP (for simple project only) .................................................................................................. 91 6. Step Ladder Instructions 92 6.1 Step Ladder ......................................................................................
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 10. Applied Instructions (Rotation and Shift Operation) Table of Contents 195 10.1 ROR / Rotation Right .............................................................................................................. 196 10.2 ROL / Rotation Left ................................................................................................................. 199 10.3 RCR / Rotation Right with Carry ...........................................
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Table of Contents 13.5 TTMR / Teaching Timer........................................................................................................... 334 13.6 STMR / Special Timer.............................................................................................................. 337 13.7 ALT / Alternate State............................................................................................................... 340 13.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 18. Applied Instructions (Floating Point) Table of Contents 439 18.1 DECMP / Floating Point Compare.......................................................................................... 441 18.2 DEZCP / Floating Point Zone Compare................................................................................. 443 18.3 DEMOV / Floating Point Move..........................................................................................
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 21. Applied Instructions (Real Time Clock Control) 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 540 TCMP / RTC Data Compare .................................................................................................... 541 TZCP / RTC Data Zone Compare ........................................................................................... 544 TADD / RTC Data Addition ................................................................
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 27. Applied Instructions (Data Operation 3) 27.1 27.2 27.3 27.4 27.5 Table of Contents 653 FDEL / Deleting Data from Tables ......................................................................................... 654 FINS / Inserting Data to Tables .............................................................................................. 657 POP / Shift Last Data Read [FILO Control] ...................................................
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Table of Contents 33.4 LOGR / Logging R and ER...................................................................................................... 761 33.5 RWER / Rewrite to ER............................................................................................................. 765 33.6 INITER / Initialize ER ............................................................................................................... 770 34.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Positioning of This Manual This manual explains sequence instructions for structured programs provided by GX Works2. Refer to other manuals for devices, parameters and application functions. Refer to each corresponding manual for analog, communication, positioning control and special units and blocks. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 2. When using FX1S/FX1N/FX1NC/FX2N/FX2NC PLCs MELSEC-Q/L/F Structured Programming Manual (Fundamentals) (Additional Manual) Q/L/F This manual explains programming methods, specifications, functions, etc. required to create structured programs. Structured FXCPU Structured Programming Manual [Device & Common] (Additional Manual) FX This manual explains devices and parameters for structured programs provided by GX Works2.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 3. When using FX0S/FX0/FX0N/FXU/FX2C PLCs MELSEC-Q/L/F Structured Programming Manual (Fundamentals) (Additional Manual) Q/L/F This manual explains programming methods, specifications, functions, etc. required to create structured programs. Structured FXCPU Structured Programming Manual [Device & Common] (Additional Manual) FX This manual explains devices and parameters for structured programs provided by GX Works2.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Related Manuals This manual explains devices and parameters for structured programs provided by GX Works2. Refer to other manuals for sequence instructions and applied functions. This chapter introduces only reference manuals for this manual and manuals which describe the hardware information of PLC main units. Manuals not introduced here may be required in some applications.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Manual name Manual number Supplied with product or Additional Manual Contents Model name code PLC main unit I/O specifications, wiring and installation of the PLC main unit FX3S extracted from the FX3S Series User's Manual - Hardware Edition. For detailed explanation, refer to the FX3S Series User's Manual - Hardware Edition.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] FX0S/FX0/FX0N/FXU/FX2C PLCs [whose production is finished] Manual number Supplied with product or Additional Manual FX0/FX0N HARDWARE MANUAL JY992D47501 Supplied with product Details about the hardware including I/O specifications, wiring, installation and maintenance of the FX0/FX0N PLC main unit.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Generic Names and Abbreviations Used in Manuals Abbreviation/generic name Name PLCs FX3U Series or FX3U PLC Generic name of FX3U Series PLCs FX3UC Series or FX3UC PLC Generic name of FX3UC Series PLCs FX3G Series or FX3G PLC Generic name of FX3G Series PLCs FX3GC Series or FX3GC PLC Generic name of FX3GC Series PLCs FX3S Series or FX3S PLC Generic name of FX3S Series PLCs FX2N Series or FX2N PLC Generic name of FX2N Series PLCs
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 1. 1 Outline 1.1 Outline of Structured Programs and Programming languages Outline This manual explains setting of sequence instructions for structured programs provided by GX Works2. Refer to another manuals for device, parameter, and application functions for structured programs. Refer to the following manual for label, data types and programming languages for structured programs. → Q/L/F Structured Programming Manual (Fundamentals) 1.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1 Programming languages Outline 1.1.2 1.1 Outline of Structured Programs and Programming languages The following programming languages can be used in each program block. Graphic languages 2 This graphic language is created based on the relay circuit design technology. A circuit always starts from the bus line located on the left side.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1.2 1.2 PLC Series and Programming Software Version PLC Series and Programming Software Version PLC series Software package name (model name) GX Works2 version FX3U•FX3UC FX3G FX2N•FX2NC FX1N•FX1NC FX1S FXU•FX2C Ver. 1.08J or later GX Works2 (SW1DNC-GXW2-E) FX0N FX0•FX0S 1.3 FX3GC Ver. 1.77F or later FX3S Ver. 1.492N or later Cautions on Creation of Fundamental Programs This section explains cautions on programming.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1 Double output (double coil) operation and countermeasures Outline 1.3.2 1.3 Cautions on Creation of Fundamental Programs This subsection explains the double output (double coil) operation and countermeasures. 1. Operation of double output Suppose that the same coil Y003 is used in two positions as shown in the figure on the right. For example, suppose that X001 is ON and X002 is OFF.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1.3.3 1.3 Cautions on Creation of Fundamental Programs Circuits which cannot be created by structured ladder programs and countermeasures 1. Bridge circuit A circuit in which the current flows in both directions should be changed as shown in the figure on the right (so that a circuit without D and a circuit without B are connected in parallel). A F B C B E D F A E A C E D C 2.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1.3 Cautions on Creation of Fundamental Programs If you program the instruction execution completion flag M8029 for two or more sequence instructions which actuate the flag M8029, you cannot judge easily by which sequence instruction the flag M8029 is controlled. In addition, the flag M8029 does not turn ON or OFF correctly for each corresponding sequence instruction.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1.3 Cautions on Creation of Fundamental Programs 2. Introduction of method for using flags in any positions other than directly under sequence instructions. When two or more sequence instructions are programmed, general flags turn ON or OFF when each sequence instruction turns ON.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1 Handling of operation error flag When there is an error in the sequence instruction configuration, target device or target device number range and an error occurs while operation is executed, the following flag turns ON and the error information is store. 1. Operation error 2 Instruction List Device storing error occurrence step *1.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1.3.7 1.3 Cautions on Creation of Fundamental Programs Limitation in the number of instructions and limitation in simultaneous instruction instances Each sequence instruction has a limitation in the number of using the instruction and the number of simultaneous instances of instructions. The limitation, however, differs from one PLC to another.
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FXCPU Structured Programming Manual 1 Outline [Basic & Applied Instruction] 1.3 Cautions on Creation of Fundamental Programs 1 Instruction name Outline FX0S, FX0, FX0N, FXU and FX2C PLCs Allowable number of times of use Remarks MTR 1 FX0, FX0S or FX0N PLCs are not provided. PLSY 1 PWM 1 1 ABSD 1 INCD 1 ROTC 1 1 TKY 1 HKY 1 DSW 2 SEGL 2 ARWS 1 PR 2 - 3 FX0S, FX0 or FX0N PLCs are not provided.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2. 2.1 Basic Instructions Instruction List This chapter introduces a list of instructions available in programming. 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 1 Step Ladder Instructions Outline 2.2 2.2 Step Ladder Instructions Applicable PLCs FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) STL Starts step ladder 3 3 3 3 3 3 3 3 3 Section 6.2 RET Completes step ladder 3 3 3 3 3 3 3 3 3 Section 6.3 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.3 Applied Instructions 1 Outline Applicable PLCs FX0N FX0(S) 3 3 3 3 3 Reference 2 Arithmetic and Logical Operation WXOR Continuous 3 3 3 3 3 3 WXORP Pulse 3 3 3 3 3 3 3 DXOR Continuous 3 3 3 3 3 3 3 DXORP Pulse 3 3 3 3 3 3 3 Logical exclusive OR Continuous 3 3 3 Pulse 3 3 3 DNEG Continuous 3 3 3 DNEGP Pulse 3 3 3 Negation 3 Section 9.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.3 Applied Instructions 1 Outline Applicable PLCs FX1N(C) FX1S FXU/FX2C 3 3 3 3 3 ALTP Pulse 3 3 3 3 3 3 3 RAMP Pulse 3 3 3 3 3 3 3 3 3 3 3 Reference 2 Handy Instruction STMR Alternate state Ramp variable value 3 Section 13.6 3 Section 13.7 Section 13.8 Continuous Rotary table control 3 3 3 Section 13.9 SORT Continuous SORT tabulated data 3 3 *1 Section 13.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.3 Applied Instructions 1 Outline Applicable PLCs FX0(S) FX0N FXU/FX2C FX1S FX1N(C) FX2N(C) FX3S Function FX3G(C) Execution condition FX3U(C) Instruction name Reference 2 DESTR DESTRP DEVAL Continuous Floating point to character string conversion Pulse 3 Section 18.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.3 Applied Instructions Applicable PLCs FX0(S) FX0N FXU/FX2C FX1S FX1N(C) FX2N(C) FX3S Function FX3G(C) Execution condition FX3U(C) Instruction name Reference Data Operation 2 WSUM Continuous WSUMP Pulse DWSUM Continuous DWSUMP Pulse WTOB Continuous WTOBP Pulse BTOW Continuous BTOWP Pulse UNI Continuous UNIP Pulse DIS Continuous DISP Pulse *1 Sum of word data *1 Section 19.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.3 Applied Instructions 1 Outline Applicable PLCs FX0(S) FX0N FXU/FX2C FX1S FX1N(C) FX2N(C) FX3S FX3G(C) Function FX3U(C) Execution condition Instruction name Reference 2 TRD Continuous TRDP Pulse TWR Continuous TWRP Pulse Continuous Continuous Set RTC data Hour meter 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 *1 3 3 3 3 3 *1 3 3 Section 21.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual 2 Instruction List [Basic & Applied Instruction] 2.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 3. 3 Configuration of Instruction 3.1 Expression and Operation Form of Sequence Instructions Configuration of Instruction This chapter explains the configuration of sequence instructions. 3.1 Expression and Operation Form of Sequence Instructions Instructions and arguments • Each instruction is given a specific name that indicates its contents. "SMOV" (shift move) is one of such examples.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 3 Configuration of Instruction 3.1 Expression and Operation Form of Sequence Instructions 1 Instructions are divided into "16-bit instructions" and "32-bit instructions" depending on the size of values they handle. The instructions also have characteristics of either a "continuous execution" or "pulse execution" depending on the form of execution. Some of the instructions have all these combinations.
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FXCPU Structured Programming Manual 3 Configuration of Instruction [Basic & Applied Instruction] 3.2 3.2 Labels Labels Types of labels Labels are either global labels or local labels. • Global labels are available for use in program blocks and function blocks. • Local labels are available for use only in a declared program part. Label classes The label classes indicate how they are used in which program parts. The table below shows the label classes.
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FXCPU Structured Programming Manual 3 Configuration of Instruction [Basic & Applied Instruction] 3.2 Labels 1 Outline • When using as a local label: Set the class, label name and data type. 2 Instruction List 3 Configuration of Instruction Expressing constants The following describes the method of expression when setting constant to a label. Type of constant Method of expression Example Enter either "FALSE" or "TRUE", or either "0" or "1".
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FXCPU Structured Programming Manual 3 Configuration of Instruction [Basic & Applied Instruction] 3.2 Labels • The universal data type is the data type of a label that puts together several basic data types. The data type name starts with "ANY".
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FXCPU Structured Programming Manual 3 Configuration of Instruction [Basic & Applied Instruction] 1 Devices and Addresses Outline 3.3 3.3 Devices and Addresses A device is expressed by a device or an address. Device 2 X0 D 100 Device name Device number Instruction List The device is expressed by a device name and a device number. 3 Configuration of Instruction Address An address is expressed by a method defined by IEC61131-3. It is expressed as follows according to IEC61131-3.
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FXCPU Structured Programming Manual 3 Configuration of Instruction [Basic & Applied Instruction] 3.4 3.4 EN and ENO EN and ENO The execution control is available for an instruction with "EN". • EN is for entering an execution condition of instruction. • ENO is for outputting the state of execution of instruction. • The table below shows the relationships between the EN and ENO and the contents of operation results.
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3 Configuration of Instruction FXCPU Structured Programming Manual 3.
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FXCPU Structured Programming Manual 4 How to Read Explanation of Instructions [Basic & Applied Instruction] 4. How to Read Explanation of Instructions The following shows one of the pages that explains the instructions. * The above is different from the actual page, as it is provided for explanation only.
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FXCPU Structured Programming Manual 4 How to Read Explanation of Instructions [Basic & Applied Instruction] 1 Outline 1) Indicates the corresponding chapter, section, subsection, number and instruction name. 2) Indicates the PLCs that support the instruction. Item Descriptions Supported by PLCs from the first release. The support conditions depend on the versions. "Cautions" explains the applicable versions. 2 Instruction List This particular series PLCs do not support the instruction.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5. Basic Instruction This chapter introduces the instructions for the structured project corresponding to the basic instructions for the simple project. Instruction name Reference Initial logical operation of NO (normally open) contacts Section 5.1 LDI Initial logical operation of NC (normally closed) contact type Section 5.1 AND Serial connection of NO (normally open) contacts Section 5.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 LD, LDI, AND, ANI, OR, ORI Outline 5.1 5.1 LD, LDI, AND, ANI, OR, ORI FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline The LD and LDI instructions are contacts connected to bus lines. The AND and ANI instructions connect one contact in series. The OR and ORI instructions connect one contact in parallel. 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.1 LD, LDI, AND, ANI, OR, ORI Function and operation explanation 1. LD (Initial logical operation of NO (normally open) contacts) [Structured ladder/FBD] LD [ ST ] Y000 X000 Y000:= X000; Bus line timing chart X000 ON ON Y000 ON ON 2.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.1 LD, LDI, AND, ANI, OR, ORI 1 [Structured ladder/FBD] Outline 4. ANI (Serial connection of NC (normally closed) contacts) [ ST ] ANI X002 X000 Y003:= X002 AND NOT X000; Y003 2 Instruction List timing chart X002 ANI X000 ON ON ON ON ON Y003 3 Configuration of Instruction LD ON 4 How to Read Explanation of Instructions 5.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 5 Basic Instruction 5.1 LD, LDI, AND, ANI, OR, ORI 7. Relationship with AND (...) AND(...) LD The parallel connection by OR or ORI instruction is connected to the preceding LD or LDI instruction in principle. The "AND (...) after" instruction, however, the parallel connection by OR or ORI instruction is connected to the second preceding LD or LDI instruction. LD OR OR AND (...) before OR OR AND (...) after 8.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 LDP, LDF, ANDP, ANDF, ORP, ORF FX3U(C) FX3G(C) Outline 5.2 5.2 LDP, LDF, ANDP, ANDF, ORP, ORF FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Contact instructions LDP, ANDP, and ORP detect the rising edge, and become active during one operation cycle only at the rising edge of a specified bit device (that is, when the bit device turns ON from OFF).
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.2 LDP, LDF, ANDP, ANDF, ORP, ORF 3. Applicable devices Bit Devices Word Devices System User Instruction Digit Specification System User Special Unit X Y M T C S D .
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.2 LDP, LDF, ANDP, ANDF, ORP, ORF 5. Differences in the operation caused by auxiliary relay (M) numbers Not supported by the FX1S, FX1N or FX1NC PLC. When an auxiliary relay (M) is specified as a device in LDP, LDF, ANDP, ANDF, ORP and ORF instructions, the operation varies depending on the device number range as shown in the figure below.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.2 LDP, LDF, ANDP, ANDF, ORP, ORF 1 1) When LDP, LDF, ANDP, ANDF, ORP or ORF instruction programmed in a same step is executed two or more times within one operation cycle, the operation is as follows. KOO X000 EN s EN n FOR ENO LDP ENO OFF Not executed Not executed ON Executed*1 Not executed *1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.3 5.3 OUT (Excluding timers and counters) OUT (Excluding timers and counters) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction outputs the operation result up to the execution of the OUT instruction to the specified device. 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.3 OUT (Excluding timers and counters) 1 Outline Function and operation explanation 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.3 OUT (Excluding timers and counters) Cautions 1) Some restrictions to applicable devices S1: The FX3U and FX3UC PLCs only are applicable. S2: Only the FX3U and FX3UC PLCs are capable of indexing applicable devices. The following devices cannot be indexed. • Special auxiliary relays (M) • State (S) • Word bit specification "D .
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.4 Operating Timer Operating Timer 5.4.1 OUT_T Outline 5.4 1 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Instruction List Outline An output is generated when a set time expires. 3 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.4 Operating Timer Function and operation explanation 1. OUT_T operation 1) When the operation result up to the OUT_T instruction operation is ON, the timer coils is ON and counts until the set value is reached. When the set time expires (or reaches the set count), the contacts become as follows: NO (normally open) contact Timer is conductive. NC (normally closed) contact Timer is not conductive.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 5 Basic Instruction 5.4 Operating Timer 1 Outline Cautions 1) When a timer device is specified in a program, use the following depending on the locations of use. - Used as contacts: TS - Used as a coil: TC - Used as a current value: TN 4) Some restrictions to applicable devices S1: The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S2: The target device can be indexed only by the FX3U and FX3UC PLCs.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.4 Operating Timer Program example 1. Program that turns ON Y010 and Y014 in 10 seconds after X000 turns ON. [Structured ladder/FBD] X000 TC1 100 TS1 [ ST ] OUT_T(X000,TC1,100); OUT(TS1,Y010); OUT(TS1,Y014); OUT_T EN ENO TCoil TValue Y010 Y014 2. Program that sets the BCD data of X010 to X01F to a timer.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.5 Operating Counters Operating Counters 5.5.1 OUT_C, OUT_C_32 Outline 5.5 1 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) The counter starts counting when the condition turns ON from OFF. It generates an output when counting up to the set value.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.5 Operating Counters 2. Counter reset After completing to count, the count value and contact condition does not change until the RST instruction is executed. 3. Counter set value The set value of the counter can be specified directly by a decimal number (K) or indirectly using a data register (D) or extension register (R). Indirect setting by the extension register (R) is applicable only to the FX3U and FX3UC PLCs.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 AND(...), OR(...) Outline 5.6 5.6 AND(...), OR(...) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Use AND (...) instruction to connect a branch circuit (parallel circuit block) to the preceding circuit in series. Use OR (...) instruction to connect a series circuit block in parallel. 1. Format and operation, execution form AND(...
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 5 Basic Instruction 5.6 AND(...), OR(...) Function and operation explanation 1. AND(...)(Serial connection of circuit blocks) AND (...) is an independent instruction not associated with any device number in the same way as the OR (...) instruction described later. When there are many parallel circuits, the AND (...) instruction can be used for each circuit block to connect them.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 MPS, MRD, MPP Outline 5.7 5.7 MPS, MRD, MPP FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 These PLCs have 11 memories called "Stack" which store the intermediate result (ON or OFF) of operations. 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.7 MPS, MRD, MPP Function and operation explanation These instructions are convenient in programming branched multi-output circuits. 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.7 MPS, MRD, MPP 1 Outline Program example 1. Program example 1 (One stack) Only one stack is used in this example.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.7 MPS, MRD, MPP 3. Program example 3 (Two stacks) [Structured ladder/FBD] [ ST ] MPS MPS X001 X002 ENO EN ENO Y000 EN MPP X003 ENO Y001 EN MPP MPS X004 X005 ENO EN ENO Y002 EN MPP ENO Y003 EN X000 X006 Y000:= (MPS(X000) AND MPS(X001)) AND X002; Y001:= MPP(TRUE) AND X003; Y002:= (MPP(TRUE) AND MPS(X004)) AND X005; Y003:= MPP(TRUE) AND X006; 4.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 INV Outline 5.8 5.8 INV FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline INV instruction inverts the operation result up to just before INV instruction. 1. Format and operation, execution form Execution form INV Continuous Expression in each language Structured ladder/FBD EN 3 ST INV ENO Configuration of Instruction Instruction name INV(EN); 2.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.8 INV 2.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 MEP, MEF Outline 5.9 5.9 MEP, MEF FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 MEP and MEF commands are instructions that change the operation results to pulses so that device numbers do not have to be specified. 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.9 MEP, MEF Function and operation explanation 1. MEP(ON during rising edge of driving contacts results) Timing chart [Structured ladder/FBD] X000 X001 EN MEP ENO EN SET ENO d X000 OFF X001 OFF ON M0 OFF ON M0 [ ST ] SET(MEP(X000 AND X001),M0); ON 2.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 SET, RST Outline 5.10 5.10 SET, RST FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 1) Setting a bit device (SET instruction [holding operation]) When the command input turns ON, SET instruction sets to ON an output relay (Y), auxiliary relay (M), state relay (S) and bit specification of word device.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.10 SET, RST Function and operation explanation SET instruction drives the coil for an output relay (Y), auxiliary relay (M), state relay (S) and bit specification of data register (D). 1. When using a bit device SET instructions located in parallel can be used consecutively as many times as necessary. In the program example shown below, RST (X1001, Y000) after SET (X000, Y000) corresponds to this usage.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.10 SET, RST 1 Outline 2. When using word device (timer or counter) Use RST instruction to reset a counter or retentive type timer.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 5 Basic Instruction 5.10 SET, RST 3. Indexing Devices used in SET and RST instructions can be indexed with index registers (V, Z). (State relays (S), special auxiliary relays (M), 32-bit counters, "D .b" and word devices cannot be indexed.) This is applicable only to the FX3U and FX3UC PLCs.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 PLS, PLF Outline 5.11 5.11 PLS, PLF FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 1. Format and operation, execution form Expression in each language Instruction Execution name form Structured ladder/FBD 4 ST Pulse EN PLF Pulse EN ENO d PLS(EN,d); ENO d PLF(EN,d); How to Read Explanation of Instructions PLS PLS PLF 5 Basic Instruction 2.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.11 PLS, PLF 3. Output drive side The following two circuits cause a same operation. <> X000 <> M0 M1 = M1 X000 PLS X000 EN ENO d M0 ON X000 ON during one operation cycle M 0 ON M 1 In each case, M0 is ON during only one operation cycle when X000 changes from OFF to ON.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 MC, MCR Outline 5.12 5.12 MC, MCR FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline When MC instruction is executed, instructions from MC to MCR are executed. Thereby, efficient ladder switching sequence programs can be created. 1.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.12 MC, MCR Function and operation explanation When MC instruction is executed, instructions from MC to MCR are executed. When MC instruction is not executed, the operation with the contact OFF is executed. In the program example below, the instructions from MC to MCR are executed as they are while the input X000 is ON. However, while the input X000 is OFF, each drive device offers the following operation.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.12 MC, MCR 1 Outline Program examples 1. When the nesting structure is not adopted. [Structured ladder/FBD] 2 MC X000 ENO d X001 Y000 X002 Y001 0 EN n M100 3 Configuration of Instruction 0 MCR EN ENO n Instruction List 0 EN n 4 MC X003 X004 Y002 X005 Y003 When not adopting the nesting structure, use nesting level "0" again to program.
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 5.12 MC, MCR 2. When the nesting structure is adopted. When using MC instructions inside MC instruction, increase the nesting level "N" in turn in the way "N0 → N1 → N2 → N3 → N4 → N5 → N6 → N7". For returning from the nesting structure, reset the nesting levels from the highest one in turn using MCR instruction in the way "N7 → N6 → N5 → N4 → N3 → N2 → N1 → N0".
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FXCPU Structured Programming Manual 5 Basic Instruction [Basic & Applied Instruction] 1 END Outline 5.13 5.13 END FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 END instruction specifies the end of a program. (Do not write the END instruction in the middle of a program.) END instruction for ending a program and input/output processing and returning to 0 step is automatically written at the end of the program. It cannot be programmed into program structural elements (POU).
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 6. 6.1 6 Step Ladder Instructions 6.1 Step Ladder Step Ladder Instructions Step Ladder This chapter introduces the instructions of structured project that correspond to the MELSEC-LD step ladder instructions. 6.1.1 Outline In programs using step ladder instructions, a state relay S is assigned to each process based on machine operations, and input condition and output control are programmed as sequences connected to the state output. 6.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.1 Step Ladder 1 STL ENO STL ENO 3 EN Process of S32 SET ENO d 4 S33 Y030 Y31 SET ENO d S32 5 Y31 programmed in SET instruction remains ON even if S31 is reset. 6 Step Ladder Instructions STL ENO EN SET ENO d Basic Instruction X001 S32 S32 Y032 EN EN s When X001 turns ON, S32 turns ON and S31 is automatically reset.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.1 Step Ladder • Special auxiliary relays For efficiently creating step ladder programs, it is necessary to use some special auxiliary relays. The table below shows major ones. Device number Name Function and application M8000 RUN monitor This relay is normally ON while the PLC is in the RUN mode.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.1 Step Ladder 1 S20 EN s STL ENO Outline • Output driving method It is required to include a LD or LDI instruction before the last OUT instruction in a state relay. Change such a circuit as shown below.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.1 Step Ladder • Example of selective recombination Do not use MPS, MRD, MPP, AND (…) and OR (…) instructions in a transfer processing program with branches and recombination. Even in a load driving circuit, MPS instructions cannot be used immediately after STL instructions. Pay attention to the programming order so that a branch line does not cross a recombination line.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 1 Program examples Outline 6.1.3 6.1 Step Ladder Examples of single flows 2 1. Example of flicker circuit Instruction List • When the PLC mode is changed from STOP to RUN, the state relay S3 is driven by the initial pulse (M8002). • The state relay S3 outputs Y000. One second later, the ON status transfers to the state relay S20. • The state relay S20 outputs Y001. 1.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.2 6.2 STL STL FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline In programs using step ladder instructions, a state relay State S is assigned to each process based on machine operations, and input condition and output control are programmed as sequences connected to the state output. STL instruction for step ladder programs is expressed as follows in each language. 1.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 1 RET Outline 6.3 6.3 RET FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline RET instruction for step ladder programs is expressed as follows in each language. 1.
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FXCPU Structured Programming Manual 6 Step Ladder Instructions [Basic & Applied Instruction] 6.3 RET 4. Caution The following examples show how MELSEC-LD step ladders are expressed in the structured programs. Reference: MELSEC-LD step ladder expression 1) When expressing step ladder (STL) instructions in the coil format. (Same as that for GX Developer) 2) When expressing step ladder (STL) instructions in the contact format.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 Outline 7. Applied Instructions (Program Flow) Instruction name CJ Function Reference Section 7.1 Call Subroutine Section 7.2 SRET Subroutine Return Section 7.3 IRET Interrupt Return Section 7.4 DI Disable Interrupt Section 7.5 EI Enable Interrupt Section 7.6 CALL CALLP Main Routine Program End Section 7.7 WDT Watchdog Timer Refresh Section 7.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 7.1 CJ / Conditional Jump CJ / Conditional Jump FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline CJ or CJP instruction jumps to the specified pointer number or ladder block label. The sequence program steps between CJ or CJP instruction and the pointer are not executed. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 CJ / Conditional Jump 1 Outline Function and operation explanation 1. 16-bit operation(CJ, CJP) While the command input is ON, CJ or CJP instruction executes a program with a specified pointer number or ladder block label. 1) In the case of CJ instruction Instruction List User program Command Jumps to the pointer P10 while the command is ON.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 CJ / Conditional Jump 4) When the pointer number or ladder block label specified by is same and there is one jump destination, the following operation is caused. When X020 turns ON, the program execution jumps from CJ instruction corresponding to X020 to the pointer P9. When X020 turns OFF and X021 turns ON, the program execution jumps from CJ instruction corresponding to X021 to the pointer P9.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 CJ / Conditional Jump M8000 RUN monitor EN p P5 CJ ENO 2 Instruction List User program (It is skipped, and is not executed.) P5: User program 3 10) The relationships between the master control instructions and jump instructions are described later. 11) The jumping ranges of CJ instruction is different according to the pointer type specified by .
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 CJ / Conditional Jump CJ instruction and operations of contact and coil In the program example shown below, when X000 turns ON, the program execution jumps from CJ instruction in the first circuit to the pointer P8. While X000 is OFF, jump is executed. The program is sequentially executed from first step, and jumps from 11th circuit to the pointer P9. The jumped instruction is not executed. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 CJ / Conditional Jump 1 X012 When X011 turns ON while the RST instruction for the counter C0 is operating (X010 is ON), the program execution jumps past the RST instruction due to the CJ instruction. In this jump status, the counter C0 remains reset. Accordingly, the current value of C0 remains "0" even if X012 turns ON.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.1 CJ / Conditional Jump Timing chart Jump operation by CJ instruction driven by X011 X012 5 3 Current value of C0 4 Counter is reset. 2 1 3 2 1 X010 ON *1 In the same operating cycle as the reset, the reset status of counter C0 is cleared.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 CALL / Call Subroutine Outline 7.2 7.2 CALL / Call Subroutine FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 1. Format and operation, execution form Instruction Operation name Structured ladder/FBD CALL EN ENO p Continuous CALLP EN ENO p Pulse 4 Use a subroutine program by reading out the function block made of other program parts.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.2 CALL / Call Subroutine Function and operation explanation 1. 16-bit operation While the command input is ON, CALL instruction is executed and the program execution jumps to a step with a specified pointer number or ladder block label. Then, the corresponding subroutine program is executed. When SRET instruction is executed, the program execution returns to the step after CALL instruction.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.2 CALL / Call Subroutine 1 Outline Program examples 1. Example of fundamental use (no nesting) X000 P10 EN p CALL ENO 2 Instruction List Main program While X000 is ON, the program execution jumps to a step with the label P10.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.2 CALL / Call Subroutine Cautions on subroutines and interrupt routines This section explains cautions on creating programs in subroutines and interrupt routines. The explanation below is given for subroutines, but the situation also applies to interrupt routines. 1. When using timers in subroutines (or interrupt routines) Use retentive type timers T192 to T199 in subroutines.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.2 CALL / Call Subroutine 1 Outline 2) Example for resetting held outputs (countermeasures) • Program examples X000 P0 CC0 K10 X002 2 OUT_C EN ENO CCoil CValue RST ENO d 3 Y007 is reset at an arbitrary timing.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.3 7.3 SRET / Subroutine Return SRET / Subroutine Return FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction returns the program execution from a subroutine to the main program. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 IRET / Interrupt Return Outline 7.4 7.4 IRET / Interrupt Return FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction returns the program execution from an interrupt routine to the main program. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.4 IRET / Interrupt Return Cautions 1) Create a task for the interrupt program and the main program. 2) Use "Event" to specify the interrupt pointer to be used for the task for the interrupt program. → For the interrupt pointer, refer to Chapter 35.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 7 Applied Instructions (Program Flow) 7.4 IRET / Interrupt Return 1 Outline Program examples [Structured ladder/FBD] Task for main program EI M8000 CC255 K100 ENO OUT_C EN ENO CCoil CValue Main program 2 Instruction List EN Interrupts are usually disabled in PLCs. Use EI instruction to enable interrupts.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.5 7.5 DI / Disable Interrupt DI / Disable Interrupt FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction disables interrupts after interrupts were enabled by EI instruction. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 EI / Enable Interrupt Outline 7.6 7.6 EI / Enable Interrupt FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline Interrupts are usually disabled in PLCs. This instruction enables interrupts in PLCs. Use this instruction for using the input interrupt, timer interrupt and counter interrupt functions. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 7 Applied Instructions (Program Flow) 7.6 EI / Enable Interrupt Cautions 1) Refer to the following items for the cautions on the interrupt program. → Refer to Section 7.4. 2) Use the EI instruction as follows when the FXU, FX2C, FX2N, FX2NC, FX3U and FX3UC PLCs use the pulse catch function. The IE instruction does not need to be programmed when the FX0S, FX0, FX0N, FX1S, FX1N, FX1NC, FX3S, FX3G or FX3GC PLC uses the pulse catch function.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 FEND / Main Routine Program End FX3U(C) FX3G(C) FX3S Outline 7.7 7.7 FEND / Main Routine Program End FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction indicates the end of the main program. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.7 FEND / Main Routine Program End 2. In the case of CALL instruction Main routine program X011 P21 EN p CALL ENO Main routine program *2 FEND EN ENO P21 When X011 is OFF When X011 is ON 0 Subroutine program *1 *1. If task names other than "MELSEC_MAIN" are used, FEND instruction is added automatically, and cause an error. Refer to item 6 of "Cautions".
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 WDT / Watchdog Timer Refresh Outline 7.8 7.8 WDT / Watchdog Timer Refresh FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction refreshes the watchdog timer in a sequence program. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.8 WDT / Watchdog Timer Refresh Cautions 1) Instructions of pulse operation type are not provided in the FX0S, FX0 or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. 2) A watchdog timer error may occur in the following cases.
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Outline FOR ENO 2 EN n K30000 7.8 WDT / Watchdog Timer Refresh [Basic & Applied Instruction] 7 Applied Instructions (Program Flow) FXCPU Structured Programming Manual 1 3. When FOR/NEXT instruction is repeated many times Put WDT instruction between FOR and NEXT.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.9 7.9 FOR / Start a FOR/NEXT Loop FOR / Start a FOR/NEXT Loop FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline FOR instruction specifies the number of repetition of the loop between FOR and NEXT instructions. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 1 NEXT / End a FOR/NEXT Loop Outline 7.10 7.10 NEXT / End a FOR/NEXT Loop FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline FOR instruction specifies the number of repetition of the loop between FOR and NEXT instructions. 1.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.10 NEXT / End a FOR/NEXT Loop Cautions FOR-NEXT loop can be nested up to 5 levels.
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FXCPU Structured Programming Manual 7 Applied Instructions (Program Flow) [Basic & Applied Instruction] 7.10 NEXT / End a FOR/NEXT Loop 1 Outline Program examples 1. Program example with three FOR-NEXT loops 2 Instruction List K4 FOR ENO EN n The loop 3) is repeated 4 times. D0Z P22 EN p CJ ENO FOR EN ENO n EN NEXT ENO 1) 7 times NEXT ENO 6 times Number of times of repeating the loops 1), 2) and 3).
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8. Applied Instructions (Move and Compare) This chapter introduces fundamental data processing instructions such as data transfer and data comparison which are regarded as most important in applied instructions. Instruction name Function Reference CMP CMPP DCMP Compare Section 8.1 Zone Compare Section 8.2 Move Section 8.3 Shift Move Section 8.4 Complement Section 8.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 CMP / Compare Outline 8.1 8.1 CMP / Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 This instruction compares two values, and outputs the result (smaller, equal or larger) to bit devices (3 points). → For the contact comparison instruction, refer to Chapter 28. → For floating point comparison, refer to Section 18.1. 3 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.1 CMP / Compare Function and operation explanation 1. 16-bit operation(CMP, CMPP) The comparison value specified by and the comparison source specified by are compared with each other. According to the result (smaller, equal or larger), any of the three points of the devices specified by turns on. • The source data specified by and are handled as BIN (binary) values.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.1 CMP / Compare 1 Outline Cautions 1) Some restrictions to applicable devices S1:The FX3U and FX3UC PLCs only are applicable. Not indexed (V,Z). S2:The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S3:The FX3U and FX3UC PLCs only are applicable. 2 Instruction List 2) Instructions of pulse operation type are not provided in the FX0, FX0S or FX0N PLC.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.2 8.2 ZCP / Zone Compare ZCP / Zone Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction compares two values (zone) with the comparison source, and outputs the result (upper, equal or lower) to bit devices (3 points). 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.2 ZCP / Zone Compare 1 Outline Function and operation explanation 1. 16-bit operation(ZCP, ZCPP) The lower comparison value specified by and the upper comparison value specified by are compared with the contents of the comparison source specified by . According to the result (smaller, within zone or larger), any of the three points of the devices specified by turns ON.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.2 ZCP / Zone Compare Cautions 1) Some restrictions to applicable devices S1:The FX3U and FX3UC PLCs only are applicable. Not indexed (V,Z). S2:The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S3:The FX3U and FX3UC PLCs only are applicable. 2) Instructions of pulse operation type are not provided in the FX0, FX0S or FX0N PLC.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 MOV / Move Outline 8.3 8.3 MOV / Move FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction transfers (copies) the contents of a device to another device. 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.3 MOV / Move Function and operation explanation 1. 16-bit operation(MOV, MOVP) The contents of the transfer source specified by . are transferred to the transfer destination specified by • While the command input is OFF, the transfer destination specified by • When a constant (K) is specified as the transfer source specified by binary.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.3 MOV / Move 1 The contents of the transfer source specified by . are transferred to the transfer destination specified by • While the command input is OFF, the transfer destination specified by Command input Transfer source data DMOV EN ENO s d [ s +1, s ] does not change.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.3 MOV / Move Program examples 1. When reading the current value of a timer and counter [Structured ladder/FBD] X001 EN s TN0 [ ST ] MOV ENO d MOV(X001,TN0,D20); D20 (Current value of T0) (D20) The operation is the same as a counter. 2.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 SMOV / Shift Move Outline 8.4 8.4 SMOV / Shift Move FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction distributes and composes data in units of digit (4 bits). 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.4 SMOV / Shift Move Function and operation explanation 1. 16-bit operation(SMOV, SMOVP) The contents of the transfer source specified by and transfer destination specified by are converted into 4-digit BCD (0000 to 9999) respectively.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.4 SMOV / Shift Move 1 Outline Program examples The data on three-digit digital switches are composed, and stored as binary data to D2.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.5 8.5 CML / Complement CML / Complement FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction inverts data in units of bit, and then transfers (copies) the inverted data. 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.5 CML / Complement 1 Outline Function and operation explanation 1. 16-bit operation(CML, CMLP) Each bit of a device specified by device specified by . is inverted (from 0 to 1 or from 1 to 0), and then transferred to the • When a constant (K) is specified as 2 , it is automatically converted into binary.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.5 CML / Complement Program examples 1. When receiving an inverted input The sequence program can be written by CML instruction. X000 M0 X000 M0 X001 M1 X001 M1 X002 M2 X002 M2 X003 M3 X003 M3 [Structured ladder/FBD] [ ST ] M8000 RUN K1X000 monitor EN s CML(M8000, K1X000, K1M0); CML ENO d K1M0 2.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 BMOV / Block Move Outline 8.6 8.6 BMOV / Block Move FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction transfers (copies) a specified number of data at one time. 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.6 BMOV / Block Move Function and operation explanation BMOV instruction transfers "n" points of data from the device specified by at one time. to the device specified by • If the device number range is exceeded, data is transferred within the possible range.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.6 BMOV / Block Move 1 Outline Cautions 1) The FX0N, FXU and FX2C PLCs handle file registers as follows. BMOV instruction Read 3 FXU FX2C 3 FXU (V2.30 or earlier) 3 Write 2 3 Instruction List FX0N 2) Instructions of pulse operation type are not provided in the FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.6 BMOV / Block Move Function of transfer between file registers and data registers BMOV instruction has a special function to file registers (D1000 and later). The maximum number of file register differs from one PLC to another. This explanation here uses the FX3U and FX3UC PLCs as examples. For the details of the file registers, refer to the following manual.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.6 BMOV / Block Move D0 D200 D1000 500 points file register D599 Data register D1100 Data register [A] D1499 D7999 8 [B] Applied Instructions (Move and Compare) 14 blocks maximum (7000 points maximum) Read Program/ comment 7 Image memory Applied Instructions (Program Flow) Program memory Data register b) Program examples When X000 is set to ON, the data register area [B] is read.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.7 8.7 FMOV / Fill Move FMOV / Fill Move FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction transfers same data to specified number of devices. 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.7 FMOV / Fill Move 1 Outline Function and operation explanation 1. 16-bit operation(FMOV, FMOVP) The data or contents of a device specified by specified by . are transferred to "n" devices starting from a device 2 • The contents will be same among all of "n" devices.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.7 FMOV / Fill Move Program examples 1. When writing specified data to two or more devices [Structured ladder/FBD] X000 K0 K5 K0 EN s n [ ST ] FMOV ENO d FMOV(X000, K0, K5, D0); D0 Before execution After execution K0 D0 ······ K 3 K 0 K0 D1 ······ K 5 K 0 K0 D2 ······ K 65 K 0 K0 D3 ······ K 7 K 0 K0 D4 ······ K100 K 0 Values before execution are shown as examples.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 XCH / Exchange Outline 8.8 8.8 XCH / Exchange FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction exchanges data between two devices. 1.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.8 XCH / Exchange Function and operation explanation 1. 16-bit operation(XCH, XCHP) Data is exchanged between the device specified by Command input EN XCH ENO d1 d2 Data exchanged 1 Data exchanged 2 Before execution and the device specified by d1 . d2 After execution d1 K10 K36 d1 d2 K10 K36 Exchange d2 2.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 BCD / Conversion to Binary Coded Decimal FX3U(C) FX3G(C) FX3S Outline 8.9 8.9 BCD / Conversion to Binary Coded Decimal FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 This instruction converts binary (BIN) data into binary-coded decimal (BCD) data. Binary data is used in operations in PLCs.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.9 BCD / Conversion to Binary Coded Decimal Function and operation explanation 1. 16-bit operation(BCD, BCDP) This instruction converts the binary (BIN) data specified by transfers the converted BCD data to the device specified by • The data of the device specified by into binary-coded decimal (BCD) data, and . can be converted if it is within the range from K0 to K9999 (BCD).
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.9 BCD / Conversion to Binary Coded Decimal 1 The FXU PLC of V2.30 or earlier does not support the extension function. When executing the instruction with M8023 ON, conversion takes place from binary float to decimal float.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.9 BCD / Conversion to Binary Coded Decimal Program examples 1. When the seven-segment display unit has 1 digit [Structured ladder/FBD] X000 D0 EN s BCD ENO d PLC K1Y000 [ ST ] BCD(X000, D0, K1Y000); 2.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 1 BIN / Conversion to Binary Outline 8.10 8.10 BIN / Conversion to Binary FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 This instruction converts binary-coded decimal (BCD) data into binary (BIN) data.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.10 BIN / Conversion to Binary Function and operation explanation 1. 16-bit operation(BIN, BINP) This instruction converts the binary-coded decimal (BCD) data specified by transfers the converted binary data to the device specified by . • The data of the device specified by can be converted if it is within the range from 0 to 9999 (BCD).
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.10 BIN / Conversion to Binary 1 The FXU PLC of V2.30 or earlier does not support the extension function. When executing the instruction with M8023 ON, conversion takes place from binary-coded decimal float to binary float.
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FXCPU Structured Programming Manual 8 Applied Instructions (Move and Compare) [Basic & Applied Instruction] 8.10 BIN / Conversion to Binary Program examples 1. When the digital switch has 1 digit [Structured ladder/FBD] X000 K1X000 EN s BIN ENO d D0 [ ST ] 6 BIN(X000, K1X000, D0); MOV instruction can be used instead. PLC [Structured ladder/FBD] X000 K1X000 EN s MOV ENO d D0 [ ST ] MOV (X000, K1X000, D0); 2.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 Applied Instructions (Arithmetic and Logical Operation) This chapter introduces the instructions for arithmetic operations and logical operations of numeric data. Function Reference ADDP DADD Subtraction Section 9.2 Multiplication Section 9.3 Division Section 9.4 Increment Section 9.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.1 9.1 ADDP / Addition ADDP / Addition FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes addition by two values to obtain the result (A + B = C) → For the floating point addition instruction [DEADD], refer to Section 18.8. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.1 ADDP / Addition 1 Outline Function and operation explanation 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.1 ADDP / Addition Extension function(FXU and FX2C PLCs) The FXU PLC of V2.30 or earlier does not support the extension function. When executing an instruction with M8023 ON, a binary float operation takes place.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 SUBP / Subtraction Outline 9.2 9.2 SUBP / Subtraction FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 This instruction executes subtraction using two values to obtain the result (A -B = C). → For the floating point subtraction instruction [DESUB], refer to Section 18.9. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.2 SUBP / Subtraction Function and operation explanation 1. 16-bit operation(SUBP) The data specified by is subtracted from the data specified by subtraction result is transferred to .
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.2 SUBP / Subtraction 1 Outline Cautions 1) Instructions of pulse operation type are not provided in the FX0, FX0S or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. 3) The same device number can be specified for both the source and the destination.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.3 9.3 MULP / Multiplication MULP / Multiplication FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes multiplication by two values to obtain the result (A × B = C). → For the floating point multiplication instruction [DEMUL], refer to Section 18.10. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.3 MULP / Multiplication 1 Outline Function and operation explanation 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.3 MULP / Multiplication 2. 32-bit operation(DMUL, DMULP) The data specified by is multiplied by the data specified by multiplication result is transferred to 64-bit (four word devices).
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.3 MULP / Multiplication 1 Outline Program examples 1. 16-bit operation [Structured ladder/FBD] X000 MULP ENO d 2 (D 0) × (D 2) × (D 5, D 4) 8 9 72 D4 Instruction List D0 D2 EN s1 s2 [ ST ] MULP(X000, D0, D2, D4); 3 Configuration of Instruction 2.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.4 9.4 DIVP / Division DIVP / Division FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes division by two values to obtain the result [A ÷ B =C...(remainder)]. → For the floating point division instruction [DEDIV], refer to Section 18.11. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.4 DIVP / Division 1 Outline Function and operation explanation 1. 16-bit operation(DIVP) The contents specified by indicates the dividend, the contents specified by quotient and remainder are transferred to the device specified by .
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.4 DIVP / Division Cautions 1) Some restrictions to applicable devices S1:The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S2:The FX3U and FX3UC PLCs only are applicable. S3:Available only for a 16-bit operation. Not available for a 32-bit operation. 2) Instructions of pulse operation type are not provided in the FX0S, FX0 or FX0N PLC.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 INC / Increment Outline 9.5 9.5 INC / Increment FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction increments the data of a specified device by "1" (+1 addition). 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.5 INC / Increment Cautions 1) Instructions of pulse operation type are not provided in the FX0S, FX0 or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. 2) Note that data is incremented in every operation cycle in a continuous operation type instruction.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 DEC / Decrement Outline 9.6 9.6 DEC / Decrement FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction decrements the data of a specified device by "1" (-1 addition). 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.6 DEC / Decrement Cautions 1) Instructions of pulse operation type are not provided in the FX0S, FX0 or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. 2) In a 16-bit operation, when "+32,767" is incremented by "1", the result is "-32,768". Flags (zero, borrow and carry) are not activated at this time.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 WAND / Logical Word AND Outline 9.7 9.7 WAND / Logical Word AND FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction executes the logical product (AND) operation of two numeric values. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.7 WAND / Logical Word AND Function and operation explanation 1. 16-bit operation(WAND, WANDP) The logical product (AND) operation is executed to the contents specified by the result is transferred to the device specified by .
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 WOR / Logical Word OR Outline 9.8 9.8 WOR / Logical Word OR FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction executes the logical sum (OR) operation of two numeric values. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.8 WOR / Logical Word OR Function and operation explanation 1. 16-bit operation(WOR, WORP) The logical sum (OR) operation is executed to the contents specified by result is transferred to the device specified by .
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 1 WXOR / Logical Exclusive OR Outline 9.9 9.9 WXOR / Logical Exclusive OR FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction executes the exclusive logical sum (XOR) operation of two numeric values. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.9 WXOR / Logical Exclusive OR Function and operation explanation 1. 16-bit operation(WXOR, WXORP) The exclusive logical sum (XOR) operation is executed to the contents specified by bit, and the result is transferred to the device specified by .
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.9 WXOR / Logical Exclusive OR 1 Outline Program examples By combining WXOR and CML instructions, the exclusive logical sum not (XORNOT) operation can be executed.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.10 9.10 NEG / Negation NEG / Negation FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction obtains the 2's complement of a numeric value (by inverting each bit and adding "1"). A sign of a numeric value can be converted by this instruction. → For the floating point sign inversion instruction [DENEG], refer to Section 18.16. 1.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.10 NEG / Negation 1 Outline Function and operation explanation 1. 16-bit operation(NEG, NEGP) Each bit of the device specified by in the original device. Command input NEG ENO d ( d ) +1 → 2 d Complement data 2. 32-bit operation(DNEG, DNEGP) Each bit of the device specified by in the original device.
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FXCPU Structured Programming Manual 9 Applied Instructions (Arithmetic and Logical Operation) [Basic & Applied Instruction] 9.10 NEG / Negation 2. Obtaining the absolute value by SUB (subtraction) instruction Even if NEG instruction (complement operation) is not used, D30 always stores the absolute value of the difference.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 1 Outline 10. Applied Instructions (Rotation and Shift Operation) This chapter introduces the instructions for rotating and shifting bit data and word data in specified directions. Function Reference ROR RORP DROR Rotation Right Section 10.1 3 DRORP ROLP Section 10.2 Rotation Right with Carry Section 10.3 Rotation Left with Carry Section 10.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.1 10.1 ROR / Rotation Right ROR / Rotation Right FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts and rotates the bit information rightward by the specified number of bits without the carry flag. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.1 ROR / Rotation Right 1 Outline Function and operation explanation 1. 16-bit operation (ROR, RORP) "n" bits out of 16 bits of the device specified by Command input ROR ENO d 2 Instruction List Number of bits to be rotated EN n are rotated rightward. Rightward rotation data • The final bit is stored in the carry flag (M8022).
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.1 ROR / Rotation Right Related device → For the carry flag use method, refer to Section 1.3.4. Device M8022 Name Carry Description Turns ON when the bit shifted last from the lowest position is "1". Cautions 1) Some restrictions to applicable devices S1:K4Y , K4M and K4S are valid for a 16-bit operation. K8Y , K8M and K8S are valid for a 32-bit operation.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 1 ROL / Rotation Left Outline 10.2 10.2 ROL / Rotation Left FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 This instruction shifts and rotates the bit information leftward by the specified number of bits without the carry flag. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.2 ROL / Rotation Left Function and operation explanation 1. 16-bit operation (ROL, ROLP) "n" bits out of 16 bits of the device specified by Command input ROL EN ENO n d Number of bits to be rotated are rotated leftward. Leftward rotation data • The final bit is stored in the carry flag (M8022). • In a device with digit specification, K4 (16-bit instruction) is valid.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.2 ROL / Rotation Left 1 → For the carry flag use method, refer to Section 1.3.4. Device Name M8022 Carry Outline Related device Description Turns ON when the bit shifted last from the highest position is "1". 2 Instruction List Cautions 1) Some restrictions to applicable devices S1:K4Y , K4M and K4S are valid for a 16-bit operation.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.3 10.3 RCR / Rotation Right with Carry RCR / Rotation Right with Carry FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts and rotates the bit information rightward by the specified number of bits together with the carry flag. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.3 RCR / Rotation Right with Carry 1 Outline Function and operation explanation 1. 16-bit operation (RCR, RCRP) "n" bits out of 16 bits of the device specified by Command input Number of bits to be rotated 2 RCR ENO d Rightward rotation data Instruction List EN n and 1 bit (carry flag M8022) are rotated rightward.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.3 RCR / Rotation Right with Carry Related device → For the carry flag use method, refer to Section 1.3.4. Device Name M8022 Carry Description Turns ON when the bit shifted last from the lowest position is "1". Cautions 1) Some restrictions to applicable devices S1:K4Y , K4M and K4S are valid for a 16-bit operation. K8Y , K8M and K8S are valid for a 32-bit operation.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 1 RCL / Rotation Left with Carry Outline 10.4 10.4 RCL / Rotation Left with Carry FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 This instruction shifts and rotates the bit information leftward by the specified number of bits together with the carry flag. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.4 RCL / Rotation Left with Carry Function and operation explanation 1. 16-bit operation (RCL, RCLP) "n" bits out of 16 bits of the device specified by Command input Number of bits to be rotated EN n RCL ENO d and 1 bit (carry flag M8022) are rotated leftward.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.4 RCL / Rotation Left with Carry 1 → For the carry flag use method, refer to Section 1.3.4. Device Name M8022 Carry Outline Related device Description Turns ON when the bit shifted last from the highest position is "1". 2 Instruction List Cautions 1) Some restrictions to applicable devices S1:K4Y , K4M and K4S are valid for a 16-bit operation.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.5 10.5 SFTR / Bit Shift Right SFTR / Bit Shift Right FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts bit devices of the specified bit length rightward by the specified number of bits. After shift, the bit device specified by is transferred by "n2" bits from the most significant bit. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.5 SFTR / Bit Shift Right 1 Outline Function and operation explanation 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.6 10.6 SFTL / Bit Shift Left SFTL / Bit Shift Left FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts bit devices of the specified bit length leftward by the specified number of bits. After shift, the bit device specified by is transferred by "n2" bits from the least significant bit. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.6 SFTL / Bit Shift Left 1 Outline Function and operation explanation 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.6 SFTL / Bit Shift Left Program examples(Conditional stepping of 1-bit data) By setting X000 to X007 to ON in turn, Y000 to Y007 are activated in turn. If the order is wrong, activation is disabled.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 1 WSFR / Word Shift Right Outline 10.7 10.7 WSFR / Word Shift Right FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction shifts word devices with "n1" data length rightward by "n2" words. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.7 WSFR / Word Shift Right Function and operation explanation 1. 16-bit operation (WSFR, WSFRP) For "n1" word devices starting from the device specified by shown below) After shift, "n2" words starting from the device specified by the device specified by [ +n1-n2] (3) shown below).
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.7 WSFR / Word Shift Right 1 Outline Program examples 1. Shifting devices with digit specification [Structured ladder/FBD] X000 WSFR ENO d 2 Instruction List K1X000 K4 K2 EN s n1 n2 K1Y000 Specify a same digit for devices with digit specification.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.8 10.8 WSFL / Word Shift Left WSFL / Word Shift Left FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts the word data information leftward by the specified number of words. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.8 WSFL / Word Shift Left 1 Outline Function and operation explanation 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.8 WSFL / Word Shift Left Program examples 1. Shifting devices with digit specification [Structured ladder/FBD] X000 K1X000 K4 K2 EN s n1 n2 WSFL ENO d K1Y000 Specify a same digit for devices with digit specification. Make sure that the number of digits is equivalent.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 1 SFWR / Shift Write [FIFO/FILO Control] FX3U(C) FX3G(C) FX3S Outline 10.9 10.9 SFWR / Shift Write [FIFO/FILO Control] FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 2 Instruction List Outline This instruction writes data for first-in first-out (FIFO) and first-in last-out (FILO) control. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.9 SFWR / Shift Write [FIFO/FILO Control] Function and operation explanation 1. 16-bit operation (SFWR, SFWRP) The contents of the device specified by are written to "n-1" devices from the device specified by +1, and "1" is added to the number of data stored in the device specified by .
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.9 SFWR / Shift Write [FIFO/FILO Control] 1 Outline Program examples 1. Example of first-in first-out control [Structured ladder/FBD] 3 Button for request to put a product into warehouse K4X000 MOVP EN ENO s d D256 K100 The product number is input from X000 to X017, and transferred to D256.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.10 SFRD / Shift Read [FIFO Control] 10.10 SFRD / Shift Read [FIFO Control] FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction reads data for first-in first-out control. 1.
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FXCPU Structured Programming Manual 10 Applied Instructions (Rotation and Shift Operation) [Basic & Applied Instruction] 10.10 SFRD / Shift Read [FIFO Control] 1 Outline Function and operation explanation 1. 16-bit operation (SFRD, SFRDP) The data of the device specified by [ +1] written in turn by SFWR instruction is transferred (read) to the device specified by , and "n-1" words from the device specified by +1 are shifted rightward by 1 word.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11. Applied Instructions (Data Operation) This chapter introduces the instructions for executing complicated processing for applied instructions move, compare, arithmetic operations, rotation and shift operation instructions. Instruction name ZRST ZRSTP DECO DECOP ENCO ENCOP Function Reference Zone Reset Section 11.1 Decode Section 11.2 Encode Section 11.3 Sum of Active Bits Section 11.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11 ZRST / Zone Reset FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This instruction resets devices located in a zone between two specified devices at one time. Use this instruction for restarting operation from the beginning after pause or after resetting control data. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.1 ZRST / Zone Reset Function and operation explanation 1. 16-bit operation (ZRST, ZRSTP) Same type of devices specified by to are reset at one time. When the devices specified by and are bit devices "OFF (reset)" is written to the entire range from the devices specified by Command input EN Before execution ZRST ENO d1 d2 ··· d2 to at one time.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.1 ZRST / Zone Reset 11 FMOV instruction is provided to write a constant (example: K0) at one time. By using this instruction, "0" can be written to word devices (KnY, KnM, KnS, T, C, D and R) at one time. X002 K0 K100 FMOV ENO d D0 12 K0 is written to D0 to D99 at one time.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.1 ZRST / Zone Reset 5) Caution on simultaneous instances of the ZRST instruction and a counter The ZRST instruction resets also the last stage and reset state of T and C coils. Accordingly, if the drive contact of X000 is ON in the following program, the counter executes counting after the ZRST instruction is executed.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11 DECO / Decode FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This instruction converts numeric data into ON bit. A bit number which is set to ON by this instruction indicates a numeric value 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.2 DECO / Decode Function and operation explanation 1. 16-bit operation (DECO, DECOP) One bit among the devices specified by [ specified by .
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.2 DECO / Decode 11 1) Instructions of pulse operation type are not provided in the FX0, FX0S or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. 2) While the command input is OFF, the instruction is not executed. The activated decode output is held in the previous ON/OFF status.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.2 DECO / Decode 2. Turning ON the bit out of word devices according to the contents of bit devices The value expressed by X000 to X002 is decoded to D0 (X000 and X001 are ON, and X002 is OFF in this example).
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11 ENCO / Encode FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This instruction obtains positions in which bits are ON in data. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.3 ENCO / Encode Function and operation explanation 1. 16-bit operation (ENCO, ENCOP) The 2n bit of the data specified by is encoded, and the result value is stored to the device specified by . This instruction converts data into binary data according to a bit position in the ON status.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.3 ENCO / Encode 11 1) Instructions of pulse operation type are not provided in the FX0S, FX0 or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. 2) When two or more bits are ON in the data specified by ON position on the high-order side is encoded.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.4 11.4 SUM / Sum of Active Bits SUM / Sum of Active Bits FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction counts the number of "1" (ON) bits in the data of a specified device. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.4 SUM / Sum of Active Bits 11 1. 16-bit operation (SUM ,SUMP) The number of bits in the ON status in the device specified by specified by . • When all bits are 0 (OFF) in the device specified by EN s SUM data SUM ENO d 12 , the zero flag M8020 turns ON.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.4 SUM / Sum of Active Bits 3.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11 BON / Check Specified Bit Status FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This instruction checks whether a specified bit position in a device is ON or OFF. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.5 BON / Check Specified Bit Status Function and operation explanation 1. 16-bit operation(BON, BONP) The status (ON or OFF) of the bit "n" in the device specified by is output to the device specified by . [When the bit "n" is ON, the device specified by is set to ON. When the bit "n" is OFF, the device specified by is set to OFF.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.5 BON / Check Specified Bit Status 11 Applied Instructions (Data Operation) Program examples When the bit 9 (n=9) in D10 is "1" (ON), M0 is set to "1" (ON).
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.6 11.6 MEAN / Mean MEAN / Mean FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction obtains the mean value of data. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.6 MEAN / Mean 11 1. 16-bit operation (MEAN, MEANP) The mean value of "n" 16-bit data from the device specified by is stored to the device specified by . • The sum is obtained as algebraic sum, and divided by "n". 12 • The remainder is ignored.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.7 11.7 ANS / Timed Annunciator Set ANS / Timed Annunciator Set FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction sets a state relay as an annunciator. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.7 ANS / Timed Annunciator Set 11 Device Name Applied Instructions (Data Operation) Related device Description M8049 Enable annunciator When M8049 is set to ON, M8048 and D8049 are valid. M8048 Annunciator ON When M8049 is ON and one of the state relays S900 to S999 is ON, M8048 turns ON.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.8 11.8 ANR / Annunciator Reset ANR / Annunciator Reset FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction resets an annunciator in the ON status with the smallest number. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 11 Applied Instructions (Data Operation) 11.8 ANR / Annunciator Reset 11 1. Execution in each operation cycle • When ANR instruction is used, annunciators in the ON status are reset in turn in each operation cycle. • When ANRP instruction is used, an annunciator in the ON status is reset only in one operation cycle (only once). Refer to ANS instruction → For a program example, refer to Section 11.7.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.9 11.9 SQR / Square Root SQR / Square Root FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction obtains the square root. The DESQR instruction obtains the square root in floating point operation. → For DESQR instruction, refer to Section 18.15. 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.9 SQR / Square Root 11 1. 16-bit operation (SQR, SQRP) The square root of the data stored in the device specified by specified by ). Command input SQR ENO d s 12 Applied Instructions (High Speed Processing) Root data EN s is calculated, and stored to the device d Resulting data 2.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.10 FLT / Conversion to Floating Point 11.10 FLT / Conversion to Floating Point FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts a binary integer into a binary floating point (real number). 1.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.10 FLT / Conversion to Floating Point 11 1. 16-bit operation (FLT, FLTP) The binary integer data of the device specified by and stored to the device specified by . Command input FLT ENO d ( d s +1, 12 d ) Binary integer Binary floating point (real number) Device that stores the binary floating point data 2.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.10 FLT / Conversion to Floating Point Program examples 1. Arithmetic operations by binary floating point operations The sequence program shown below is constructed as follows: 1) Calculation example (D 0) 16-bit binary (X017 to X010) 2-digit BCD 1) 2) (D 21, D 20) Binary floating point operation 5) (D 22) BIN × K34.
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FXCPU Structured Programming Manual 11 Applied Instructions (Data Operation) [Basic & Applied Instruction] 11.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12. Applied Instructions (High Speed Processing) This chapter introduces interrupt processing type high-speed instructions that execute sequence control using the latest I/O information and utilize the high-speed processing performance of the PLC.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 11 REF / Refresh FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 12.1 12.1 REF / Refresh 12 This instruction immediately outputs the latest input (X) information or the current output (Y) operation result in the middle of a sequence program operation. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.1 REF / Refresh Function and operation explanation 1. 16-bit operation(REF, REFP) 1) When refreshing outputs (Y) "n" points are refreshed from the output of the device specified by REF Command input Head device number Number of points . ("n" must be a multiple of 8.) EN d n ENO * Refer to "Caution" for the head device number and the number of points.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.1 REF / Refresh 11 1) When setting the specified head device number "d", make sure that the least significant digit number is "0" such as "X000, X010, X020, ..." or "Y000, Y010, Y020, ...". 2) Instructions of pulse operation type are not provided in the FX0S, FX0 or FX0N PLC. To execute pulse operation, make the instruction execution condition pulse type. PLC 13 n K8(H8), K16(H10), ..
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.1 REF / Refresh 12.1.1 What should be understood before using the REF instruction 1. Changing the input filter The input filter value is determined by the contents of D8020 (initial value: 10 ms). Use the MOV instruction, etc. to adjust the value in D8020, which represents the input filter value. → For details, refer to "FX Structured Programming Manual (Device & Common)." 2.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 11 REFF / Refresh and Filter Adjust FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 12.2 12.2 REFF / Refresh and Filter Adjust 12 The digital input filter time of the inputs can be changed using this instruction or D8020.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.2 REFF / Refresh and Filter Adjust • When the input turns ON "n × 1 ms" before the instruction is executed, the input image memory is set to ON. When the input turns OFF "n × 1 ms" before the instruction is executed, the input image memory is set to OFF. • When the command input is ON, the REFF instruction is executed in each operation cycle.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.2 REFF / Refresh and Filter Adjust 11 Applied Instructions (Data Operation) Program examples 1. Relationship between the program and the filter time [Structured ladder/FBD] X010 REFF ENO When X010 is ON The image memory is refreshed with an input filter of 1 ms.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.2 REFF / Refresh and Filter Adjust 12.2.1 What should be understood before using REFF instruction Generally, a C-R filter of approximately 10 ms is provided for inputs in PLCs as countermeasures against chattering and noise at the input contacts. A digital filter is provided for some inputs (*1). The digital filter value can be changed within the range from 0 to 60 ms using instructions.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 11 MTR / Input Matrix FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 12.3 12.3 MTR / Input Matrix 12 Applied Instructions (High Speed Processing) Outline This instruction reads matrix input as 8-point input × "n" output (transistor) in the time division method. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.3 MTR / Input Matrix Function and operation explanation 1. 16-bit operation (MTR) An input signal of 8 points × "n" columns is controlled in the time division method using 8 inputs of the device specified by and "n" transistor outputs of the device specified by . Each column is read in turn, and then output to the device specified by .
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.3 MTR / Input Matrix 11 n = Three outputs (Y020, Y021 and Y022) are set to ON in turn repeatedly. Every time an output is set to ON, eight inputs in the 1st, 2nd and 3rd columns are received in turn repeatedly, and stored to M30 to M37, M40 to M47, and M50 to M57 respectively. In this program example, the FX3U series main unit (sink input / sink output) is used.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.3 MTR / Input Matrix 12.3.1 Operation and cautions for MTR instruction 1. Command input 1) Setting the command input to normally ON For the MTR instruction, set the command input to normally ON. M (Normally ON) EN s n X020 K8 MTR ENO d1 d2 Y040 M0 2. Input numbers used in MTR instruction 1) Inputs available in MTR instruction Use inputs X020 and later under normal conditions.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set 11 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 DHSCS Outline 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set Function and operation explanation 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set 11 1. Selection of the counter comparison method 1) Case to select DHSCS instruction - When the output should be given when the counting result becomes equivalent to the comparison value without regard to the scan time of the PLC.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set 4. Some restrictions to applicable devices S1: The FX3U and FX3UC PLCs only are applicable. Not indexed (V, Z). S2: The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S3: The FX3U and FX3UC PLCs only are applicable.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set 11 DHSCS, DHSCR, DHSZ and DHSCT instructions are provided for high speed counters. This section explains common cautions for these instructions. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set 2) Operation Even if the condition for setting the output to ON or OFF is given as the comparison result, the comparison result does not change when an instruction is simply driven. 5.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set 2) FX1S, FX1N, FX1NC, FX2N, FX2NC, FX3S, FX3G and FX3GC PLCs Comparison is executed in the programmed sequence without regard to the instructions.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.4 DHSCS, DHSCS_I / High Speed Counter Set, High Speed Interrupt Counter Set Operation of FX3U and FX3UC PLCs *1. To change the comparison results by the instructions (1) to (3) and (5) in the previous page, change the comparison value "K500" in the instructions (1) to (3) and (5) in the previous page to "K0". Current value 500 250 0 Y000 to Y002 and Y006 do not change.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 11 DHSCR / High Speed Counter Reset FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction compares the value counted by a high speed counter with a specified value at each count, and immediately resets an external output (Y) when both values become equivalent to each other. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.5 DHSCR / High Speed Counter Reset Function and operation explanation 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.5 DHSCR / High Speed Counter Reset 11 1. Selection of the counter comparison method 1) Case to select DHSCR instruction - When the output should be given when the counting result becomes equivalent to the comparison value without regard to the scan time of the PLC.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.5 DHSCR / High Speed Counter Reset S3: The FX3U and FX3UC PLCs only are applicable. S4: The same counter of the device specified by (See the program example.) can be used. 4. Specifying input and output variables When handling 32-bit data in a structured program, a 16-bit device cannot be specified directly as in the case of a simple project. Use a label to handle 32-bit data.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 11 DHSZ / High Speed Counter Zone Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction compares the current value of a high speed counter with two values (one zone), and outputs the comparison result to three bit devices (refresh). 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare Function and operation explanation 1. 32-bit operation (DHSZ) The current value of the high speed counter of the device specified by is compared with two comparison points (comparison value 1 and comparison value 2).
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare 11 1. Selection of the counter comparison method When the DHSCS instruction is used, the maximum frequency and total frequency of the high speed counter are affected.Refer to the counting operation described below, and select according to the contents of control whether to use this instruction or general-purpose comparison instruction.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare For FXU and FX2C PLCs CN251 K10000 INT_TO_DINT _INT CN251 K10000 INT_TO_DINT _INT CN251 K20000 INT_TO_DINT _INT EN _IN _IN EN _IN _IN LT_E ENO Y010 GE_E ENO CN251 INT_TO_DINT _INT K20000 EN _IN _IN EN _IN _IN LE_E ENO Y011 GT_E ENO Y012 REF M8000 Y010 K8 EN d n ENO 2.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.6 DHSZ / High Speed Counter Zone Compare Explanation of operation The outputs Y010 to Y012 are as shown below. Y010 = ON 1,000 13 Y012 = ON Applied Instructions (Handy Instruction) 0 Y011 = ON 1,200 Current value of C235 Program examples 14 X010 RST EN EN ENO d ZRST ENO d1 d2 Y010 Y012 15 Y010 to Y012 are reset.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare Timing chart In the part 1) in the timing chart, Y010 remains OFF if the current value of a high speed counter (C235 in the example below) is "0" when restoring the power.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare 11 1. Set data Operand type Description Data type Head word device number storing the data table (only data register D) ANY32 Number of lines in the table (only K or H) ...
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare 2.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.6 DHSZ / High Speed Counter Zone Compare Cautions 1. Limitation in the number of DHSZ instruction This instruction can be programmed only once in a program. With regard to the DHSCS, DHSCR, DHSZ and DHSCT instructions used for other purposes, a limited number of instructions including the DHSZ instruction can be driven at one time. 2.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.6 DHSZ / High Speed Counter Zone Compare 11 1. Control example 12 Applied Instructions (High Speed Processing) When the special auxiliary relay M8132 for declaring the frequency control mode is specified as in the DHSZ instruction, the special function shown below is provided if DPLSY instruction is combined.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 12 Applied Instructions (High Speed Processing) 12.6 DHSZ / High Speed Counter Zone Compare 11 Applied Instructions (Data Operation) Output pulse characteristics Output pulse Frequency (Hz) 500 12 Applied Instructions (High Speed Processing) 300 200 13 0 0 20 600 700 800 Current value of C251 1) Write prescribed data in advance to data registers constructing the table as shown in this program example.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.7 12.7 SPD / Speed Detection SPD / Speed Detection FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction counts the input pulse for a specified period of time as interrupt input. The function of this instruction varies depending on the version. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.7 SPD / Speed Detection 11 1. 16-bit operation (SPD) Command input SPD ENO d 13 Pulse density data s2 Applied Instructions (Handy Instruction) Device for pulse input Time data EN s1 12 Applied Instructions (High Speed Processing) The input pulse specified by is counted only for the period of "time specified by multiplied by 1 ms.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.7 SPD / Speed Detection 2. 32-bit operation (DSPD) [FX3GC PLCs Ver. 1.40 or later, FX3UC PLCs Ver. 2.20 or later, and FX3S/FX3G/FX3U PLCs] The input pulse specified by is counted only for the period of "time specified by multiplied by 1 ms." The measured value is stored in [ +1, ], the current value is stored in [ +3, +2], and the remaining time is stored in [ +5, +4] (ms).
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.7 SPD / Speed Detection 11 1. Input specifications of the input specified by 1) FX3U PLC Main unit X000 to X005 100kHz*1 100kHz*1 X006 to X007 10kHz 10kHz FX3U-4HSX-ADP 200kHz 14 When receiving pulses within the response frequency range of 50k to 100 kHz, perform the following actions: - Make sure that the wiring length is 5 m or less. Connect a bleeder resistor of 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 12.8 PLSY / Pulse Y Output PLSY / Pulse Y Output FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction generates a pulse signal. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 PLSY / Pulse Y Output 11 1. 16-bit operation (PLSY) A pulse train of frequency specified by specified by .
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 PLSY / Pulse Y Output 2. Monitoring the current number of generated pulses The number of pulses output from Y000 or Y001 is stored in the following special data resistors.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 PLSY / Pulse Y Output 11 When using transistor outputs in the main unit, set the output frequency specified by Do not set the frequency to "0". • FX3U and FX3UC PLCs as follows.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 PLSY / Pulse Y Output 6. Handling of pulse output terminals in the main units The outputs Y000 and Y001 are the high speed response type. When using a pulse output instruction or positioning instruction, adjust the load current of the open collector transistor output.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 PLSY / Pulse Y Output 11 1) Outputs of special high speed output adapters work as differential line drivers. Pulse output destination Operation = Y000 Y004 While Y004 is ON, pulses are output from Y000 in the high speed output adapter. While Y004 is OFF, pulses are output from Y004 in the high speed output adapter.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.8 PLSY / Pulse Y Output Program examples (When outputting pulses without any limitation) When the device specified by is set to K0, pulses are output without any limitation.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 11 PWM / Pulse Width Modulation FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 12.9 12.9 PWM / Pulse Width Modulation 12 Applied Instructions (High Speed Processing) Outline This instruction outputs pulses with a specified period and ON duration. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.9 PWM / Pulse Width Modulation Cautions about writing during RUN Avoid writing during RUN after either of the following operations in a circuit block including the pulse output instruction or positioning instruction. • Changing a program for a circuit block including a corresponding instruction.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.9 PWM / Pulse Width Modulation 11 Applied Instructions (Data Operation) 3. Restrictions to target devices S1: Refer to item 2 of "Cautions". S2: The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S3: The FX3U and FX3UC PLCs only are applicable. 4.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.10 PLSR / Acceleration/Deceleration Setup 12.10 PLSR / Acceleration/Deceleration Setup FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This pulse output instruction has the acceleration/deceleration function. 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.10 PLSR / Acceleration/Deceleration Setup 11 1.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.10 PLSR / Acceleration/Deceleration Setup Related devices 1. Instruction execution complete flag Device Name Description OFF :The command input is OFF, or pulses are being output. (This flag does not turn ON if the pulse Instruction execution output is interrupted in the middle of output.) complete ON :Output of the number of pulses set in is completed. M8029 2.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.10 PLSR / Acceleration/Deceleration Setup 11 :16-bit instruction→10 to 32,767(Hz) 32-bit instruction→10 to 100,000 Hz or less (200,000 Hz or less when using special high speed adapter.
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FXCPU Structured Programming Manual 12 Applied Instructions (High Speed Processing) [Basic & Applied Instruction] 12.10 PLSR / Acceleration/Deceleration Setup • The pulse output is controlled by the dedicated hardware not affected by the sequence program (operation cycle). • If the command input is set to OFF during continuous pulse output, the output from the device specified by turns OFF. 5. Restrictions to target devices S1: Refer to item 4 in "Cautions".
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 11 Applied Instructions (Data Operation) 13. Applied Instructions (Handy Instruction) This chapter introduces the instructions which achieve complicated control in a minimum sequence program. IST Function Reference Section 13.1 Search a Data Stack Section 13.2 Absolute Drum Sequencer Section 13.3 SER SERP DSER DSERP ABSD DABSD 13 INCD Incremental Drum Sequencer Section 13.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 13.1 IST / Initial State IST / Initial State FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This is a command for controlling the initial state and special auxiliary relay automatically in a program by stepladder. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 IST / Initial State 11 Applied Instructions (Data Operation) Function and operation explanation IST Command input ENO d1 d2 Minimum state Maximum state 12 Source Device No. (example) Switch function Device No.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 IST / Initial State Cautions 1. Devices designated in and switches to be used Not all mode selection switches are used. Vacant numbers (not usable in other applications) are designated in switches not in use. 2. Program sequence of IST command and STL command • IST command must be programmed prior to a series of STL circuits such as states S0 to S2. 3.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 IST / Initial State 11 Detail of special auxiliary relay (M) or initial state (S0 to S9) controlled automatically by IST command is as shown in the following equivalent circuit. (Read as reference knowledge.) This equivalent circuit cannot create program. 12 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 IST / Initial State IST command introduction examples (examples of work transfer mechanism) 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 13 Applied Instructions (Handy Instruction) 13.1 IST / Initial State 4. Special auxiliary relays for IST command(M) Auxiliary relays (M) used in IST command are divided into those controlled automatically by the command depending on the circumstances, and others that must be controlled by the program depending on the operation preparation or purpose of control.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 IST / Initial State 11 [Structured ladder/FBD] [ ST ] X004 X002 Y001 Left limit Upper Unclamp limit X020 EN s ENO d1 d2 14 Initial state S20 S27 b) Individual operation Program is not required when individual mode is not available.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.1 IST / Initial State c) Return to home position Program is not required when return home mode is not available. However, before automatic operation, return home end M8043 must be once set.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 11 SER / Search a Data Stack FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This is a command for searching same data and maximum value, minimum value from the table of data. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.2 SER / Search a Data Stack Function and operation explanation 1. 16-bit operation In n pieces of data beginning from the device designated in , same data as the device designated in is searched, and the result is stored in the device designated in .
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.2 SER / Search a Data Stack 11 Applied Instructions (Data Operation) 2. 32-bit operation(DSER, DSERP) In n pieces of data beginning from the device designated in , same data as the device designated in is searched, and the result is stored in the device designated in .
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.2 SER / Search a Data Stack Cautions 1. Comparison of magnitude To be calculated algebraically. (-10 < 2) 2. When minimum value and maximum value are present in a plurality If there are a plurality of minimum value and maximum value in the data, the latter position is stored individually. 3.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 11 ABSD / Absolute Drum Sequencer FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This is a command for creating multiple output patterns corresponding to the present value of the counter. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.3 ABSD / Absolute Drum Sequencer IST command equivalent circuit 1. 16-bit operation(ABSD) This is an example for explaining the ON/OFF control of the output by one revolution of table (0 to 360 degrees).
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.3 ABSD / Absolute Drum Sequencer Cautions 1. Designation of high speed counter DABSD command can designate a high-speed counter in the device designated in . When the high-speed counter is specified, as compared with the counter present value, the output pattern may have a response delay due to scan cycle.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 11 INCD / Incremental Drum Sequencer FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This is a command for creating multiple output patterns by using a pair of counters. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.4 INCD / Incremental Drum Sequencer Function and operation explanation 1. 16-bit operation(INCD) Data table (n lines × 1 point occupied) of n lines from the device designated in is compared with the present value of the counter of the device designated in , and by resetting when coinciding, outputs are sequentially controlled to be ON/OFF.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.4 INCD / Incremental Drum Sequencer 11 3) Output (M0) is reset when the present value of C0 reaches comparative value D300, and the count value of the process counter C1 is incremented by +1, and the present value of the counter C0 is also reset. 4) Next output M1 is turned ON. 6) Similarly compared up to the number of points designated in n(K4).
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.5 13.5 TTMR / Teaching Timer TTMR / Teaching Timer FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This is a command for measuring the ON duration of TTMR command. This is used when adjusting the timer setting time by pushbutton. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.5 TTMR / Teaching Timer 11 1. 16-bit operation(TTMR) The pushing duration of command input (pushbutton) is measured in the unit of seconds, and is multiplied by multiplying factor (10n), and transferred to the device designated in .
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.5 TTMR / Teaching Timer Program examples Write teaching time in ten data registers. Set values should be preliminarily written in D400 to D409.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 11 STMR / Special Timer FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This is the command for creating the off-delay timer, one-shot timer or flicker timer easily. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.6 STMR / Special Timer Function and operation explanation 1. 16-bit operation(STMR) The value designated in m is determined as the set value for the timer of the device designated in is issued to four points from the device designated in . Create the program depending on the application by referring to the following example.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.6 STMR / Special Timer 11 1. Handling of designated timer The timer number designated by this command cannot be used in overlap with other general circuit (OUT command, etc.). If overlapped, the timer does not operate correctly. Four devices are occupied from the one designated in . Be careful not to overlap with the device used in control of the machine.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.7 13.7 ALT / Alternate State ALT / Alternate State FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This is the command for inverting the bit device (ON to OFF, OFF to ON) when the input is turned ON. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.7 ALT / Alternate State 11 Applied Instructions (Data Operation) Function and operation explanation 1. 16-bit operation(ALT, ALTP) Alternate output (one stage) Every time the command input is changed from OFF to ON, the bit device designated in ON to OFF, from OFF to ON.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.7 ALT / Alternate State 2. Flicker operation 1) When the input X006 is turned ON, the contact of timer T2 operates momentarily in every 5 seconds. 2) Every time the contact of T2 is turned ON, the output Y007 is alternately turned ON/OFF.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 11 RAMP / Ramp Variable Value FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This is a command for obtaining data changing n times when designated between the beginning (initial value) and the end (target value). 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.8 RAMP / Ramp Variable Value Function and operation explanation 1. 16-bit operation(RAMP) The starting value and the desired end value are designated in and , and when the command input is turned ON, the value equally divided by the number of times designated in n is added to sequentially in every operation period, and the sum is stored in the device designated in .
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.8 RAMP / Ramp Variable Value 11 In FXU (V1.20 or higher), FX2C, FX2N, FX2NC, FX3U and FX3UC PLCs, by ON/OFF switching of mode flag M8026, the content of +1 is changed as follows. FX0S, FX0, FX0N, FX1S, FX1N, FX3S, FX3G and FX3GC PLCs operate same as when the M8026 is turned ON. FXU (V1.1 or lower) PLC operates same as when the M8026 is turned OFF.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.9 13.9 ROTC / Rotary Table Control ROTC / Rotary Table Control FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This is a command suited for turning the table by a shortcut route depending on the demanding window when putting on or taking out articles on the rotary table. 1.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.9 ROTC / Rotary Table Control 11 1. 16-bit operation(ROTC) As shown below, in order to put on or take out articles on the rotary table divided into m1 sections (=10), depending on the demanding window, the table is controlled and moved by a shortcut route in the condition designated in m2 or and .
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.9 ROTC / Rotary Table Control Operation condition The condition necessary for using this command is as shown in the example below. 1) Rotation detection signal: X→ a) Please install two-phase switch (X000, X001) for detecting normal rotation/reverse rotation of table, and switch X002 for operating when article number 0 comes to window number 0.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.10 SORT / SORT Tabulated Data 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This command reshuffles the data table composed of data (columns) and group data (rows) in the ascending order in column unit on the basis of designated group data (rows). In this command, the group data (rows) is stored in continuous devices.
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.10 SORT / SORT Tabulated Data Function and operation explanation 1. 16-bit operation(SORT) This command reshuffles the data table (reshuffling origin) composed of (m1×m2) points from the device designated in in the ascending order in data columns on the basis of n rows of group data, and stores in the data table (after reshuffling) of (m1×m2) points from the device designated in .
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FXCPU Structured Programming Manual 13 Applied Instructions (Handy Instruction) [Basic & Applied Instruction] 13.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14. Applied Instructions (External FX I/O Device) This chapter introduces the instructions to receive data from and send data to external devices mainly using inputs and outputs in PLCs. Instruction name TKY Function Reference Ten Key Input Section 14.1 Hexadecimal Input Section 14.2 Digital Switch (Thumbwheel Input) Section 14.3 Seven Segment Decoder Section 14.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 11 TKY / Ten Key Input FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This is a command for setting data in the timer or counter by the input of numeric keys 0 to 9. 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.1 TKY / Ten Key Input Function and operation explanation 1. 16-bit operation(TKY) By pressing key from the input for connecting the numeric keys (device designated in ), the entered numerical value is stored in the device designated in , and the key pushing information and key sense output are issued to the device designated in .
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.1 TKY / Ten Key Input 11 By pressing key from the input for connecting the numeric keys (device designated in ), the entered numerical value is stored in the device designated in , and the key pushing information and key sense output are issued to the device designated in . 1) Entered numerical value - If more than 99,999,999, the value overflows from the higher digits.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.1 TKY / Ten Key Input Program examples This is an explanation of an example in which the input X000 is the beginning, and numeric keys 0 to 9 are connected. 1. Program [Structured ladder/FBD] TKY(X030, X000, D0, M10); TKY X030 X000 [ST] EN s ENO d1 d2 D0 M10 2. Wiring diagram This wiring diagram is an example of FX3U PLC (sync input).
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 11 HKY / Hexadecimal Input FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 14.2 14.2 HKY / Hexadecimal Input 12 This is a command for setting the input data of numerical value (0 to 9) or operation condition (function keys A to F), by the input of keys from 0 to F (16 keys).
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.2 HKY / Hexadecimal Input Function and operation explanation 1. 16-bit operation(HKY) The numerical value scanned by the signals of the input for connecting 16 keys (0 to F) (device designated in ) and the row output (device designated in ) and by pressing keys 0 to 9 is stored in the device designated in , and the key sense output is issued to the device designated in .
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.2 HKY / Hexadecimal Input 11 When the extension function is validated by turning ON the M8167, the hexadecimal key pushing data of 0 to F is stored in BIN. Except for the following, this is same as the "function and operation explanation" given above. FXU PLC: V2.30 or lower has no extension function.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.2 HKY / Hexadecimal Input Cautions 1. Limit of number of times of use of command Only one of HKY command and DHKY command can be used in the program. If desired to use plural times, you can program by the index modifier (V, Z) function. 2. When keys are pressed simultaneously When plural keys are pressed, only the first pressed key is valid 3.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 11 DSW / Digital Switch (Thumbwheel Input) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 14.3 14.3 DSW / Digital Switch (Thumbwheel Input) 12 Applied Instructions (High Speed Processing) Outline This is a command for reading in the set value of digital switch.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.3 DSW / Digital Switch (Thumbwheel Input) Function and operation explanation 1. 16-bit operation(DSW) The value of digital switch connected to the device designated in is processed by time division (entered sequentially from the first digit by output signals at 100 ms intervals), and stored in the device designated in .
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.3 DSW / Digital Switch (Thumbwheel Input) 11 This is an example of explaining connection of digital switch starting from the input X010 and starting from the digit designation output Y010. 1. Program [Structured ladder/FBD] X10 K1 EN s n DSW ENO d1 d2 12 [ST] DSW(X000, X10, K1, Y10, D0); Applied Instructions (High Speed Processing) X000 Y10 D0 2.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.3 DSW / Digital Switch (Thumbwheel Input) 4. Method of using by relay output type You can also use the relay output type PLC by providing with "digital switch reading input." When pushbutton (X000) is pressed, the DSW performs a series of operations. In the case of this program, if Y010 to Y013 are relay outputs, there is no problem in relay contact life.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 11 SEGD / Seven Segment Decoder FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Applied Instructions (High Speed Processing) Outline This is a command for lighting up the 7-segement display unit (1 digit) by decoding the data. 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.4 SEGD / Seven Segment Decoder 2.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 11 SEGL / Seven Segment With Latch FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 14.5 14.5 SEGL / Seven Segment With Latch 12 This is a command for controlling the 7-segment display unit with latch of 4 digits and 1 set or 4 digits and 2 sets. 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.5 SEGL / Seven Segment With Latch When using 4 digits and 1 set(n=K0 to K3) → As for selection of "n", refer to section 14.5.2. 1) Data and strobe signal The 4-digit numerical value of is converted from BIN to BCD, and is issued sequentially by time division digit by digit from to +3.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.5 SEGL / Seven Segment With Latch 11 Applied Instructions (Data Operation) 3) Connection example of 7-segment display unit The following diagram show an example of FX3U series basic unit (sync output). As for the actual wiring, see the manual of the PLC.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.5 SEGL / Seven Segment With Latch 14.5.1 Selection procedure of 7-segment display unit You can select the 7-segment display unit depending on the electrical content by referring to the example below. → As for the actual wiring, see the hardware manual of the PLC main body. 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.6 14.6 ARWS / Arrow Switch ARWS / Arrow Switch FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction enters data by arrow switches for digit move and increase and decrease of numerical value of each digit. 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.6 ARWS / Arrow Switch Cautions 1. Setting of parameter n Refer to the parameter setting of SEGL instruction. However, the setting range is 0 to 3. 2. Output format of PLC Use the PLC of transistor output type. 3. Scan time (operation period) and display timing ARWS instruction is executed in synchronism with the scan time (operation cycle) of the PLC.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.7 14.7 ASC / ASCII Code Data Input ASC / ASCII Code Data Input FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts the 1-byte alphanumeric character string into ASCII code. This is used when selecting and displaying plural messages in the external display unit. 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.7 ASC / ASCII Code Data Input 11 When the extension function is validated by turning ON M8161, the 1-byte alphanumeric character string of the device specified by is converted into ASCII code, and sequentially transferred into the device specified by only in the lower 8 bits (1 byte). The extension function is not available when FXU PLC is V2.30 or earlier.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.8 14.8 PR / Print (ASCII Code) PR / Print (ASCII Code) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction performs parallel output of ASCII code data to the output (Y). 1.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.8 PR / Print (ASCII Code) 11 Applied Instructions (Data Operation) 2.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.8 PR / Print (ASCII Code) 2) Timing chart (When M8027=ON) Operation starts when changed from X000=OFF to ON.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 11 FROM / Read From A Special Function Block FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction reads out the content of buffer memory (BFM) of special extension unit/block to the PLC. If a large quantity of buffer memory (BFM) data is read out in batch by using this instruction, a watchdog timer error may occur.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.9 FROM / Read From A Special Function Block 3. Applicable devices Bit Devices Operand type Word Devices System user Digit designation Special System user unit X Y M T C S D .b KnX KnY KnM KnS T C D z z R U \G Others Index Cons Real Character Pointer tant Number String V Z Modifier K H S1 S1 z z S1 S1 z z S1 S1 z z z z z z S1 z z E " " P z S: Refer to "Cautions".
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.9 FROM / Read From A Special Function Block 11 1) Bit device digits to be specified by should be K1 to K4 in the case of 16-bit operation instruction, and K1 to K8 in the case of 32-bit operation. 2) The instruction is provided in the FXU PLC Ver. 2.10 or later. 12 Applied Instructions (High Speed Processing) 3) Instructions of pulse operation type are not provided in the FX0N PLC.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.9 FROM / Read From A Special Function Block 14.9.1 Common terms of FROM/TO instruction (detail) Specification content of operand 1. Unit number n1 of special extension unit/block Unit number is used for specifying which equipment is the object of working for FROM/TO instruction. Setting range: K0 to K7 Unit No. 0 built-in CC-Link/LT Unit No. 1 Unit No.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.9 FROM / Read From A Special Function Block 11 1. Cause of occurrence of watchdog timer error Watchdog timer error may occur in the following cases. 2) When FROM/TO instructions are driven simultaneously. When many FROM/TO instructions are executed, or when multiple buffer memories are transferred, the operation time is extended, and a watchdog timer error may occur.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.10 TO / Write To A Special Function Block 14.10 TO / Write To A Special Function Block FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction writes data from PLC into the buffer memory (BFM) of special extension unit/block. By this instruction, when data is written into multiple buffer memories (BFM) in batch a watchdog timer error may occur.
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.10 TO / Write To A Special Function Block 11 Bit Devices Operand type Word Devices System user Digit designation Special System user unit X Y M T C S D .
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FXCPU Structured Programming Manual 14 Applied Instructions (External FX I/O Device) [Basic & Applied Instruction] 14.10 TO / Write To A Special Function Block Cautions 1) About bit device digit specification to be specified by Specify K1 to K4 in the case of 16-bit operation instruction, or K1 to K8 in the case of 32-bit operation. 2) The instruction is provided in the FXU PLC Ver. 2.10 or later. 3) Instructions of pulse operation type are not provided in the FX0N PLC.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 12 This chapter introduces the instructions for special adapters mainly connected to serial ports. Function Reference Serial Communication Section 15.1 Parallel Run (Octal Mode) Section 15.2 Hexadecimal to ASCII Conversion Section 15.3 ASCII to Hexadecimal Conversion Section 15.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.1 15.1 RS / Serial Communication RS / Serial Communication FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction sends and receives data in no-protocol communication by way of a serial port (only the ch1) in accordance with RS-232C or RS-485 provided in the main unit. 1.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.1 RS / Serial Communication 11 1. 16-bit operation (RS) This instruction sends and receives data in no-protocol communication by way of serial ports in accordance with RS-232C or RS-485 provided in the main unit. → For detailed explanation, refer to the Data Communication Edition manual.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.1 RS / Serial Communication Cautions → For other cautions, refer to the Data Communication Edition manual. 1) RS instruction can be used for ch1 only (cannot be used for ch0*1 and ch2*1). 2) Do not drive two or more RS and/or RS2*2 instructions for the same port at the same time.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 PRUN / Parallel Run (Octal Mode) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction handles the device number specified by and transfers data. and specified by digits as octal number, 1.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.2 PRUN / Parallel Run (Octal Mode) Function and operation explanation 1.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 ASCI / Hexadecimal to ASCII Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 15.3 15.3 ASCI / Hexadecimal to ASCII Conversion 12 This instruction converts HEX code into ASCII code.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.3 ASCI / Hexadecimal to ASCII Conversion 2. <16-bit conversion mode> When M8161=OFF(M8161 is used commonly with RS, HEX, CCD, CRC instructions) Each digit of HEX data stored after the device specified by is converted into ASCII code, and transferred to lower and higher 8 bits (bytes) each in each device after the one specified by .
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 HEX / ASCII to Hexadecimal Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 15.4 15.4 HEX / ASCII to Hexadecimal Conversion 12 This instruction converts ASCII code into HEX code.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.4 HEX / ASCII to Hexadecimal Conversion 2. <16-bit conversion mode> When M8161=OFF(M8161 is used commonly with RS, ASCI, CCD, CRC instructions) ASCII characters stored in higher and lower 8 bits (bytes) in the device specified by are converted into HEX data, and transferred to the device specified by in every four digits.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.4 HEX / ASCII to Hexadecimal Conversion 11 D 102 D 101 In the case of n=K4 D 100 D 200 1 2 1 0 0 0 0 1 0 0 1 A) 1 30H 0 0 0 0 0 1 0 1 0 0 12 0) 0 1 0 0ABCH ...0H ABC1H 6 ..0AH BC12H 7 .
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.4 HEX / ASCII to Hexadecimal Conversion Conversion source data ASCII code HEX conversion D 200 30H 0 D 201 41H A D 202 42H B D 203 43H C D 204 31H 1 D 205 32H 2 D 206 33H 3 D 207 34H 4 D 208 35H 5 Number of characters specified and result of conversion "." is 0. In the case of n=K2 D 102 D 101 D 100 D 200 1 2 3 Not changed 4 0 1 .
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 CCD / Check Code FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction calculates the horizontal parity value or check sum value of error check method used in communication or the like. The error check method also includes cyclic redundancy check (CRC). Use the CRC instruction when determining the CRC value.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.5 CCD / Check Code 2. <16-bit conversion mode> When M8161=OFF(M8161 is used commonly with RS, ASCI, HEX, CRC instructions) Of the data of n points starting from the device specified by , the addition data and the horizontal parity data of higher and lower 8 bits are stored in the device specified by . M8161 is used commonly with RS, ASCI, HEX, CRC instructions.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.6 15.6 VRRD / Volume Read VRRD / Volume Read FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction reads out the value determined by the variable resistor. 1.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.6 VRRD / Volume Read 11 1) The FX1NC, FX2NC and FX3GC PLCs are not provided with variable resistors for reading out by this instruction, and hence do not function even if programmed. 2) In FX3S PLCs, the variable analog potentiometer board can be connected to the option connector.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.6 VRRD / Volume Read Program example Variable resistor values are read out sequentially. Depending on variable resistors VR0 to VR7, the specified values of VRRD instruction are K0 to K7. In the example below, being decorated by index (Z = 0 to 7), K0Z is K0 to K7.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 VRSC / Volume Scale FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 15.7 15.7 VRSC / Volume Scale 12 Applied Instructions (High Speed Processing) Outline This instruction reads out the value determined in the variable resistor graduations. 1.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.7 VRSC / Volume Scale Cautions 1) The FX1NC, FX2NC and FX3GC PLCs are not provided with variable resistors for reading out by this instruction, and hence do not function even if programmed. 2) In FX3S PLCs, the variable analog potentiometer board can be connected to the option connector.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 11 RS2 / Serial Communication 2 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 15.8 15.8 RS2 / Serial Communication 2 12 This instruction transmits and receives data by no-procedure communication via serial port of RS-232C or RS-485 installed in the basic unit.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.8 RS2 / Serial Communication 2 Function and operation explanation 1. 16-bit operation(RS2) This instruction transmits and receives data by no-procedure communication via serial port of RS-232C or RS-485 installed in the basic unit. → As for the detailed explanation, refer to the communication control manual.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.8 RS2 / Serial Communication 2 11 In order to use this instruction, you must install any one of the following products in the basic unit. → As for the system configuration, refer to the hardware manual of the corresponding PLC main unit. → As for the detailed explanation, refer to the communication control manual.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.9 15.9 PID / PID Control Loop PID / PID Control Loop FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes PID control for changing the output values depending on the change value of the input. → As for the detail, refer to the analog control manual. 1.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.9 PID / PID Control Loop 11 Target value(SV) Measured value(PV) Content • • • No. of points occupied 1 point 12 1 point Applied Instructions (High Speed Processing) Setting items Applied Instructions (Data Operation) 2. Setting items To set the target value (SV). PID instruction does not change the contents of setting.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.
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FXCPU Structured Programming Manual 15 Applied Instructions (External Device (optional device)) [Basic & Applied Instruction] 15.9 PID / PID Control Loop 11 5. FX2N PLC supports the upper and lower limit setting functions of the auto-tuning and output value at Ver. 2.00 or later. 6. Some restrictions to applicable devices. Applied Instructions (Data Operation) 4. The instruction is provided in the FXU and FX2C PLCs Ver. 2.70 or later.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 16. Applied Instructions (External Device) This chapter introduces the instructions for control of F2 PLC special extension equipment. Instruction name MNET MNETP ANRD ANRDP ANWR ANWRP RMST Function Reference F-16NP/NT communication Section 16.1 Read from F2-6A Section 16.2 Write to F2-6A Section 16.3 F2-32RM start Section 16.4 Write to F2-32RM Section 16.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 11 MNET / F-16NP/NT communication FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction exchanges ON/OFF signals between the FXU, FX2C PLCs, and F-16NP/NT type interface unit. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 16 Applied Instructions (External Device) 16.1 MNET / F-16NP/NT communication Cautions 1) In the case of FX-16NP/NT, FX-16NP/NT-S3 type interface block, this instruction is not used, and FX224EI is not needed. 2) The instruction is not provided in the FXU and FX2C PLCs Ver. 3.30 or later. This instruction is disused from V3.30 and later.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 11 ANRD / Read from F2-6A FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 16.2 16.2 ANRD / Read from F2-6A 12 Applied Instructions (High Speed Processing) Outline This instruction writes the analog input of F2-6A type analog input and output unit. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 16 Applied Instructions (External Device) 16.2 ANRD / Read from F2-6A Program example This is intended to determine the average of three points of time series data in 100 ms unit in order to suppress fluctuations of the analog input.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 11 ANWR / Write to F2-6A FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 16.3 16.3 ANWR / Write to F2-6A 12 This instruction writes data from the PLC in the F2-6A type analog input and output unit, and issues as analog data. 1.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 16.4 16.4 RMST / F2-32RM start RMST / F2-32RM start FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction gives start signal from the PLC or receives status information, in the F 2 -32RM type programmable cam switch. 1.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 11 RMWR / Write to F2-32RM FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 16.5 16.5 RMWR / Write to F2-32RM 12 This instruction sends output prohibit information from the PLC to the F2-32RM type programmable cam switch. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 16 Applied Instructions (External Device) 16.5 RMWR / Write to F2-32RM Function and operation explanation X000 M500 X040 RMWR EN ENO s1 d s2 • This instruction sends output prohibit information from the PLC to the F2-32RM type programmable cam switch. Y030 Writing of output prohibit information • The content of the device specified by , is determined by the connection position of FX2-24EI type special adapter.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 11 RMRD / Read from F2-32RM FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 16.6 16.6 RMRD / Read from F2-32RM 12 This instruction reads out the ON/OFF state of output of the F2-32RM type programmable cam switch to the PLC. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 16 Applied Instructions (External Device) 16.6 RMRD / Read from F2-32RM Function and operation explanation X000 X040 EN s RMRD ENO d1 d2 • This instruction reads out the ON/OFF state of output of the F2-32RM type programmable cam switch to the PLC. Y030 M660 Reading of ON/OFF information • The content of the device specified by , is determined by the connection position of FX2-24EI type special adapter.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 11 RMMN / F2-32RM monitor FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 16.7 16.7 RMMN / F2-32RM monitor 12 This instruction reads out the rotating speed (rpm) or present angle of the resolver connected to the F2-32RM type programmable cam switch to the PLC. 1.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 16.8 16.8 BLK / Specify F2-30GM BLK / Specify F2-30GM FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction specifies the block number for the F2-30GM type pulse output unit from the PLC. 1.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 16.8 BLK / Specify F2-30GM 11 BLK X000 K0 X040 EN s1 s2 ENO d Y030 • When using the BCD digital switch as , it is converted to BIN value, and the result must be specified. (Constant K is automatically converted into BIN value, and 0 to 31 can be directly entered.) • The content of the device specified by 24EI type special block.
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FXCPU Structured Programming Manual 16 Applied Instructions (External Device) [Basic & Applied Instruction] 16.9 16.9 MCDE / F2-30GM code MCDE / F2-30GM code FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction sends the M code numbers M0 to M77 to the PLC from the F2-30GM type pulse output unit. 1.
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FXCPU Structured Programming Manual 17 Applied Instructions (Data Transfer 2) [Basic & Applied Instruction] 11 Applied Instructions (Data Operation) 17. Applied Instructions (Data Transfer 2) Instruction name ZPUSH ZPUSHP ZPOP ZPOPP Function Reference Batch Store of Index Register Section 17.1 Batch POP of Index Register Section 17.
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FXCPU Structured Programming Manual 17 Applied Instructions (Data Transfer 2) [Basic & Applied Instruction] 17.1 17.1 ZPUSH / Batch Store of Index Register ZPUSH / Batch Store of Index Register FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction temporarily retracts the present values of index registers V0 to V7, Z0 to Z7. To return the retracted present values to the original values, use the ZPOP instruction. → As for ZPOP instruction, refer to section 17.2.
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FXCPU Structured Programming Manual 17 Applied Instructions (Data Transfer 2) [Basic & Applied Instruction] 17.1 ZPUSH / Batch Store of Index Register 11 Applied Instructions (Data Operation) Function and operation explanation 1. 16-bit operation (ZPUSH/ZPUSHP) Command input EN ZPUSH ENO d 12 1) Contents of index registers V0 to V7, Z0 to Z7 are temporarily retracted in and after the device specified by .
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FXCPU Structured Programming Manual 17 Applied Instructions (Data Transfer 2) [Basic & Applied Instruction] 17.1 ZPUSH / Batch Store of Index Register Program example This is a program for retracting the contents of index registers Z0 to Z7, V0 to V7 before execution of subroutine program after D0, when using the index register in the subroutine after pointer P0.
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FXCPU Structured Programming Manual 17 Applied Instructions (Data Transfer 2) [Basic & Applied Instruction] 17.2 ZPOP / Batch POP of Index Register ZPOP / Batch POP of Index Register FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 17.2 11 12 This instruction returns the contents of index registers V0 to V7, Z0 to Z7 once retracted by the ZPUSH instruction to the original state. → As for ZPUSH instruction, refer to section 17.1. 1.
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FXCPU Structured Programming Manual 17 Applied Instructions (Data Transfer 2) [Basic & Applied Instruction] 17.2 ZPOP / Batch POP of Index Register Related instructions Instruction ZPUSH Content This instruction temporarily retracts the present values of index registers V0 to V7, Z0 to Z7. Caution • The instruction is provided in the FX3UC PLC Ver. 2.20 or later. Error It is an operation error in the following case, and error flag M8067 is turned ON, and error code is stored in D8067.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 Applied Instructions (Data Operation) 18. Applied Instructions (Floating Point) Instruction name DESTR DESTRP DEVAL DEVALP DEBCD DEBCDP DEBIN DEBINP DEADD DEADDP DESUB DESUBP DEMUL DEMULP DEDIV DEDIVP DEXP DEXPP DLOGE DLOGEP DLOG10 DESQR DESQRP DENEG DENEGP Floating Point Zone Compare Section 18.2 Floating Point Move Section 18.3 Floating Point to Character String Conversion Section 18.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] Instruction name DRAD DRADP DDEG DDEGP 440 Function Reference Floating Point Degrees to Radians Conversion Section 18.24 Floating Point Radians to Degrees Conversion Section 18.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.1 DECMP / Floating Point Compare DECMP / Floating Point Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction compares two data (binary floating decimal point), and issues the result of greater, smaller, or equal to the bit device (3 points). → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common].
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.1 DECMP / Floating Point Compare Function and operation explanation 1. 32-bit operation (DECMP, DECMPP) The compared value specified by and the comparison source specified by are compared as floating decimal point data, and depending on the result of greater, smaller, or equal, any bit of devices ( , +1, and +2) specified by is turned ON.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DEZCP / Floating Point Zone Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction compares the comparison range of upper and lower two points and the data (binary floating decimal point), and issues the result to the bit device (3 points) depending on the greater, smaller or the band.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.2 DEZCP / Floating Point Zone Compare Function and operation explanation 1. 32-bit operation (DEZCP, DEZCPP) The compared value specified by , and the comparison source specified by are compared as floating decimal point data, and depending on the result of smaller, within range, or greater, any bit of devices ( , +1, and +2) specified by is turned ON.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DEMOV / Floating Point Move FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction transfers binary floating point data. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.3 DEMOV / Floating Point Move Function and operation explanation 1. 32-bit operation (DEMOV/DEMOVP) The content (binary floating decimal point data) of transfer source of device specified by is transferred to the device specified by . Real number (E) can be directly specified in the device specified by .
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DESTR / Floating Point to Character String Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.4 DESTR / Floating Point to Character String Conversion Function and operation explanation 1. 32-bit operation (DESTR/DESTRP) The content (binary floating decimal point data) of the device specified by is converted into character string depending on the content of the device specified by , and stored in or after the device specified by .
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.4 DESTR / Floating Point to Character String Conversion s2 0 s2 +1 8 s2 +2 3 All digits Number of digits below decimal point b15 2 3 5 Sign d +1 31H(1) 20H(space) d +2 32H(2) 2EH(.) d +3 35H(5) 33H(3) 13 0000H d +4 s1 -1.23456 To be stored automatically at the end of character string.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.4 DESTR / Floating Point to Character String Conversion 3. In the case of exponential type b15 Exponential type s2 s2 +1 All digits s2 +2 Number of digits below decimal point s1 +1 ASCII code of digit number (all digits specified value - 1) d +1 ASCII code of ASCII code of digit number decimal point (.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.4 DESTR / Floating Point to Character String Conversion 11 1 12 All digits (12) s2 +1 12 s2 +2 4 1 digit fixed 1 s1 +1 Applied Instructions (High Speed Processing) s2 Applied Instructions (Data Operation) • The converted character string data is stored in the device after as follows.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 18 Applied Instructions (Floating Point) 18.4 DESTR / Floating Point to Character String Conversion Error In the following cases, it is an operation error, and error flag (M8067) is turned ON, and error code is stored in D8067. • When is not within the following range. (Error code: K6706) -126 ≤ < ±2128 0, ±2 • When the type specification specified by is other than 0, 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.4 DESTR / Floating Point to Character String Conversion 11 1) This is a program for converting the content (binary floating decimal point data) of R0, R1 depending on the content specified by R10 to R12 when the X000 is turned ON, and storing after the D0.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.5 18.5 DEVAL / Character String to Floating Point Conversion DEVAL / Character String to Floating Point Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts the character string (ASCII code) into binary floating decimal point data. You can also use the VAL instruction for converting the character string (ASCII code) into BIN data.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.5 DEVAL / Character String to Floating Point Conversion b) In the case of exponential type b15 s b8 b7 b0 20H(space) 2DH(-) s +1 2EH(.) 31H(1) s +2 35H(5) 33H(3) s +3 33H(3) 30H(0) s +4 31H(1) 34H(4) s +5 45H(E) 32H(2) s +6 30H(0) 2DH(-) 00H 32H(2) 1 3 5 0 3 4 1 2 E d +1 d -1.35034E-2 Binary floating decimal point (real number) 0 2 To be cut off.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.5 DEVAL / Character String to Floating Point Conversion 11 → As for the manner of using the zero, borrow, or carry flag, refer to the FX Structured Programming Manual [Device & Common].
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.5 DEVAL / Character String to Floating Point Conversion Program example 1) This is a program for converting the character string stored after R0 when the X000 is turned ON, into binary floating decimal point, and storing in D0, D1. [Structured ladder/FBD] X000 R0 [ST] DEVALP(X000,R0,D0); DEVALP EN ENO d s b15 D0 b8 b7 b0 R0 20H(space) 2DH(-) R1 31H(1) 30H(0) R2 32H(2) 2EH(.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DEBCD / Floating Point to Scientific Notation Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction converts the binary floating decimal point in the device into decimal floating decimal point. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.6 DEBCD / Floating Point to Scientific Notation Conversion Function and operation explanation 1. 32-bit operation (DEBCD, DEBCDP) The binary floating decimal point of the device specified by point, and is transferred to the device specified by .
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DEBIN / Scientific Notation to Floating Point Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction converts the decimal floating decimal point in the device into binary floating decimal point. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.7 DEBIN / Scientific Notation to Floating Point Conversion Function and operation explanation 1. 32-bit operation (DEBIN, DEBINP) The decimal floating decimal point of the device specified by point, and is transferred to the device specified by .
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DEADD / Floating Point Addition FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 Outline Expression in each language DEADD Continuous 32 bits DEADDP 32 bits Structured ladder/FBD EN s1 s2 ST DEADD ENO d DEADDP EN ENO s1 d s2 Pulse 14 DEADD(EN, s1, s2, d); Applied Instructions (External FX I/O Device) Execution form DEADDP(EN, s1, s2, d); 15 Applied Inst
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 18 Applied Instructions (Floating Point) 18.8 DEADD / Floating Point Addition Cautions 1) When the same devices are specified, the same device numbers can be specified in and and . In this case, when the continuous execution type instruction (DEADD) is used, it must be noted that the addition result changes in every operation cycle. 2) The instruction is provided in the FX3G PLC Ver. 1.10 or later.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 11 DESUB / Floating Point Subtraction FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction subtracts two binary floating decimal points. → As for program example of floating decimal point operation, refer to section 11.10. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common].
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.9 DESUB / Floating Point Subtraction Function and operation explanation 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.10 DEMUL / Floating Point Multiplication 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction multiplies two binary floating decimal points. → As for program example of floating decimal point operation, refer to section 11.10. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 13 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.10 DEMUL / Floating Point Multiplication Function and operation explanation 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.11 DEDIV / Floating Point Division 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction divides two binary floating decimal points. → As for program example of floating decimal point operation, refer to section 11.10. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common].
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.11 DEDIV / Floating Point Division Function and operation explanation 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.12 DEXP / Floating Point Exponent 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 18.12 DEXP / Floating Point Exponent 12 This instruction executes exponential operation whose base is "e (2.71828)". → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.12 DEXP / Floating Point Exponent Error In the following cases, it is an operation error, error flag (M8067) is turned ON, and error code is stored in D8067. • When the operation result is out of the following range.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.13 DLOGE / Floating Point Natural Logarithm 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 18.13 DLOGE / Floating Point Natural Logarithm 12 Applied Instructions (High Speed Processing) Outline This instruction executes natural logarithm operation. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.13 DLOGE / Floating Point Natural Logarithm Error In the following cases, it is an operation error, error flag (M8067) is turned ON, and error code is stored in D8067. • When the value specified by is negative. (Error code: K6706) • When the value specified by is 0.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.14 DLOG10 / Floating Point Common Logarithm 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 18.14 DLOG10 / Floating Point Common Logarithm 12 This instruction executes common logarithm operation. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.14 DLOG10 / Floating Point Common Logarithm Error In the following cases, it is an operation error, error flag (M8067) is turned ON, and error code is stored in D8067. • When the value specified by is negative. (Error code: K6706) • When the value specified by is 0.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.15 DESQR / Floating Point Square Root 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 18.15 DESQR / Floating Point Square Root 12 Outline 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 18 Applied Instructions (Floating Point) 18.15 DESQR / Floating Point Square Root Cautions 1) The instruction is provided in the FX3G PLC Ver. 1.10 or later. 2) Some restrictions to applicable devices. S1: The FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable. S2: The FX3U and FX3UC PLCs only are applicable. S3: The FX3S, FX3G, FX3GC, FX3U and FX3UC PLCs only are applicable.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.16 DENEG / Floating Point Negation 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 18.16 DENEG / Floating Point Negation 12 This instruction inverts the sign of binary floating decimal point (real number) data. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.17 INT / Floating Point to Integer Conversion 18.17 INT / Floating Point to Integer Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts the binary floating decimal point into BIN integer in normal data type in the PLC.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.17 INT / Floating Point to Integer Conversion 11 1. 16-bit operation (INT, INTP) The binary floating decimal point of the device specified by transferred to the device specified by . Command input 12 Instruction of reverse converting operation Reverse converting operation of the operation of this instruction is FLT. → As for FLT instruction, refer to 11.10.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.18 DSIN / Floating Point Sine 18.18 DSIN / Floating Point Sine FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction determines the SIN value of angle (RAD). → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.18 DSIN / Floating Point Sine 11 Applied Instructions (Data Operation) Cautions 1) Some restrictions to applicable devices. S1: The FX3U and FX3UC PLCs only are applicable.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.19 DCOS / Floating Point Cosine 18.19 DCOS / Floating Point Cosine FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction determines the COS value of angle (RAD). → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.20 DTAN / Floating Point Tangent 11 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 18.20 DTAN / Floating Point Tangent 12 This instruction determines the TAN value of angle (RAD). → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
PAGE 488
FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.21 DASIN / Floating Point Arc Sine 18.21 DASIN / Floating Point Arc Sine FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes SIN-1 operation. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.21 DASIN / Floating Point Arc Sine 11 In the following cases, it is an operation error, error flag (M8067) is turned ON, and error code is stored in D8067. • When the value specified by is out of the range of -1.0 to 1.0.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.22 DACOS / Floating Point Arc Cosine 18.22 DACOS / Floating Point Arc Cosine FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes COS-1 operation. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.22 DACOS / Floating Point Arc Cosine 11 In the following cases, it is an operation error, error flag (M8067) is turned ON, and error code is stored in D8067. • When the value specified by is out of the range of -1.0 to 1.0.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.23 DATAN / Floating Point Arc Tangent 18.23 DATAN / Floating Point Arc Tangent FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes TAN-1 operation. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.23 DATAN / Floating Point Arc Tangent 11 This is a program for determining TAN-1 of D0, D1 (binary floating decimal point) when the X000 is ON, and sending the angle to Y040 to Y057 in BCD four digits. [Structured ladder/FBD] X000 D10 12 DATAN EN ENO d s D10 DDEG ENO d D20 EN s Calculation of angle (radian) by TAN-1 operation.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.24 DRAD / Floating Point Degrees to Radians Conversion 18.24 DRAD / Floating Point Degrees to Radians Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts the value of angle unit to the radian unit. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.24 DRAD / Floating Point Degrees to Radians Conversion 11 This is a program for converting the angle set in BCD four digits in X020 to X037 when the X000 is ON, and storing in binary floating decimal point in D20, D21. [Structured ladder/FBD] X000 12 BIN ENO d D0 D0 EN s ENO d D10 DRAD EN ENO d s D20 Input of angle to be converted to radian value.
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FXCPU Structured Programming Manual 18 Applied Instructions (Floating Point) [Basic & Applied Instruction] 18.25 DDEG / Floating Point Radians to Degrees Conversion 18.25 DDEG / Floating Point Radians to Degrees Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts the radian unit value into the angle (DEG) unit. → As for handling of floating decimal point, refer to FX Structured Programming Manual [Device & Common]. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 18 Applied Instructions (Floating Point) 18.25 DDEG / Floating Point Radians to Degrees Conversion 11 This is a program for converting the radian value set in binary floating decimal point in D20, D21 to the angle when the X000 is ON, and issuing to the Y040 to Y057 in BCD value. [Structured ladder/FBD] X000 D10 EN s DDEG ENO d 12 Radial value is converted to angle.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19. Applied Instructions (Data Operation 2) This chapter introduces the instructions for executing complicated processing for fundamental applied instructions and for executing special processing. Instruction name Function Reference WSUM WSUMP DWSUM Sum of Word Data Section 19.1 WORD to BYTE Section 19.2 BYTE to WORD Section 19.3 4-bit Linking of Word Data Section 19.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 11 WSUM / Sum of Word Data FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction calculates the total value of continuous 16-bit data or 32-bit data. Please use the CCD when calculating the sum data (total value) in byte (8-bit) unit. → As for the CCD, refer to section 15.5. 1.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.1 WSUM / Sum of Word Data Function and operation explanation 1. 16-bit operation (WSUM/WSUMP) The total value of n points of 16-bit data from the device specified by as 32-bit data.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.1 WSUM / Sum of Word Data 11 This is a program for storing the total value of 16-bit data of D10 to D14 when the X010 is turned ON to [D101, D100].
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.2 19.2 WTOB / WORD to BYTE WTOB / WORD to BYTE FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction separates continuous 16-bit data in byte (8-bit) unit. 1.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.2 WTOB / WORD to BYTE 11 1. 16-bit operation (WTOB/WTOBP) 1) This instruction separates n/2 points of 16-bit data stored after the device specified by and stores into n devices starting from the device specified by as explained below. Head device of the data to be separated. Number of byte data to be separated. WTOB EN ENO s d n Head device for storing the result separated in byte unit.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.2 WTOB / WORD to BYTE Error In the following case, it is an operation error, error flag M8067 is turned ON, and error code is stored in D8067. 1) When devices to +n/2 of separation source exceed the device range of specified devices. When n is an odd number, the devices are required in the number by rounding up.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 11 BTOW / BYTE to WORD FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 19.3 19.3 BTOW / BYTE to WORD 12 Applied Instructions (High Speed Processing) Outline This instruction couples the lower 8 bits (lower byte) of continuous 16-bit data. 1.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.3 BTOW / BYTE to WORD 2) Higher byte (8 bits) of 16-bit data (after ) in the coupling source is ignored. 3) When n is an odd number, as shown below, higher byte (8 bits) of the data coupled in the last place is set to 00H. For example, in the case of n=5, data of lower byte (8 bits) of to +4 is stored in to +2. Higher byte (8 bits) of +2 is 00H.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.3 BTOW / BYTE to WORD 11 This is a program for coupling the data of lower byte (8 bits) of D20 to D25 when the X000 is turned ON, and storing into D10 to D12.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.4 19.4 UNI / 4-bit Linking of Word Data UNI / 4-bit Linking of Word Data FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction couples lower 4 bits of continuous 16-bit data. 1.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.4 UNI / 4-bit Linking of Word Data 11 3) In the case of 1 ≤ n ≤ 3, higher (4×(4-n)) bits of the device specified by are 0. For example, in the case of n=3, lower 4 bits of to ( +2) are stored in b0 to b11 of higher 4 bits of are 0. b4 b3 b0 Lower 4 bits Lower 4 bits Lower 4 bits Ignored.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.5 19.5 DIS / 4-bit Grouping of Word Data DIS / 4-bit Grouping of Word Data FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction separates 16-bit data in 4-bit unit. 1.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.5 DIS / 4-bit Grouping of Word Data 11 1. 16-bit operation (DIS/DISP) 1) This instruction separates 16-bit data of the device specified by device specified by as follows. Device for storing the data to be separated.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.6 19.6 SWAP / Byte Swap SWAP / Byte Swap FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction swaps higher 8 bits and lower 8 bits of word data. 1.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.6 SWAP / Byte Swap 11 Applied Instructions (Data Operation) 2. 32-bit operation (DSWAP, DSWAPP) In the case of 32-bit instruction, too, lower 8 bits and higher 8 bits are swapped individually.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.7 19.7 SORT2 / Sort Tabulated Data 2 SORT2 / Sort Tabulated Data 2 FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction sorts the data table composed of data (rows) and group data (columns) in the ascending order/descending order in row unit on the basis of the specified group data (rows).
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.7 SORT2 / Sort Tabulated Data 2 11 1. 16-bit operation (SORT2) Command input Head device for storing data table. Number of data (rows) Number of group data (columns) SORT2 ENO d Head device for storing the operation result.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.7 SORT2 / Sort Tabulated Data 2 2. 32-bit operation (DSORT2) This instruction sorts the data rows of data table (sorting source) of (m1×m2) points from the device specified by in the ascending order/descending order on the basis of group data of n rows, and stores in data table (after sorting) of (m1×m2) points from the device specified by . → As for operation example, refer to 3.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.
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FXCPU Structured Programming Manual 19 Applied Instructions (Data Operation 2) [Basic & Applied Instruction] 19.7 SORT2 / Sort Tabulated Data 2 Related devices → As for the manner of using the instruction execution complete flag, refer to section 1.3.4. Device Name Content M8029 Instruction execution complete M8165 Descending order Turned ON when data sorting instruction is complete. Sorted in descending order when M8165=ON. Sorted in ascending order when M8165=OFF.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 11 Applied Instructions (Data Operation) 20. Applied Instructions (Positioning Control) 12 This chapter introduces the instructions using the built-in pulse output function of the PLC. DSZR DVIT DDVIT Function Reference Dog Search Zero Return Section 20.1 Interrupt Positioning Section 20.2 Applied Instructions (High Speed Processing) Instruction name Section 20.3 Section 20.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.1 20.1 DSZR / Dog Search Zero Return DSZR / Dog Search Zero Return FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction matches the mechanical position and the current value register in the PLC by zero return. This instruction can perform following operation which is not supported by ZRN.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.1 DSZR / Dog Search Zero Return 11 Second unit Rotating direction signal =Y000 =Y004 =Y001 =Y005 =Y002 =Y006 =Y003 =Y007 2) Output number of rotating direction signal Operation changes as follows depending on polarity of output pulse frequency.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.2 20.2 DVIT / Interrupt Positioning DVIT / Interrupt Positioning FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes one-speed interrupt inching. → As for explanation of the instruction, see the positioning control manual. → As for cautions of use of high speed output special adapter, see the positioning control manual. 1.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.2 DVIT / Interrupt Positioning 11 Avoid writing during RUN after either of the following operations in a circuit block including the pulse output instruction or positioning instruction. • Changing a program for a circuit block including a corresponding instruction. 12 Not available for the FX3S, FX3G or FX3GC PLC. *2. Not available for the FX3S PLC.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.2 DVIT / Interrupt Positioning Cautions 1) Some restrictions to applicable devices. S1: Please specify Y000, Y001, Y002 of transistor output of basic unit, or Y000, Y001, Y002*2, Y003*2 of high speed output special adapter*1. *1. High speed output special adapter can be connected only in FX3U PLC. *2.
PAGE 525
FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 11 DTBL / Batch Data Positioning Mode FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Operation) 20.3 20.3 DTBL / Batch Data Positioning Mode 12 Instructions should be set in a data table beforehand using GX Works2. This instruction specifies one table and operates instructions in that table.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 20 Applied Instructions (Positioning Control) 20.3 DTBL / Batch Data Positioning Mode Cautions 1) The instruction is provided in the FX3UC PLC Ver. 2.20 or later. 2) Some restrictions to applicable devices. S1: Please specify Y000, Y001, Y002*1 of transistor output of basic unit, or Y000, Y001, Y002*3, Y003*3 of high speed output special adapter*2. *1. Y002 is not available in FX3G PLC (14-point and 24-point type) and FX3GC PLC. *2.
PAGE 527
FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 11 DABS / Absolute Current Value Read FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction connects with our company's MR-J4 A, MR-J3 A, MR-J2(S) A, or MR-H A type servo amplifier (with absolute position detecting function), and reads out the absolute position (ABS) data. The data is read out in pulse converted value.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 20 Applied Instructions (Positioning Control) 20.4 DABS / Absolute Current Value Read Cautions 1) The instruction is provided in the FX2N and FX2NC PLCs Ver. 3.00 or later. 2) Since ABS data is read out in pulse converted value, please specify "Motor system" for parameter setting (BFM#3) of FX2N-1PG. (FX2N, FX2NC, FX3U, FX3UC PLCs.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 11 ZRN / Zero Return FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction matches the mechanical position and the current value register in the PLC by zero return. Please use DSZR when DOG search function is necessary. → As for explanation of the instruction, see the positioning control manual.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 20 Applied Instructions (Positioning Control) 20.5 ZRN / Zero Return 11 12 Applied Instructions (High Speed Processing) 13 2) Not applicable to DOG search function, please start the zero return operation from the front side of the near-point signal. (FX1S, FX1N, FX1NC PLCs.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.5 ZRN / Zero Return 6) Specify the speed of return zero point in The setting range is as follows. a) In the case of 16-bit operation .
PAGE 533
FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 11 PLSV / Variable Speed Pulse Output FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction issues a variable speed pulse with the rotating direction. → As for explanation of the instruction, see the positioning control manual. → As for cautions of use of high speed output special adapter, see the positioning control manual. 1.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.6 PLSV / Variable Speed Pulse Output Cautions about writing during RUN Avoid writing during RUN after either of the following operations in a circuit block including the pulse output instruction or positioning instruction. • Changing a program for a circuit block including a corresponding instruction.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.6 PLSV / Variable Speed Pulse Output =Y004 =Y001 =Y005 =Y002 =Y006 =Y003 =Y007 15 4) The output pulse frequency is specified by . The setting range is as follows.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.7 20.7 DRVI / Drive to Increment DRVI / Drive to Increment FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction performs one-speed positioning by relative drive. The moving distance from the present position is specified together with plus or minus sign, and this is also called increment (relative) driving method.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.7 DRVI / Drive to Increment 2) Some restrictions to applicable devices. S1: Please specify Y000, Y001, Y002*1 of transistor output of basic unit, or Y000, Y001, Y002*3, Y003*3 of high speed output special adapter*2. *1. The pulse output destination Y002 is not available in FX3S, FX3G (14-point and 24-point type) and FX3GC PLCs. *2.
PAGE 539
FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 11 DRVA / Drive to Absolute FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 12 This instruction performs one-speed positioning by absolute drive. The moving distance from the origin (0 point) is specified, and this is also called absolute driving method. 1.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.8 DRVA / Drive to Absolute Cautions about writing during RUN Avoid writing during RUN after either of the following operations in a circuit block including the pulse output instruction or positioning instruction. • Changing a program for a circuit block including a corresponding instruction.
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FXCPU Structured Programming Manual 20 Applied Instructions (Positioning Control) [Basic & Applied Instruction] 20.8 DRVA / Drive to Absolute Connection position of high speed output special adapter First unit Rotating direction signal =Y000 =Y004 =Y001 =Y005 =Y002 =Y006 =Y003 =Y007 12 3) Number of output pulses is specified by The setting range is as follows. a) In the case of 16-bit operation .
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21. Applied Instructions (Real Time Clock Control) This chapter introduces operation and comparison instructions for the time data. Instruction name TCMP TCMPP TZCP TZCPP TADD TADDP TSUB TSUBP Function Reference RTC Data Compare Section 21.1 RTC Data Zone Compare Section 21.2 RTC Data Addition Section 21.3 RTC Data Subtraction Section 21.4 Hour to Second Conversion Section 21.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 TCMP / RTC Data Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 The comparison time and the time data are compared, and the bit device is turned ON or OFF depending on the magnitude of difference. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.1 TCMP / RTC Data Compare Function and operation explanation 1. 16-bit operation (TCMP) The time of comparison time (hour, minute, second) , , is compared with the time data (hour, minute, second) of the device specified by , and the device specified by is turned ON or OFF depending on the magnitude of difference.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.1 TCMP / RTC Data Compare 21 [Structured ladder/FBD] [ST] X000 M0 10 hours, 30 minutes, 50 seconds 10 hours, 30 minutes, 50 seconds TCMP ENO d D0 > = (hour) D1 (minute) D2 (second) < and then turned ON (hour) D1 (minute) D2 (second) and then turned ON s1 :Comparison time "hour" is specified. s2 :Comparison time "minute" is specified.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.2 21.2 TZCP / RTC Data Zone Compare TZCP / RTC Data Zone Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline The comparison time of higher and lower points and the time data are compared, and the bit device is turned ON or OFF depending on the magnitude of difference. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.2 TZCP / RTC Data Zone Compare 21 1. 16-bit operation (TZCP, TZCPP) The comparison time (hour, minute, second) of higher and lower points and the time data (hour, minute, second) of the device specified by are compared, and the device specified by is turned ON or OFF depending on the magnitude of difference.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 TADD / RTC Data Addition FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline Two time data are added and stored in the word device. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.3 TADD / RTC Data Addition Function and operation explanation 1. 16-bit operation (TADD) Time data (hour, minute, second) of the device specified by , and time data (hour, minute, second) of the device specified by are added, and the result is stored in the device specified by . Command input EN s1 s2 *1 *1 *1.
PAGE 551
FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 TSUB / RTC Data Subtraction FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline Two time data are subtracted and stored in the word device. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.4 TSUB / RTC Data Subtraction Function and operation explanation 1. 16-bit operation (TSUB, TSUBP) From the time data (hour, minute, second) of the device specified by , the time data (hour, minute, second) of the device specified by is subtracted, and the result is stored in the device specified by . Command input EN s1 s2 *1 *1 *1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 HTOS / Hour to Second Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction converts the "hour, minute, second" unit (time) data into second unit data. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.5 HTOS / Hour to Second Conversion Function and operation explanation 1. 16-bit operation (HTOS/HTOSP) The time data (hour, minute, second) of the device specified by the result is stored in the device specified by .
PAGE 555
FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.5 HTOS / Hour to Second Conversion 21 This is a program for converting the time data being read out from the real-time clock built in the PLC, when the X020 is ON, into the second unit, and storing in D100, D101.
PAGE 556
FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.6 21.6 STOH / Second to Hour Conversion STOH / Second to Hour Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts the time data in second unit into time data in "hour, minute, second" unit. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.6 STOH / Second to Hour Conversion 21 1. 16-bit operation The second unit data of the device specified by result is stored in the device specified by .
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.6 STOH / Second to Hour Conversion Program example This is a program for converting the second unit data stored in D0, D1 when the X020 is turned ON, into the "hour, minute, second" unit, and storing the result in D100, D101, D102.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 TRD / Read RTC data FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline The clock data is read out in the real-time clock built in the PLC. When using FX2NC PLC, optional memory board for Real time clock is required. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.7 TRD / Read RTC data Function and operation explanation 1. 16-bit operation (TRD) The clock data (D8013 to D8019) of the real-time clock built in the PLC is read out into the device specified by in the following format. [ST] [Structured ladder/FBD] Special data register X000 EN TRD ENO d This instruction reads out the real-time clock data of the PLC into seven data registers.
PAGE 561
FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 TWR / Set RTC data FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline The clock data is written into the real-time clock built in the PLC. When using FX2NC PLC, optional memory board for Real time clock is required. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.8 TWR / Set RTC data Function and operation explanation The setting clock data stored in the device specified by the real-time clock built in the PLC.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.8 TWR / Set RTC data 21 Applied Instructions (Real Time Clock Control) Program example 1. Setting example of clock data (time) To set the real-time clock. In the case of 15 hours, 20 minutes, 30 seconds, Tuesday, April 25, 2001.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 21 Applied Instructions (Real Time Clock Control) 21.8 TWR / Set RTC data 4) When connecting with the data access unit of FX-10DU, FX-20DU, FX-25DU types, please set the year in two-digit mode. If set in four-digit mode, the year is not displayed correctly in the present versions of these DU types. When the PLC is in four-digit mode, if the clock is set from FX-10DU, 20DU, 25DU, it must be noted that the mode is changed to two-digit mode.
PAGE 565
FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21 HOUR / Hour Meter FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction adds and measures the ON time duration of input contact in one-hour unit. 1.
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FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.9 HOUR / Hour Meter Function and operation explanation 1. 16-bit operation Command input ON time duration of device specified by d2 : : +1 : : HOUR EN ENO d1 d2 Present value of one-hour unit Device of alarm output destination When the cumulative total of ON time duration of command input exceeds the time of the device specified by , the device specified by is turned ON.
PAGE 567
FXCPU Structured Programming Manual 21 Applied Instructions (Real Time Clock Control) [Basic & Applied Instruction] 21.9 HOUR / Hour Meter 21 1) The instruction is provided in the FX2N and FX2NC PLCs Ver. 3.00 or later. 2) Number of devices occupied The device specified by occupies two devices (16-bit operation) or three devices (32-bit operation). Be careful not to overlap with the devices used in machine control.
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 22. Applied Instructions (External Device) This chapter introduces conversion instructions for gray codes used in absolute type rotary encoders and instructions dedicated to analog blocks. Instruction name Function Reference GRY GRYP DGRY Decimal to Gray Code Conversion Section 22.1 Gray Code to Decimal Conversion Section 22.2 Read form Dedicated Analog Block Section 22.
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 21 GRY / Decimal to Gray Code Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction converts a binary value into a gray code, and transfers it. 1.
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 22.1 GRY / Decimal to Gray Code Conversion Function and operation explanation 1. 16-bit operation (GRY, GRYP) [Structured ladder/FBD] Command input Conversion source data or word device storing conversion source data [ST] GRY EN ENO s d GRY(EN,s,d); Word device storing data after conversion This instruction converts and transfers data from the source (binary) to the destination (gray code).
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 21 GBIN / Gray Code to Decimal Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction converts a gray code into a binary value, and transfers it. 1.
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 22.2 GBIN / Gray Code to Decimal Conversion Function and operation explanation 1.
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 21 RD3A / Read form Dedicated Analog Block FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction reads an analog input value from the analog block FX0N-3A or FX2N-2AD. 1.
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FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 22.3 RD3A / Read form Dedicated Analog Block Function and operation explanation 1.
PAGE 575
FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 21 WR3A / Write to Dedicated Analog Block FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction writes a digital value to the analog block FX0N-3A and FX2N-2DA. 1.
PAGE 576
FXCPU Structured Programming Manual 22 Applied Instructions (External Device) [Basic & Applied Instruction] 22.4 WR3A / Write to Dedicated Analog Block Function and operation explanation 1. 16-bit operation (WR3A, WR3AP) [ST] [Structured ladder/FBD] Command input Special block number Analog output channel Data to be written or word device storing data to be written.
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Applied Instructions (Real Time Clock Control) 23. Applied Instructions (Extension Function) 22 This chapter introduces inverter instructions for the FX2N and FX2NC PLCs.
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FXCPU Structured Programming Manual 23 Applied Instructions (Extension Function) [Basic & Applied Instruction] 23.1 23.1 EXTR_IN / External ROM function EXTR_IN / External ROM function FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction writes the operation control instructions and parameters of the memory for extension function. 1.
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FXCPU Structured Programming Manual 23 Applied Instructions (Extension Function) [Basic & Applied Instruction] 23.1 EXTR_IN / External ROM function 21 → For the details of the instruction, refer to Communication Control Manual. This instruction is for using the optional memory for extension functions. When K11 is set to the device specified by , the control values necessary for inverter operation are written in the PLC.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 23 Applied Instructions (Extension Function) 23.1 EXTR_IN / External ROM function Function and operation explanation2 (Writing inverter parameters) → For the details of the instruction, refer to Communication Control Manual. This instruction is for using the optional memory for extension functions. When K13 is set to device specified by , the inverter parameter is written. 1.
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FXCPU Structured Programming Manual 23 Applied Instructions (Extension Function) [Basic & Applied Instruction] 21 EXTR_OUT / External ROM function FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction is for the short mail transmission of the memory for extension function, inverter operation monitoring instruction, and parameter readout. 1.
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FXCPU Structured Programming Manual 23 Applied Instructions (Extension Function) [Basic & Applied Instruction] 23.2 EXTR_OUT / External ROM function Function and operation explanation1 (Transmitting short mail) → For the details of the instruction, refer to Communication Control Manual. This instruction is for using the optional memory for extension function. When K0 is set to the device specified by , the PLC transmits the short mail. The short mail is transmitted by the PLC.
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FXCPU Structured Programming Manual 23 Applied Instructions (Extension Function) [Basic & Applied Instruction] 23.2 EXTR_OUT / External ROM function 21 → For the details of the instruction, refer to Communication Control Manual. This instruction is for using the optional memory for extension functions. When K10 is set to the device specified by , the inverter operation is monitored. 1. 16-bit operation (EXTR_OUT, EXTRP_OUT) Command input 23 Destination device storing readout value.
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FXCPU Structured Programming Manual 23 Applied Instructions (Extension Function) [Basic & Applied Instruction] 23.2 EXTR_OUT / External ROM function Function and operation explanation3 (Reading inverter parameters) → For the details of the instruction, refer to Communication Control Manual. This instruction is for using the optional memory for extension functions. When K12 is set to the device specified by , the inverter parameter is read out to the PLC. 1.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 21 Applied Instructions (Real Time Clock Control) 24. Applied Instructions (Others) Instruction name COMRD COMRDP RND RNDP CRC CRCP DHCMOV Reference Read Device Comment Data Section 24.1 Random Number Generation Section 24.2 Timing Pulse Generation Section 24.3 Cyclic Redundancy Check Section 24.4 High Speed Counter Move Section 24.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.1 24.1 COMRD / Read Device Comment Data COMRD / Read Device Comment Data FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction reads the comment data for registered devices written to the PLC by programming software such as GX Works2. 1.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.1 COMRD / Read Device Comment Data 21 1. 16-bit operation (COMRD/COMRDP) 1) The comment registered for the device specified by specified by . COMRDP EN ENO d s Device for which comment to be read is registered Head device storing read comment b15 b8 b7 ASCII code of 2nd character ASCII code of 1st character +1 +2 +3 ASCII code of 4th character ASCII code of 3rd character s .
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.1 COMRD / Read Device Comment Data Cautions 1) Specify a device number in the device specified by for which a comment is registered in the PLC. If a comment is not registered for the device specified by , "20H" (space) is stored in the device specified by for the number of characters in the comment (16 half-width characters). 2) The instruction is provided in the FX3UC PLC Ver. 2.20 or later.
PAGE 589
FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 21 RND / Random Number Generation FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction generates random numbers. 1.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.2 RND / Random Number Generation Program examples In the program example shown below, a random number is stored to D100 every time X010 turns ON. When the PLC mode switches from STOP to RUN, the time data converted into seconds and added by the value "(Year + Month) × Day" is written to (D8311 and D8310). [Structured ladder/FBD] M8002 EN [ST] TRD ENO d TRD(M8002,D0); D0 The clock data is read.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 21 DUTY / Timing Pulse Generation FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction generates the timing signal whose one cycle corresponds to the specified number of operation cycles. 1.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.3 DUTY / Timing Pulse Generation Function and operation explanation 1. 16-bit operation (DUTY) 1) The timing clock output of the device specified by scans and OFF duration for "n2" scans.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.3 DUTY / Timing Pulse Generation 21 1) DUTY instruction can be used up to 5 times (points). It is not permitted, however, to use the same timing clock output destination device (device specified by ) for two or more DUTY instructions. 22 2) The instruction is provided in the FX3UC PLC Ver. 2.20 or later. Error An operation error is caused in the following cases.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.4 24.4 CRC / Cyclic Redundancy Check CRC / Cyclic Redundancy Check FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This CRC instruction calculates the CRC (cyclic redundancy check) value which is an error check method used in communication. In addition to CRC value, there are other error check methods such as parity check and sum check.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.4 CRC / Cyclic Redundancy Check 21 1. 16-bit operation Command input *1 *2 EN s n CRC ENO d *3 23 Applied Instructions (Extension Function) *1. Head device storing data for which the CRC value is generated *2. Number of 8-bit (byte) data for which the CRC value is generated or the device storing the number of data *3.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.4 CRC / Cyclic Redundancy Check 2) 8-bit conversion mode [M8161 = ON] In this mode, the operation is executed only for low-order 8 bits (low-order byte) of device specified by . With regard to the operation result, low-order 8 bits (byte) are stored to a device specified by , and high-order 8 bits (byte) are stored to a device specified by +1.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.4 CRC / Cyclic Redundancy Check 21 An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.5 24.5 DHCMOV / High Speed Counter Move DHCMOV / High Speed Counter Move FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction transfers the current value of a specified high speed counter or ring counter. The function of this instruction varies depending on the PLC version. 1.
PAGE 599
FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.5 DHCMOV / High Speed Counter Move "n" set value *1. Operation K0(H0) Does not clear the current value (no processing). K1(H1) Clears the current value to "0". 2.
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FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.5 DHCMOV / High Speed Counter Move 3) If two or more DHCMOV instructions are used in one input interrupt program, only the first instruction (just after the interrupt pointer) is executed when the interrupt is generated. The rest of the interrupt, including additional instructions, is executed according to normal interrupt processing.
PAGE 601
FXCPU Structured Programming Manual 24 Applied Instructions (Others) [Basic & Applied Instruction] 24.5 DHCMOV / High Speed Counter Move 21 Applied Instructions (Real Time Clock Control) Function change depending on the version The function of this instruction changes depending on the version as shown in the table below. Applicable version FX3U Item FX3UC Outline of function Ring counter (D8099 and D8398) can be specified in the device specified by . Ver. 2.20 or later Ver. 2.
PAGE 602
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25. Applied Instructions (Block Data Operation) This chapter introduces the instructions for adding, subtracting and comparing block data. Instruction name Function Reference BK+ BK+P DBK+ Block Data Addition Section 25.1 Block Data Subtraction Section 25.2 Block Data Compare Section 25.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 21 BK+ / Block Data Addition FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction adds binary block data. 1.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.1 BK+ / Block Data Addition 3. Applicable devices Bit Devices Operand type System user Word Devices System user Digit specification Others Special unit X Y M T C S D .b KnX KnY KnM KnS T C D R U \G Index Cons Real Character Pointer tant Number String V Z Modifier K H z z z z z z z z z z z z E P " " z z z z z z z z z Function and operation explanation 1.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.1 BK+ / Block Data Addition Error An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When "n" ("2n" in 32-bit operation) devices starting from the devices specified by exceed the corresponding device range (error code: K6706).
PAGE 607
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 21 BK- / Block Data Subtraction FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction subtracts binary block data. 1.
PAGE 608
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.2 BK- / Block Data Subtraction Function and operation explanation 1.
PAGE 609
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.
PAGE 610
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.2 BK- / Block Data Subtraction Program examples In the program shown below, the constant "8765" is subtracted from the data stored in D100 to D102 when X010 is set to ON, and the operation result is stored in D200 and later.
PAGE 611
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 21 BKCMP=, >, <, < >, <=, >= / Block Data Compare FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline These instructions compare block data in the comparison condition set in each instruction. 1.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] Instruction name BKCMP
P BKCMP<=P BKCMP>=P DBKCMP= DBKCMP> DBKCMP< DBKCMP<> DBKCMP<= DBKCMP>= *1. 610 Operation 16 bits 16 bits 16 bits 16 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 25.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.3 BKCMP=, >, <, < >, <=, >= / Block Data Compare Function and operation explanation 1.
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FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.
PAGE 616
FXCPU Structured Programming Manual [Basic & Applied Instruction] 25 Applied Instructions (Block Data Operation) 25.3 BKCMP=, >, <, < >, <=, >= / Block Data Compare Related device Device Name M8090 Block comparison signal Description Turns ON when all comparison results are "ON (1)" in a block data instruction. DBKCMP=, DBKCMP>, DBKCMP<, DBKCMP<>, DBKCMP<=, DBKCMP>= Cautions 1) The instruction is provided in the FX3UC PLC Ver. 2.20 or later.
PAGE 617
FXCPU Structured Programming Manual 25 Applied Instructions (Block Data Operation) [Basic & Applied Instruction] 25.3 BKCMP=, >, <, < >, <=, >= / Block Data Compare 21 1) In the program shown below, four 16-bit binary data starting from D100 are compared with four 16-bit binary data starting from D200 by BKCMP= instruction when X020 is set to ON, and the comparison result is stored in four points starting from M10.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26. Applied Instructions (Character String Control) This chapter introduces the instructions for controlling character strings such as linking character string data, replacing some characters and extracting character string data. Instruction name Function Reference STR STRP DSTR BIN to Character String Conversion Section 26.1 Character String to BIN Conversion Section 26.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 21 STR / BIN to Character String Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction converts binary data into character strings (ASCII codes). On the other hand, the ESTR instruction converts floating point data into character strings. 1.
PAGE 620
FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.1 STR / BIN to Character String Conversion Function and operation explanation 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 26 Applied Instructions (Character String Control) 26.1 STR / BIN to Character String Conversion 5) Converted character string data is stored in and later as shown below. a) For the sign, "space" (20H) is stored when the 32-bit binary data stored in is positive, and "-" (2DH) is stored when the 32-bit binary data stored in is negative.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.1 STR / BIN to Character String Conversion 21 An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When the number of all digits stored in is outside the following range (error code: K6706).
PAGE 624
FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.2 26.2 VAL / Character String to BIN Conversion VAL / Character String to BIN Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts a character string (ASCII codes) into binary data. On the other hand, EVAL instruction converts a character string (ASCII codes) into floating point data. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.2 VAL / Character String to BIN Conversion 21 1. 16-bit operation (VAL/VALP) Command input VAL ENO d1 d2 Head device storing the number of digits of the binary data acquired by conversion. Head device storing the binary data acquired by conversion.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.2 VAL / Character String to BIN Conversion 3) The device specified by stores the number of all digits. The number of all digits indicates the number of all characters (including the number, sign and decimal point). 4) The device specified by + 1 stores the number of digits of the decimal part.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.2 VAL / Character String to BIN Conversion Description Number of all characters (digits) 2 to 13 Number of characters (digits) of decimal part 0 to 10 and smaller than "number of all digits - 3" 22 -2,147,483,648 to 2,147,483,647 Example) "12345.
PAGE 628
FXCPU Structured Programming Manual [Basic & Applied Instruction] 26 Applied Instructions (Character String Control) 26.2 VAL / Character String to BIN Conversion Error An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When the number of characters of the character string to be converted (device specified by later) is outside the following ranges.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.2 VAL / Character String to BIN Conversion 21 1) In the program below, the character string data stored in D20 to D22 is regarded as an integer value, converted into a binary value, and stored in D0 when X000 is set to ON. [ Structured ladder/FBD] b15 b8 b7 D10 D0 23 b0 2DH(-) 36H(6) 35H(5) 00H D0 -1654 D10 D11 6 2 Applied Instructions (Extension Function) 31H(1) 2EH(.
PAGE 630
FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.3 26.3 $+ / Link Character Strings $+ / Link Character Strings FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction links a character string to another character string. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.3 $+ / Link Character Strings 21 1. 16-bit operation ($+/$+P) Command input b15---b8 b7---- b0 s1 +0 46H(F) 48H(H) + b15---b8 b7---- b0 31H(1) s2 +0 35H(5) 23 Head device storing the linked data (character string) d +1 39H(9) 33H(3) +2 00H 41H(A) "00H" is automatically stored.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.3 $+ / Link Character Strings Program examples In the program example shown below, a character string stored in D10 to D12 (abcde) is linked to the character string "ABCD", and the result is stored to D100 and later when X000 turns ON.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 21 LEN / Character String Length Detection FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction detects the number of characters (bytes) of a specified character string. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.4 LEN / Character String Length Detection Function and operation explanation 1. 16-bit operation (LEN/LENP) The length of a character string stored in the device specified by device specified by . Data starting from the device specified by handled as a character string in units of byte.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.4 LEN / Character String Length Detection 21 In the program example shown below, the length of a character string stored in D0 and later is output in 4-digit BCD to Y040 to Y057 when X000 turns ON. [ST] [Structured ladder/FBD] D10 D3 53H(S) 49H(I) 49H(I) 48H(H) D5 41H(A) 00H D10 10 "MITSUBISHI" (Characters "ABC ..." after "00H" are ignored.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.5 26.5 RIGHT / Extracting Character String Data from the Right RIGHT / Extracting Character String Data from the Right FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction extracts a specified number of characters from the right end of a specified character string.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.5 RIGHT / Extracting Character String Data from the Right 21 1. 16-bit operation (RIGHT/RIGHTP) 1) When the number of extracted characters is odd, "00H" is stored in the high-order byte of a device storing the last character. 2) When the number of extracted characters is even, "0000H" is stored in the device after the last character.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.5 RIGHT / Extracting Character String Data from the Right Cautions 1) When handling character codes other than ASCII codes, note the following contents: a) The number of characters is handled in byte units (8 bits). Accordingly, in the case of character codes in which two bytes express one character such as shift JIS codes, the length of one character is detected as "2".
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 21 LEFT / Extracting Character String Data from the Left FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction extracts a specified number of characters from the left end of a specified character string. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.6 LEFT / Extracting Character String Data from the Left Function and operation explanation 1. 16-bit operation (LEFT/LEFTP) "n" characters are extracted from the left end (that is, from the head) of the character string data stored in the device specified by and later and stored to the device specified by and later.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.6 LEFT / Extracting Character String Data from the Left 21 22 Applied Instructions (External Device) 1) When handling character codes other than ASCII codes, note the following contents: a) The number of characters is handled in byte units (8 bits).
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.7 26.7 MIDR / Random Selection of Character Strings MIDR / Random Selection of Character Strings FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction extracts a specified number of characters from arbitrary positions of a specified character string. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.7 MIDR / Random Selection of Character Strings 21 1. 16-bit operation (MIDR/MIDRP) 1) When the number of extracted characters of the device specified by " the high-order byte of a device storing the last character. +1" is odd, "00H" is stored in 2) When the number of extracted characters of the device specified by " in the device after the last character.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.7 MIDR / Random Selection of Character Strings Cautions 1) When handling character codes other than ASCII codes, note the following contents: a) The number of characters is handled in byte units (8 bits). Accordingly, in the case of character codes in which two bytes express one character such as shift JIS codes, the length of one character is detected as "2".
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 21 MIDW / Random Replacement of Character Strings FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction replaces the characters in arbitrary positions inside designated character string with a specified character string. → For handling of character strings, refer to "FX Structured Programming Manual [Device & Common]." 23 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.8 MIDW / Random Replacement of Character Strings Function and operation explanation 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.8 MIDW / Random Replacement of Character Strings Program examples In the program example shown below, four characters are extracted from the character string data stored in D0 and later, and stored to the third character (from the left end) and later for the character string data stored in D100 and later when X010 turns ON.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 21 INSTR / Character string search FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction searches a specified character string within another character string. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.9 INSTR / Character string search Function and operation explanation 1. 16-bit operation (INSTR/INSTRP) 1) The character string stored in the device specified by and later is searched for within the character string of the device specified by and later.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.9 INSTR / Character string search 21 An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When the search start position "n" exceeds the number of characters stored in (Error code: K6706) 3) When "00H (NULL)" is not located within the corresponding device range starting from the device specified by .
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.10 $MOV / Character String Transfer 26.10 $MOV / Character String Transfer FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction transfers character string data. 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.10 $MOV / Character String Transfer 21 1.
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FXCPU Structured Programming Manual 26 Applied Instructions (Character String Control) [Basic & Applied Instruction] 26.10 $MOV / Character String Transfer Error An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 21 Applied Instructions (Real Time Clock Control) 27. Applied Instructions (Data Operation 3) Instruction name FDEL FDELP FINS FINSP SFR SFRP SFL Deleting Data from Tables Section 27.1 Inserting Data to Tables Section 27.2 Shift Last Data Read [FILO Control] Section 27.3 Bit Shift Right with Carry Section 27.4 Bit Shift Left with Carry Section 27.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.1 27.1 FDEL / Deleting Data from Tables FDEL / Deleting Data from Tables FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction deletes an arbitrary piece of data from a data table. 1.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.1 FDEL / Deleting Data from Tables 21 1. 16-bit operation (FDEL/FDELP) "n"th data is deleted from a data table (stored in the device specified by and later), and the deleted data is stored in the device specified by . "n + 1"th data and later in the data table are shifted forward one by one, and the number of stored data is subtracted by "1".
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.1 FDEL / Deleting Data from Tables Program examples In the program example shown below, the second data is deleted from the data table stored in D100 to D105, and the deleted data is stored in D0 when X010 is set to ON. When the amount of data stored is "0", however, the FDEL instruction is not executed. (The device range used in the data table is D100 to D107.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 21 FINS / Inserting Data to Tables FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction inserts data into an arbitrary position in a data table. 1.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.2 FINS / Inserting Data to Tables Function and operation explanation 1. 16-bit operation (FINS/FINSP) 1) 16-bit data of the device specified by is inserted in "n"th position in a data table (stored in the device specified by and later). "n"th data and later in the data table are shifted backward one by one, and the number of stored data is added by "1".
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.2 FINS / Inserting Data to Tables 21 In the program example shown below, data stored in D100 is inserted into the third position of the data table stored in D0 to D4 when X010 is set to ON. When the amount of data stored exceeds "7", however, the FINS instruction is not executed. (The device range used in the data table is D0 to D7.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.3 27.3 POP / Shift Last Data Read [FILO Control] POP / Shift Last Data Read [FILO Control] FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction reads the last data written by the shift write (SFWR) instruction for the first-in first-out and firstin last-out control 1.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.3 POP / Shift Last Data Read [FILO Control] 21 Applied Instructions (Real Time Clock Control) Function and operation explanation 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 27 Applied Instructions (Data Operation 3) 27.3 POP / Shift Last Data Read [FILO Control] Related instruction Instruction Description SFWR Shift write [for FIFO/FILO control] SFRD Shift read [for FIFO control] Cautions 1) When this instruction is programmed in the continuous operation type, the instruction is executed in every operation cycle. As a result, an expected operation may not be achieved.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.3 POP / Shift Last Data Read [FILO Control] 21 In the program example shown below, among value stored in D20 input first to D101 to D106, the last value input is stored to D10, and "1" is subtracted from the number of stored data (pointer D100) every time X000 turns ON.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.4 27.4 SFR / Bit Shift Right with Carry SFR / Bit Shift Right with Carry FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts 16 bits stored in a word device rightward by "n" bits. 1.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.5 27.5 SFL / Bit Shift Left with Carry SFL / Bit Shift Left with Carry FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction shifts 16 bits stored in a word device leftward by "n" bits. 1.
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FXCPU Structured Programming Manual 27 Applied Instructions (Data Operation 3) [Basic & Applied Instruction] 27.5 SFL / Bit Shift Left with Carry 21 d Applied Instructions (Real Time Clock Control) 3) "0" is set to "n" bits from the least significant bit.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 28. Applied Instructions (Data Comparison) This chapter introduces data comparison instructions which can be handled as contact symbols in programming such as LD, AND and OR. Instruction name Function Reference LD= LD> LD< LD<> LD<= LD>= LDD= Data Comparison Section 28.1 Data Comparison Section 28.2 Data Comparison Section 28.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 21 LD =, >, <, <>, <=, >= / Data Comparison FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 These instructions compare numeric values, and set a contact to ON when the condition agrees so that an operation started. 1.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] Instruction Operation name LDD< 32 bits LDD<> 32 bits LDD<= 32 bits LDD>= *1. 32 bits 28.1 LD =, >, <, <>, <=, >= / Data Comparison Expression in each language Execution form ST*1 Structured ladder/FBD EN s1 s2 Continuous EN s1 s2 Continuous Continuous EN s1 s2 Continuous EN s1 s2 LDD< ENO - LDD<> ENO - LDD<= ENO - LDD>= ENO - Refer to "Cautions". 2.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 28 Applied Instructions (Data Comparison) 28.1 LD =, >, <, <>, <=, >= / Data Comparison 21 or , it is 22 2) When using 32-bit counters (including 32-bit high speed counters) Be sure to execute the 32-bit operation (such as LDD=, LDD> and LDD<) when comparing 32-bit counters. If a 32-bit counter is specified in the 16-bit operation (such as LD=, LD> and LD<), a program error or operation error will occur.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 28.2 28.2 AND=, >, <, < >, <=, >= / Data Comparison AND=, >, <, < >, <=, >= / Data Comparison FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N Outline These instructions compare numeric values, and set a contact to ON when the condition agrees. 1.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 28.2 AND=, >, <, < >, <=, >= / Data Comparison 21 Execution form ANDD<> 32 bits 32 bits Continuous ANDD<> EN ENO s1 s2 - Continuous ANDD<= EN ENO s1 s2 - Continuous ANDD>= EN ENO s1 s2 - 22 23 24 Refer to "Cautions". 2.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 28.2 AND=, >, <, < >, <=, >= / Data Comparison Cautions 1) Negative values When the most significant bit is "1" in the data stored in the device specified by regarded as a negative value in comparison.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 21 OR=, >, <, < >, <=, >= / Data Comparison FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline These instructions compare numeric values, and set a contact to ON when the condition agrees. 1.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 28.3 OR=, >, <, < >, <=, >= / Data Comparison Instruction Operation name Execution form ORD> Continuous 32 bits ORD< 32 bits OR<> 32 bits ORD<= 32 bits Expression in each language ST*1 Structured ladder/FBD EN s1 s2 EN s1 s2 Continuous EN s1 s2 Continuous EN s1 s2 Continuous ORD> ENO - ORD< ENO - OR<> ENO - ORD<= ENO - LD= ORD>= *1.
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FXCPU Structured Programming Manual 28 Applied Instructions (Data Comparison) [Basic & Applied Instruction] 28.3 OR=, >, <, < >, <=, >= / Data Comparison 21 These data comparison instructions are connected to other contacts in parallel. The contents of the device specified by is compared with the contents of the device specified by in binary format, and a contact becomes conductive (ON) or non-conductive (OFF) depending on the comparison result.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29. Applied Instructions (Data Table Operation) Instruction name Function Reference LIMIT LIMITP DLIMIT Limit Control Section 29.1 Dead Band Control Section 29.2 Zone Control Section 29.3 Scaling (Coordinate by Point Data) Section 29.4 Decimal ASCII to BIN Conversion Section 29.5 BIN to Decimal ASCII Conversion Section 29.6 Scaling 2 (Coordinate by X/Y Data) Section 29.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 21 LIMIT / Limit Control FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction provides the upper limit value and lower limit value for an input numeric value, and control the output value using these limit values. 1.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.1 LIMIT / Limit Control 3. Applicable devices Bit Devices Operand type Word Devices System user Digit specification System user Others Special unit X Y M T C S D .
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.1 LIMIT / Limit Control 21 Depending on how the input value (32-bit binary value) of the device specified by compares to the range between the upper and lower limits specified by and , the output value to be stored in the device specified by is controlled. Command input s1 lower limit value 2) In the case of " upper limit value > s1 < input value s2 d s3 ≤ upper limit value "..
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.1 LIMIT / Limit Control Program example 1. Program example 1 In the program example shown below, the BCD data set in X020 to X037 is controlled by the limit values "500" to "5000", and the controlled value is output to D1 when X000 turns ON.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 21 BAND / Dead Band Control FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction provides the upper limit value and lower limit value of the dead band for an input numeric value, and controls the output value using these limit values. 1.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.2 BAND / Dead Band Control Function and operation explanation 1. 16-bit operation (BAND/BANDP) Depending on how the input value (16-bit binary value) of the device specified by and lower limit dead band range between the devices specified by and stored in the device specified by is controlled. The output value is controlled as shown below.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.2 BAND / Dead Band Control 21 1) When the output value overflows, it is handled as follows: a) In the 16-bit operation The output value is a 16-bit binary value with sign.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.2 BAND / Dead Band Control 2. Program example 2 In the program example shown below, the BCD data set in X020 to X057 is controlled by the dead band from "-10000" to "10000", and a controlled value is output to D11 and D10 when X000 turns ON.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 21 ZONE / Zone Control FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Depending on whether the input value is positive or negative, the output value is controlled by the bias value specified. 1.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.3 ZONE / Zone Control Function and operation explanation 1. 16-bit operation (ZONE/ZONEP) The bias value specified by or is added to the input value specified by device specified by . The bias value is added as shown below.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.3 ZONE / Zone Control 21 1) When the output value overflows, it is handled as follows: a) In the 16-bit operation The output value is a 16-bit binary value with sign.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.3 ZONE / Zone Control 2. Program example 2 In the program example below, the BCD data set in X020 to X057 is controlled by the zone from "-10000" to "10000", and the controlled value is output to D11 and D10 when X000 turns ON.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 21 SCL / Scaling (Coordinate by Point Data) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction executes scaling of the input value using a specified data table, and outputs the result. SCL2 is also available with a different data table configuration for scaling. → For SCL2 instruction, refer to Section 29.7. 1.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.4 SCL / Scaling (Coordinate by Point Data) Function and operation explanation 1. 16-bit operation (SCL/SCLP) The input value of the device specified by is processed by scaling for the specified conversion characteristics, and stored to a device number specified by . Conversion for scaling is executed based on the data table stored in a device specified in and later.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.4 SCL / Scaling (Coordinate by Point Data) Error An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When the Xn data is not set in the ascending order in the data table (error code: K6706) The data table is searched from the low-order side of device numbers in the data table in the operation.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.5 DABIN / Decimal ASCII to BIN Conversion DABIN / Decimal ASCII to BIN Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 Applied Instructions (External Device) Outline This instruction converts numeric data expressed in decimal ASCII codes (30H to 39H) into binary data. 1.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.5 DABIN / Decimal ASCII to BIN Conversion Function and operation explanation 1. 16-bit operation (DABIN/DABINP) 1) Data expressed in decimal ASCII codes (30H to 39H) and stored in the device specified by converted into 16-bit binary data, and stored in the device specified by .
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.5 DABIN / Decimal ASCII to BIN Conversion 21 is from "-2,147,483,648" to 3) As "sign data", "20H (space)" is set when the data to be converted is positive, and "2DH (-)" is set when the data to be converted is negative. 5) When an ASCII code for each digit is "20H (space)" or "00H (NULL)", it is handled as "30H".
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.6 BINDA / BIN to Decimal ASCII Conversion 29.6 BINDA / BIN to Decimal ASCII Conversion FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction converts binary data into decimal ASCII codes (30H to 39H). 1.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.6 BINDA / BIN to Decimal ASCII Conversion 21 1. 16-bit operation (BINDA/BINDAP) 1) Each digit of 16-bit binary data stored in the device specified by (30H to 39H), and stored in the device specified by and later. Device storing binary data to be converted into ASCII codes b0 s 16-bit binary data d +0 b0 M8091=OFF:0000H M8091=ON:Does not change.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.6 BINDA / BIN to Decimal ASCII Conversion 2. 32-bit operation (DBINDA/DBINDAP) 1) Each digit of 32-bit binary data stored in the device specified by (30H to 39H), and stored in the device specified by and later.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.6 BINDA / BIN to Decimal ASCII Conversion 21 Instruction Applied Instructions (Real Time Clock Control) Related instructions Description ASCI Converts hexadecimal codes into ASCII codes. Converts ASCII codes into hexadecimal codes. DESTR Converts binary floating point data into a character string data (ASCII code) with the specified number of digits.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.7 SCL2 / Scaling 2 (Coordinate by X/Y Data) 29.7 SCL2 / Scaling 2 (Coordinate by X/Y Data) FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction executes scaling of the input value using a specified data table, and outputs the result. SCL instruction is also available with a different data table configuration for scaling.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.7 SCL2 / Scaling 2 (Coordinate by X/Y Data) 21 1. 16-bit operation (SCL2/SCL2P) Command input *1 *2 Conversion setting data table for scaling Number of coordinate points ("5" in the case shown in the left figure) *1. Input value used in scaling or device storing the input value X coordinate *2.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.7 SCL2 / Scaling 2 (Coordinate by X/Y Data) 3. Setting the conversion table for scaling The conversion table for scaling is set based on the data table stored in a device specified in and later. The data table has the following configuration: → For a setting example, refer to the next page.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.
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FXCPU Structured Programming Manual 29 Applied Instructions (Data Table Operation) [Basic & Applied Instruction] 29.7 SCL2 / Scaling 2 (Coordinate by X/Y Data) Error An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When the Xn data is not set in the ascending order in the data table (error code: K6706) The data table is searched from the low-order side of device numbers in the data table in the operation.
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FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 21 This chapter introduces the instructions for executing inverter communication and MODBUS communication. Function Reference IVCK Inverter Status Check Section 30.1 IVDR Inverter Drive Section 30.2 Inverter Parameter Read Section 30.3 Inverter Parameter Write Section 30.4 Inverter Parameter Block Write Section 30.5 IVBWR IVMC Inverter Multi Command Section 30.
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FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.1 30.1 IVCK / Inverter Status Check IVCK / Inverter Status Check FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction reads the operation status of an inverter to a PLC using the computer link operation function of the inverter. Applicable inverters vary depending on the version.
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FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.1 IVCK / Inverter Status Check 21 → For detailed explanation of the instruction, refer to the Data Communication Edition manual. 1. 16-bit operation (IVCK) Command input Inverter station number Inverter instruction code Channel to be used IVCK ENO d Device storing the read value 23 Refer to the instruction code list.
PAGE 712
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.1 IVCK / Inverter Status Check Cautions → For other cautions, refer to the Data Communication Edition manual. 1) The instruction is provided in the FX3G PLC Ver. 1.10 or later.
PAGE 713
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 21 IVDR / Inverter Drive FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction writes a inverter operation required control value to the PLC using the computer link operation function of the inverter. This instruction corresponds to the EXTR (K11) instruction in the FX2N and FX2NC series PLCs.
PAGE 714
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.2 IVDR / Inverter Drive Function and operation explanation → For detailed explanation of the instruction, refer to the Data Communication Edition manual. 1.
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FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.2 IVDR / Inverter Drive 21 → For other cautions, refer to the Data Communication Edition manual. 1) The instruction is provided in the FX3G PLC Ver. 1.10 or later. - "FLCRT*1, FLDEL*1, FLWR*1, FLRD*1, FLCMD*1 or FLSTRD*1" instruction 3) Two or more inverter communication instructions (IVCK, IVDR, IVRD, IVWR, IVBWR*1 and IVMC) can be driven for the same port at the same time.
PAGE 716
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.3 30.3 IVRD / Inverter Parameter Read IVRD / Inverter Parameter Read FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction reads an inverter parameter to the PLC using the computer link operation function of the inverter. This instruction corresponds to the EXTR (K12) instruction in the FX2N and FX2NC series PLCs.
PAGE 717
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.3 IVRD / Inverter Parameter Read 21 → For detailed explanation of the instruction, refer to the Data Communication Edition manual. 1. 16-bit operation (IVRD) Command input Inverter station number Inverter parameter number IVRD ENO d Device storing the read value 23 2. Related devices → For the instruction execution complete flag use method, refer to Section 1.3.4.
PAGE 718
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.4 30.4 IVWR / Inverter Parameter Write IVWR / Inverter Parameter Write FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction writes a parameter of an inverter using the computer link operation function of the inverter. This instruction corresponds to the EXTR (K13) instruction in the FX2N and FX2NC series PLCs.
PAGE 719
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.4 IVWR / Inverter Parameter Write 21 → For detailed explanation of the instruction, refer to the Data Communication Edition manual. 1.
PAGE 720
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.4 IVWR / Inverter Parameter Write Cases in which a password reset error occurs in an inverter communication instruction, and the actual number of times of reset error in such cases. - When a wrong password is written to Pr297 due to a password input error When the writing instruction is executed once, a password reset error occurs 3 times.
PAGE 721
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 21 IVBWR / Inverter Parameter Block Write FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction writes parameters of an inverter at one time using the computer link operation function of the inverter. → For detailed explanation of the instruction, refer to the Data Communication Edition manual. 1.
PAGE 722
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.5 IVBWR / Inverter Parameter Block Write Function and operation explanation → For detailed explanation of the instruction, refer to the Data Communication Edition manual. 1.
PAGE 723
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 21 IVMC / Inverter Multi Command FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 22 This instruction writes 2 types of settings (operation command and set frequency) to the inverter, and reads 2 types of data (inverter status monitor, output frequency, etc.) from the inverter at the same time.
PAGE 724
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.6 IVMC / Inverter Multi Command Function and operation explanation 1. 16-bit operation This instruction executes multiple commands of an inverter connected to a communication port n whose station number is specified by the device specified in .
PAGE 725
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.6 IVMC / Inverter Multi Command 21 1) The instruction is provided in the FX3U and FX3UC PLCs Ver. 2.70 or later. The instruction is provided in the FX3G PLC Ver. 1.40 or later. - "FLCRT*1, FLDEL*1, FLWR*1, FLRD*1, FLCMD*1 or FLSTRD*1" instruction.
PAGE 726
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.7 30.7 ADPRW / MODBUS Read/Write ADPRW / MODBUS Read/Write FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction allows the MODBUS Master to communicate (read/write data) with its associated Slaves. 1.
PAGE 727
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.7 ADPRW / MODBUS Read/Write 21 Applied Instructions (Real Time Clock Control) Cautions 1) The instruction is provided in the FX3U and FX3UC PLCs Ver. 2.40 or later. The instruction is provided in the FX3G PLC Ver. 1.30 or later.
PAGE 728
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.
PAGE 729
FXCPU Structured Programming Manual 30 Applied Instructions (External Device Communication) [Basic & Applied Instruction] 30.7 ADPRW / MODBUS Read/Write 21 Applied Instructions (Real Time Clock Control) PLC Source Device (head address) 10H MODBUS Address: Write Multiple Registers 0000H to FFFFH Device Count: 1 to 123 Applicable Devices D, R, K, H (D, R can be indexed.
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FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31. Applied Instructions (Data Transfer 3) This chapter introduces the instructions for executing more complicated processing for fundamental applied instructions and for special processing. Instruction name 728 Function Reference RBFM Divided BFM Read Section 31.1 WBFM Divided BFM Write Section 31.
PAGE 731
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31 RBFM / Divided BFM Read FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 This instruction reads data from continuous buffer memories (BFM) in a special function block and unit over several operation cycles by the time division method. This instruction is convenient for reading received data, etc.
PAGE 732
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31.1 RBFM / Divided BFM Read Function and operation explanation 1. 16-bit operation (RBFM) "n1" buffer memory (BFM) units at location No. "m2" in special function block/unit No. "m1" are transferred (read) to the device specified by in the PLC. While transferring, "n1" is divided by "n2" so n1/n2 buffer memories (rounded up when there is a remainder) are transferred per scan time.
PAGE 733
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31.1 RBFM / Divided BFM Read 31 Specification of unit number of special function block and unit and buffer memory → For the connection method of special extension units and blocks, number of connectable units and blocks, and handling of I/O numbers, refer to the manual of the PLC used and special function block and unit.
PAGE 734
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31.1 RBFM / Divided BFM Read Cautions 1) A watchdog timer error may occur when many numbers of points are transferred in one operation cycle. In such a case, take either of the following countermeasures. a) Change the watchdog timer time By overwriting the contents of D8000 (watchdog timer time), the watchdog timer detection time is changed (initial value: K200).
PAGE 735
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31.1 RBFM / Divided BFM Read 31 In the program example shown below, data is read from and written to the buffer memories (BFM) in the unit No. 2 as follows: 1) When X000 is set to ON, data stored in D100 to D179 (80 points) are written to the buffer memories (BFM) #1001 to #1080 in the special function block and unit whose unit number is No. 2 by 16 points in each operation cycle.
PAGE 736
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31.1 RBFM / Divided BFM Read 2) When X001 is set to ON, the buffer memories (BFM) #2001 to #2080 (80 points) in the special function block and unit whose unit number is No. 2 are written to D200 to D279 by 16 points in each operation cycle.
PAGE 737
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31 WBFM / Divided BFM Write FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 This instruction writes data to continuous buffer memories (BFM) in a special function block and unit over several operation cycles by the time division method. This instruction is convenient for writing send data, etc.
PAGE 738
FXCPU Structured Programming Manual 31 Applied Instructions (Data Transfer 3) [Basic & Applied Instruction] 31.2 WBFM / Divided BFM Write Function and operation explanation 1. 16-bit operation (WBFM) "n1" word units from the device specified by in the PLC are transferred (written) to buffer memory (BFM) location No. "m2" in special function unit and block No. "m1". While transferring, "n1" is divided by "n2" so n1/ n2 words (rounded up when there is a remainder) are transferred per scan time.
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Applied Instructions (Data Transfer 3) 32. Applied Instructions (High Speed Processing 2) Applied Instructions (Extension File Register Control) Applied Instructions (FX3U-CF-ADP) Interrupt Function and Pulse Catch Function Relationships between devices and addresses Applied Instruction List 737 32 Reference Applied Instructions (High Speed Processing 2) Section 32.
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FXCPU Structured Programming Manual 32 Applied Instructions (High Speed Processing 2) [Basic & Applied Instruction] 32.1 32.1 DHSCT / High Speed Counter Compare With Data Table DHSCT / High Speed Counter Compare With Data Table FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction compares the current value of a high speed counter with a data table of comparison points, and then sets or resets up to 16 output devices. 1.
PAGE 741
FXCPU Structured Programming Manual 32 Applied Instructions (High Speed Processing 2) [Basic & Applied Instruction] 32.1 DHSCT / High Speed Counter Compare With Data Table 31 1. 32-bit operation (DHSCT) The current value of a high speed counter specified in is compared with the data table shown below which has "m" points stored in the device specified by and later, and the operation output set value (ON or OFF) specified in the data table is output to the devices specified by .
PAGE 742
FXCPU Structured Programming Manual 32 Applied Instructions (High Speed Processing 2) [Basic & Applied Instruction] 32.
PAGE 743
FXCPU Structured Programming Manual 32 Applied Instructions (High Speed Processing 2) [Basic & Applied Instruction] 32.1 DHSCT / High Speed Counter Compare With Data Table 31 Device Name Description M8138 DHSCT Instruction execution complete flag Turns ON when the operation for the final table No. "m-1" is completed. D8138 DHSCT Table counter Stores the comparison point number handled as the comparison target. 32 1) This instruction can be executed only once in a program.
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FXCPU Structured Programming Manual 32 Applied Instructions (High Speed Processing 2) [Basic & Applied Instruction] 32.1 DHSCT / High Speed Counter Compare With Data Table Program example In the program example shown below, the current value of C235 (counting X000) is compared with the comparison data table set in R0 and later, and a specified pattern is output to Y010 to Y013. [ST] [Structured ladder/FBD] C235 is used as an up counter.
PAGE 745
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 31 Instruction name LOADRP SAVER INITR INITRP LOGR RWER RWERP INITER INITERP Reference Load From ER Section 33.1 Save to ER Section 33.2 Initialize R and ER Section 33.3 Logging R and ER Section 33.4 Rewrite to ER Section 33.5 Initialize ER Section 33.
PAGE 746
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.1 33.
PAGE 747
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.1 LOADR / Load From ER 31 Applied Instructions (Data Transfer 3) Function and operation explanation 1.
PAGE 748
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.1 LOADR / Load From ER b) When not connecting to a memory cassette The contents (current values) of extension file registers (ER) stored in PLC's built-in EEPROM having the same numbers with the extension registers specified by to +n-1 are read, and transferred to the extension registers (R) specified by to +n-1 stored in the PLC's built-in RAM.
PAGE 749
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.1 LOADR / Load From ER 31 In the program example shown below, the contents (current values) of 4000 extension file registers ER1 to ER4000 inside the memory cassette are read, and transferred to 4000 extension registers R1 to R4000 inside the built-in RAM.
PAGE 750
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.2 33.2 SAVER / Save to ER SAVER / Save to ER FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction writes the current values of extension registers (R) stored in the PLC's built-in RAM to extension file registers (ER) stored in a memory cassette (flash memory) in units of sector (2048 points). RWER instruction provided in FX3UC PLCs Ver.
PAGE 751
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.2 SAVER / Save to ER 31 1.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.2 SAVER / Save to ER Cautions 1. Cautions on writing data to a memory cassette Memory cassettes adopt flash memory. Note the following contents when writing data to extension file registers in a memory cassettes with the SAVER instruction. 1) It takes about 340 ms to write all points (2048 points).
PAGE 753
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.2 SAVER / Save to ER Note the following when accessing the extension file registers: Error 1) When any device number other than the head device number of a sector of extension file registers is set to . (Error code: K6706) 2) When a memory cassette is not connected.
PAGE 754
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.2 SAVER / Save to ER Program example 1) In the case of FX3UC PLCs Ver. 1.30 or later and FX3U PLCs Ver. 2.20 or later In the program example shown below, the changed contents of extension registers R10 to R19 (sector 0) used for setting data are reflected on the extension file registers (ER) when X000 is set to ON. (128 points are written in one operation cycle.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.
PAGE 756
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.2 SAVER / Save to ER 2) In the case of FX3UC PLCs former than Ver. 1.30 In the program example shown below, the changed contents of the extension registers R10 to R19 (sector 0) used for setting data are reflected on extension file registers (ER) when X000 is set to ON. (128 points are written in one operation cycle.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.
PAGE 758
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] Setting data Setting backup data Setting data Extension registers (R) Extension file registers (ER) Unused extension registers Device number Current value Device number Current value R0 HFFFF ER0 HFFFF R0 K100 R1 HFFFF ER1 HFFFF R1 K105 R10 HFFFF ER10 HFFFF R10 K200 R11 HFFFF ER11 HFFFF R11 K215 R12 HFFFF ER12 HFFFF R12 K400 INITR instruction
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 31 INITR / Initialize R and ER FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 1.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.3 INITR / Initialize R and ER Function and operation explanation 1. 16-bit operation (INITR/INITRP) "n" sectors of extension registers in the PLC's built-in RAM starting from the one specified by and "n" sectors of extension file registers in a memory cassette (flash memory) having the same device numbers are initialized (initial value "HFFFF" is written.).
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.3 INITR / Initialize R and ER 31 Applied Instructions (Data Transfer 3) Cautions 1. Initializing two or more sectors When a memory cassette is attached, 18 ms is required to initialize one sector. (When a memory cassette is not attached, only 1 ms is required to initialize one sector.) When initializing two or more sectors, take either measures shown below.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.3 INITR / Initialize R and ER Error An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When any device number other than the head device number of a sector of extension file registers is set to . (Error code: K6706) 2) When a device number to be initialized exceeds "32767".
PAGE 763
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 31 LOGR / Logging R and ER FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 This instruction logs specified devices, and stores the logged data to extension registers (R) and extension file registers (ER) in a memory cassette. 1.
PAGE 764
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.4 LOGR / Logging R and ER Function and operation explanation 1. 16-bit operation (LOGR/LOGRP) While the instruction is driven, "m" devices starting from the device specified by are logged until "n" sectors of extension registers (R) starting from the device specified by and extension file registers (ER) in a memory cassette are filled.
PAGE 765
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.4 LOGR / Logging R and ER 31 Applied Instructions (Data Transfer 3) Cautions 1. About LOGR instruction LOGR instruction executes logging in each operation in the continuous operation type. When logging should be executed only once by one input, use the pulse operation type. 32 Flash memory is adopted in a memory cassette.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.4 LOGR / Logging R and ER Program example In the program example shown below, D1 and D2 are logged to the area from R2048 to R6143 every time X001 turns ON.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 31 RWER / Rewrite to ER FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 This instruction writes the current values of an arbitrary number of extension registers (R) in the PLC's built-in RAM to extension file registers (ER) in a memory cassette (flash memory or EEPROM) or to the extension file registers (ER) in the PLC's built-in EEPROM.
PAGE 768
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.5 RWER / Rewrite to ER Function and operation explanation 1.
PAGE 769
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.5 RWER / Rewrite to ER 31 1. Cautions on writing data to the memory cassette (flash memory) for the FX3U and FX3UC PLCs Memory cassettes adopt flash memory. Note the following contents when writing data to extension file registers in a memory cassette with the RWER instruction. Writing command input M100 D8000 D200 EN s n *1.
PAGE 770
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.5 RWER / Rewrite to ER 2. Cautions on writing data to the memory cassette (EEPROM) for the FX3G PLCs Memory cassettes adopt EEPROM. Note the following contents when writing data to extension file registers in a memory cassette with the RWER instruction. • Do not turn OFF the power while this instruction is being executed.
PAGE 771
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.5 RWER / Rewrite to ER 31 In the program example shown below, the changed contents of extension registers R10 to R19 (sector 0) used for setting data are reflected on extension file registers (ER) when X000 turns ON.
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FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.6 33.6 INITER / Initialize ER INITER / Initialize ER FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Outline This instruction initializes extension file registers (ER) to "HFFFF" () in a memory cassette (flash memory) before executing the SAVER instruction. Because INITER instruction is not provided in the FX3UC PLC earlier than Ver. 1.
PAGE 773
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.6 INITER / Initialize ER 31 1. 16-bit operation (INITER/INITERP) "n" sectors of extension file registers (ER) in a memory cassette (flash memory) with the same device number as the device specified by are initialized (initial value "HFFFF" () is writen.). Initialization is executed in sectors.
PAGE 774
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.6 INITER / Initialize ER Cautions 1. About 25 ms is required to initialize one sector. When initializing two or more sectors, take either measure shown below. 1) Set a large value to the watchdog timer D8000 using the following program.
PAGE 775
FXCPU Structured Programming Manual 33 Applied Instructions (Extension File Register Control) [Basic & Applied Instruction] 33.6 INITER / Initialize ER 31 An operation error is caused in the following cases. The error flag M8067 turns ON, and the error code is stored in D8067. 1) When any device number other than the head device number of a sector of extension file registers (ER) is set to . (Error code: K6706) 3) When the protect switch of the memory cassette is set to ON.
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FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34. Applied Instructions (FX3U-CF-ADP) Instruction name FLCRT 774 Function Reference File create • check Section 34.1 FLDEL File delete • CF card format Section 34.2 FLWR Data write Section 34.3 FLRD Data read Section 34.4 FLCMD FX3U-CF-ADP command Section 34.5 FLSTRD FX3U-CF-ADP status read Section 34.
PAGE 777
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 31 FLCRT / File create • check FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 The FLCRT instruction creates a file inside the CompactFlashTM card mounted in the FX3U-CF-ADP. When executed after creation of a new file, the FLCRT instruction checks the association with the file ID, and evaluates it. → As for explanation of the instruction, see the FX3U-CF-ADP User's Manual.
PAGE 778
FXCPU Structured Programming Manual [Basic & Applied Instruction] 34 Applied Instructions (FX3U-CF-ADP) 34.1 FLCRT / File create • check Function and operation explanation 1. 16-bit operation (FLCRT) Command input File ID File name File creation parameter Used channel number EN s1 s2 s3 n FLCRT ENO 1) When the file ID is "K0" When is "K0", the FLCRT instruction creates a FIFO file. When the PLC creates two or more files for FIFO file, and executes FIFO (first in, first out) in units of files.
PAGE 779
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.1 FLCRT / File create • check 31 Details of the setting data in the FLCRT instruction are as shown below. Setting items Description Data Type File ID This ID number is associated with the file name. The FLCRT instruction creates a file, and associates the file name with the file ID at the same time. The user should use the file ID for specifying a file after that.
PAGE 780
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.1 FLCRT / File create • check Cautions 1) When the file ID is "K0" a) The CF-ADP can create up to 1000 files (within the CompactFlashTM card capacity). b) The file name is set to "FILE0000.CSV" to "FILE0999.CSV". 2) When the file ID is "K1" to "K63" a) The user can create up to 63 files (within the CompactFlashTM card capacity).
PAGE 781
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 31 FLDEL / File delete • CF card format FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 The FLDEL instruction deletes files stored in the CompactFlash TM card, or formats the CompactFlashTM card. → As for explanation of the instruction, see the FX3U-CF-ADP User's Manual. 1.
PAGE 782
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.2 FLDEL / File delete • CF card format Function and operation explanation 1. 16-bit operation (FLDEL) Command input File ID File delete method Used channel number EN s1 s2 n FLDEL ENO The FLDEL instruction deletes files stored in the CompactFlashTM card, or formats the CompactFlashTM card in the following method. 1) Specify file deletion or file formatting using .
PAGE 783
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 31 FLWR / Data write FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 The FLWR instruction writes data to the CompactFlashTM card or to the buffer inside the FX3U-CF-ADP. → As for explanation of the instruction, see the FX3U-CF-ADP User's Manual. 1.
PAGE 784
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.3 FLWR / Data write Function and operation explanation 1.
PAGE 785
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.3 FLWR / Data write 31 Details of the setting data in the FLWR instruction are as shown below. Setting items Description File ID K0 to K63 Data Type ANY16 Head of devices which store data to be written. Data write parameter +2 Specify the data column position in the writing destination.
PAGE 786
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.3 FLWR / Data write Cautions 1) The FLWR instruction is completed abnormally if a CompactFlashTM card is not mounted. 2) The user should pay close attention to the number of times data is written when the writing destination is set to the CompactFlashTM card because data is written every time the FLWR instruction is executed.
PAGE 787
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 31 FLRD / Data read FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) Applied Instructions (Data Transfer 3) 34.4 34.4 FLRD / Data read 32 The FLRD instruction reads data from the CompactFlashTM card. → As for explanation of the instruction, see the FX3U-CF-ADP User's Manual. 1.
PAGE 788
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.4 FLRD / Data read Detailed explanation of setting data Details of the setting data in the FLRD instruction are as shown below.
PAGE 789
FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.5 FLCMD / FX3U-CF-ADP command FLCMD / FX3U-CF-ADP command FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 The FLCMD instruction gives instruction for operation to the FX3U-CF-ADP. → As for explanation of the instruction, see the FX3U-CF-ADP User's Manual. 1.
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FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.5 FLCMD / FX3U-CF-ADP command Detailed explanation of setting data Details of the setting data in the FLCMD instruction are as shown below. Setting items Description Data Type Contents of instruction for operation K-1 : Forcibly writes all buffered data to the CompactFlashTM card. K0 to K63 : Forcibly writes the buffered data of the specified file ID to the CompactFlashTM card.
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FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 31 FLSTRD / FX3U-CF-ADP status read FX3U(C) FX3G(C) FX3S FX2N(C) FX1N(C) FX1S FXU/FX2C FX0N FX0(S) 32 The FLSTRD instruction reads the status (including the error information and file information) of the FX3UCFADP. → As for explanation of the instruction, see the FX3U-CF-ADP User's Manual. 1.
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FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.6 FLSTRD / FX3U-CF-ADP status read Detailed explanation of setting data Details of the setting data in the FLSTRD instruction are as shown below.
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FXCPU Structured Programming Manual 34 Applied Instructions (FX3U-CF-ADP) [Basic & Applied Instruction] 34.6 FLSTRD / FX3U-CF-ADP status read 31 Setting items Applied Instructions (Data Transfer 3) • When is "K1024 (H400)" The FLSTRD instruction reads the error information (error flag). Description Error detection signal b0 : The CompactFlashTM card is not mounted.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.1 Outline 35. Interrupt Function and Pulse Catch Function This chapter explains the built-in interrupt function and pulse catch function in FX PLCs. The input, special devices and timers in the explanations relate to the FX3U and FX3UC PLCs. Note that these differ from one model of PLC to another. → FX Structured Programming Manual [Device & Common] 35.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 31 Common items Applied Instructions (Data Transfer 3) 35.2 35.2 Common items 35.2.1 Interrupt function 32 Applied Instructions (High Speed Processing 2) Three types of interrupt, namely, input interrupt, timer interrupt and counter interrupt, are available. Observe the following in creating an interrupt program. 1) Create a task for interrupt and main program.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.2 Common items 35.2.2 How to disable interrupt function and pulse catch function This section describes how to disable the interrupt function and pulse catch function. 1. Limiting the program interrupt range [interrupt function and pulse catch function] 1) Programming method Program the DI instruction to set the interrupt disabled zone.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.2 Common items 31 1) Programming method The special auxiliary relays M8050 to M8059 for disabling interrupt are provided. While an interrupt disable flag (M8050 to M8059) is ON, a corresponding interrupt program is not executed even if the interrupt disable flag is set to OFF after a corresponding interrupt is generated.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.2 Common items 35.2.4 Cautions on use (common) This section explains common cautions on using the interrupt function or pulse catch function. Specific cautions on each interrupt function are explained in the description of each interrupt function. 1. Processing when many interrupts are generated When many interrupts are generated in turn, priority is given to the first one.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.2 Common items 31 Execution of interrupt program I001 triggered by X000 Applied Instructions (Data Transfer 3) 2) Timing chart Interrupt program 32 X001 Applied Instructions (High Speed Processing 2) Current value of C0 3 Because the C0 reset instruction is valid, the current value of C0 remains unchanged even if pulses are input. Counter is reset. 2 1 33 C0 remains reset.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35.3 35 Interrupt Function and Pulse Catch Function 35.3 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] 35.3.1 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] 1. Outline An interrupt routine is executed by the input signal from an input X000 to X005. 2.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.3 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] 31 When either one among M8050 to M8055 is set to ON in a program, interrupts from the corresponding input number are disabled. (Refer to the previous page for the correspondence.) 6.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.3 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] 7. Program example 1) When using both an external input interrupt at the rising edge and the output refresh (REF instruction) In the program example shown below, the output Y000 immediately turns ON when the rising edge of the external input X000 is detected.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.3 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] [Main program] [Interrupt program] (Event: I201) When the rising edge of X002 is detected EN RUN monitor INC ENO d 33 When X002 turns ON, "1" is added to the value of D0. INC instruction executes increment in every operation cycle, but the interrupt routine is executed only once by an input signal.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.3 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] 35.3.2 Examples of practical programs (programs to measure short pulse width) By using a 1 ms retentive type timer or the special data register D8099 (high speed ring counter), the short pulse width can be measured in 1 ms or 0.1 ms units. 1.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.3 Input Interrupt (Interrupt Triggered by External Signal) [Without Delay Function] [Main program] EN Interrupts are enabled by EI instruction. The main program is described. EI ENO 31 Applied Instructions (Data Transfer 3) 2.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.4 35.4 Input Interrupt (Interrupt by External Signal) [With Delay function] Input Interrupt (Interrupt by External Signal) [With Delay function] 1. Outline An input interrupt has the function to delay execution of an interrupt routine in units of 1 ms. The delay time can be specified using the pattern program shown below.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 31 Timer Interrupt (Interrupt in Constant Cycle) Applied Instructions (Data Transfer 3) 35.5 35.5 Timer Interrupt (Interrupt in Constant Cycle) 35.5.1 Timer Interrupt (Interrupt in Constant Cycle) 32 An interrupt routine is executed at every 10 to 99 ms without being affected by the operation cycle of a PLC.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.5 Timer Interrupt (Interrupt in Constant Cycle) 6. Program example In the program example shown below, data is added and addition result is compared with the set value at every 10 ms. 1) Program example [Main program] EN X001 EN Interrupts are enabled by EI instruction. The main program is described.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.5 Timer Interrupt (Interrupt in Constant Cycle) 31 The ramp signal output circuit shown below is programmed using the timer interrupt function executed every 10 ms. 1) Ramp output pattern D4 is occupied as a register for counting the number of times of execution.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.5 Timer Interrupt (Interrupt in Constant Cycle) 3. Cautions 1) When the HKY, SEGL or PR instruction is used in an interrupt program, the instruction turns ON M8029 in the interrupt program.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.5 Timer Interrupt (Interrupt in Constant Cycle) Countermeasures program example 32 [Main program] EN ENO EN DI ENO K6 H6F K1 EN s1 s2 n EN IVCK ENO d D100 34 Applied Instructions (FX3U-CF-ADP) M8029 33 Applied Instructions (Extension File Register Control) M100 Applied Instructions (High Speed Processing 2) EI RST ENO EI EN ENO When interrupt is given at every 20 ms.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35.6 35 Interrupt Function and Pulse Catch Function 35.6 Counter Interrupt - Interrupt Triggered by Counting Up of High Speed Counter Counter Interrupt - Interrupt Triggered by Counting Up of High Speed Counter 1. Outline This type of interrupt utilizes the current value of a high speed counter. The FX0S, FX0, FX0N, FX1S, FX1N, FX1NC, FX3S, FX3G or FX3GC PLC does not support the counter interrupt function. The FXU PLC of V 3.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.7 Pulse Catch Function[M8170 to M8177] 31 When only controlling the ON/OFF status of an output relay (Y) or auxiliary relay (M) according to the current value of a high speed counter, a required program can be easily created using DHSCS, DHSCR or DHSZ instruction. 6.
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FXCPU Structured Programming Manual 35 Interrupt Function and Pulse Catch Function [Basic & Applied Instruction] 35.7 Pulse Catch Function[M8170 to M8177] 2. Program example The FX0S, FX0, FX0N, FX1S, FX1N, FX1NC, FX3S, FX3G or FX3GC PLC does not require the EI instruction. When the rising edge of X000 is detected, M8170 is set as interrupt. The pulse catch result is reset.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35.8 Pulse width/Pulse period measurement function [M8075 to M8083, D8074 to D8097] 31 Pulse width/Pulse period measurement function [M8075 to M8083, D8074 to D8097] Applied Instructions (Data Transfer 3) 35.8 35 Interrupt Function and Pulse Catch Function This function is supported only in FX3G PLC (Ver.1.10 or later) and FX3GC.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.8 Pulse width/Pulse period measurement function [M8075 to M8083, D8074 to D8097] 2) Pulse period measurement The pulse period of the input signal from X000 is measured. ON X000 OFF This duration is measured. [Main program] EI EN ENO M8075 Pulse width/Pulse period measurement setting flag X2 M8076 X000 is used for the pulse width/pulse period measurement function.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.8 Pulse width/Pulse period measurement function [M8075 to M8083, D8074 to D8097] ON OFF X001 ON OFF 32 Applied Instructions (High Speed Processing 2) X000 This duration is measured. [Main program] 33 Pulse width/Pulse period measurement setting flag M8076 X000 is used for the pulse width/pulse period measurement function.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] [Interrupt program] (Event: I101) 35 Interrupt Function and Pulse Catch Function 35.8 Pulse width/Pulse period measurement function [M8075 to M8083, D8074 to D8097] X001 Rising edge interrupt DMOV EN ENO M8000 RUN monitor s D8074 d D0 The ring counter value at the rising edge of the input signal from X000 stored in D8074 and D8075 is transferred to D1 and D0.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] 35 Interrupt Function and Pulse Catch Function 35.8 Pulse width/Pulse period measurement function [M8075 to M8083, D8074 to D8097] 31 • The pulse width/pulse period measurement function and input interrupts can be used at the same time in a same input terminal.
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FXCPU Structured Programming Manual Appendix A: Relationships between devices and addresses [Basic & Applied Instruction] Appendix A: Relationships between devices and addresses The table below shows the relationships between devices and addresses. Device Timer Input relay X Xn Address %IXn Device X367 Address %IX247 Output relay Y Yn %QXn Y367 %QX247 Auxiliary relay M Mn %MX0.n M499 %MX0.499 Contact TS Tn %MX3.n TS191 %MX3.191 Coil TC Tn %MX5.n TC191 %MX5.
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Appendix A: Relationships between devices and addresses FXCPU Structured Programming Manual [Basic & Applied Instruction] 31 Applied Instructions (Data Transfer 3) MEMO 32 Applied Instructions (High Speed Processing 2) 33 Applied Instructions (Extension File Register Control) 34 Applied Instructions (FX3U-CF-ADP) 35 Interrupt Function and Pulse Catch Function A Relationships between devices and addresses B Applied Instruction List 819
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] Appendix B-1 Applied instructions [by instruction type] Applied instructions are classified into the following twenty-one types: 1 Data transfer instructions 11 Program flow control instructions 2 Data conversion instru
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] 31 Mnemonic Function Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] 3. Comparison instructions Mnemonic DBKCMP<> DBKCMP<= DBKCMP>= DBKCMP=P DBKCMP>P DBKCMP
DBKCMP >=P Block Data Compare DAND ≤ WORP DOR Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] DACOS DACOSP DATAN DATANP RND RNDP Function Ref. Page Floating Point Arc Cosine 488 Floating Point Arc Tangent 490 Random Number Generation 587 225 Decode 229 32 Encode 233 Mean 242 33 Sum of Word Data 497 Mnemonic ZRST ZRSTP DECO DECOP ENCO ENCOP Function Ref. Page MEAN 7.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] 9. Data operation instructions Mnemonic Function Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] 31 Mnemonic TCMP TCMPP TZCP TADD TADDP TSUB TSUBP TRD TWRP 541 RTC Data Zone Compare 544 RTC Data Addition 547 RTC Data Subtraction 549 Read RTC data 557 Set RTC data 559 DHTOS 714 Inverter Parameter Write 716 IVBWR Inverter Parameter Block Write 719 IVMC Inverter Multi Command 721
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-1 Applied instructions [by instruction type] 19.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-2 Applied instructions [in alphabetical order] 31 Mnemonic Function Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Mnemonic Appendix B-2 Applied instructions [in alphabetical order] Function Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-2 Applied instructions [in alphabetical order] 31 Function Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Mnemonic Appendix B-2 Applied instructions [in alphabetical order] Function Ref. Page D DVIT DWSUM DWSUMP DXCH DXCHP DXOR DXORP DZCP DZCPP DZONE DZONEP DZRN ENCO ENCOP Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Appendix B-2 Applied instructions [in alphabetical order] 31 Function Ref. Page L LOGR LOGRP Mnemonic Function Ref.
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FXCPU Structured Programming Manual Appendix B: Applied Instruction List [by Instruction Type / in Alphabetic Order] [Basic & Applied Instruction] Mnemonic Appendix B-2 Applied instructions [in alphabetical order] Function Ref.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Warranty Warranty Please confirm the following product warranty details before using this product. 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or Mitsubishi Service Company.
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FXCPU Structured Programming Manual [Basic & Applied Instruction] Revised History Revised History 834 Date created Revision Description 1/2009 A First edition 7/2009 B • Instructions was added: INV, MEP, MEF, RS,FLCRT, FLDEL, FLWR, FLRD, FLCMD, FLSTRD • The following instructions are provided in the FX3G series. RD3A, RD3AP, WR3A, WR3AP 2/2010 C • Manual name of a related manual was changed. 4/2010 D • Operands in sequence instructions was changed into array type. • Appendix B was added.
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FXCPU Structured Programming Manual Basic & Applied Instruction HEAD OFFICE: TOKYO BUILDING, 2-7-3 MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN HIMEJI WORKS: 840, CHIYODA CHO, HIMEJI, JAPAN MODEL FX-KP-SM-E MODEL CODE 09R926 JY997D34701L (MEE) Effective Sep. 2013 Specifications are subject to change without notice.