QCPU User's Manual (Multiple CPU System) -Q00CPU -Q01CPU -Q02(H)CPU -Q06HCPU -Q12HCPU -Q25HCPU -Q02PHCPU -Q06PHCPU -Q12PHCPU -Q25PHCPU -Q00UCPU -Q01UCPU -Q02UCPU -Q03UDVCPU -Q03UD(E)CPU -Q04UDVCPU -Q04UD(E)HCPU -Q06UDVCPU -Q06UD(E)HCPU -Q10UD(E)HCPU -Q13UDVCPU -Q13UD(E)HCPU -Q20UD(E)HCPU -Q26UDVCPU -Q26UD(E)HCPU -Q50UDEHCPU -Q100UDEHCPU
SAFETY PRECAUTIONS (Read these precautions before using this product.) Before using this product, please read this manual and the relevant manuals carefully and pay full attention to safety to handle the product correctly. In this manual, the safety precautions are classified into two levels: " WARNING" and " CAUTION". WARNING Indicates that incorrect handling may cause hazardous conditions, resulting in death or severe injury.
[Design Precautions] WARNING ● In an output module, when a load current exceeding the rated current or an overcurrent caused by a load short-circuit flows for a long time, it may cause smoke and fire. To prevent this, configure an external safety circuit, such as a fuse. ● Configure a circuit so that the programmable controller is turned on first and then the external power supply. If the external power supply is turned on first, an accident may occur due to an incorrect output or malfunction.
[Installation Precautions] CAUTION ● Use the programmable controller in an environment that meets the general specifications in the QCPU User's Manual (Hardware Design, Maintenance and Inspection). Failure to do so may result in electric shock, fire, malfunction, or damage to or deterioration of the product.
[Wiring Precautions] CAUTION ● Individually ground the FG and LG terminals of the programmable controller with a ground resistance of 100 or less. Failure to do so may result in electric shock or malfunction. ● Use applicable solderless terminals and tighten them within the specified torque range. If any spade solderless terminal is used, it may be disconnected when the terminal screw comes loose, resulting in failure.
[Startup and Maintenance Precautions] WARNING ● Do not touch any terminal while power is on. Doing so will cause electric shock or malfunction. ● Correctly connect the battery connector. Do not charge, disassemble, heat, short-circuit, solder, or throw the battery into the fire. Also, do not expose it to liquid or strong shock. Doing so will cause the battery to produce heat, explode, ignite, or leak, resulting in injury and fire.
[Disposal Precautions] CAUTION ● When disposing of this product, treat it as industrial waste. When disposing of batteries, separate them from other wastes according to the local regulations. (For the Battery Directive in EU member states, refer to the QCPU User's Manual (Hardware Design, Maintenance and Inspection).) [Transportation Precautions] CAUTION ● When transporting lithium batteries, follow the transportation regulations.
CONDITIONS OF USE FOR THE PRODUCT (1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions; i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major or serious accident; and ii) where the backup and fail-safe function are systematically or automatically provided outside of the PRODUCT for the case of any problem, fault or failure occurring in the PRODUCT.
INTRODUCTION This manual describes the system configurations, functions, and communication methods with external devices required in a multiple CPU system. Before using this product, please read this manual and the relevant manuals carefully and develop familiarity with the functions and performance of the Q series programmable controller to handle the product correctly.
Memo 9
CONTENTS CONTENTS SAFETY PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CONDITIONS OF USE FOR THE PRODUCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MANUALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 104 5.1 Access to Controlled Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2 Access to Non-controlled Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2.1 Loading input (X) data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.2.2 Loading output (Y) data . . . . . .
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following lists. The numbers in the "CPU module" and the respective modules are as follows.
(2) Programming manual Manual name Description MELSEC-Q/L Programming Manual (Common Instruction) Detailed description and usage of instructions used in programs MELSEC-Q/L/QnA Programming Manual System configuration, specifications, functions, (SFC) programming, and error codes for SFC (MELSAP3) System configuration, specifications, functions, L) programming, and error codes for SFC (MELSAP-L) MELSEC-Q/L Programming Manual
MANUAL PAGE ORGANIZATION In this manual, pages are organized and the symbols are used as shown below. The following page illustration is for explanation purpose only, and is different from the actual pages. "" is used for window names and items. The chapter of the current page is shown. shows operating procedures. shows mouse operations.*1 [ ] is used for items in the menu bar and the project window. The section of the current page is shown. Ex. shows setting or operating examples.
TERMS Unless otherwise specified, this manual uses the following generic terms and abbreviations. * indicates a part of the model or version. Ex.
Term QnUDVCPU QnUDE(H)CPU Description A generic term for the Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU A generic term for the Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU, Q20UDEHCPU, Q26UDEHCPU, Q50UDEHCPU, and Q100UDEHCPU Q172CPUN(-T) A generic term for the Q172CPUN and Q172CPUN-T Q173CPUN(-T) A generic term for the Q173CPUN and Q173CPUN-T Q172HCPU(-T) A generic term for the Q172HCPU and Q172HCPU-T Q173HCPU(-T) A generic term for the Q173HCPU and Q173HCPU-T Q172DC
Term A series power supply module The abbreviation for the Q61SP slim type power supply module A generic term for the Q63RP and Q64RP redundant power supply modules Life detection power supply module The abbreviation for the Q61P-D life detection power supply module Network module A generic term for the CC-Link IE Controller Network module and CC-Link IE Field Network module MELSECNET/H module The abbreviation for the MELSECNET/H network module Ethernet module The abbreviation for the Ethernet
CHAPTER 1 OVERVIEW In a multiple CPU system, more than one CPU module is mounted on the main base unit and each CPU module controls I/O modules and intelligent function modules separately. QCPUs, Motion CPUs, C Controller modules, and PC CPU modules can be used in multiple CPU systems. ( Page 31, CHAPTER 3) Motion CPU QCPU PC CPU module Remark This manual describes the combinations of CPU modules and communications among CPU modules in a multiple CPU system.
CHAPTER 1 OVERVIEW (a) Distribution of processing The overall system scan time can be reduced by distributing the high-load processing performed in a single CPU module over multiple CPU modules. Data processing (low speed) Machine control (high speed) A single QCPU controls an entire system.
(2) Configuring sequence control and motion control systems on the same base unit In a multiple CPU system consisting of a QCPU and Motion CPU, sequence control and motion control can be implemented together to achieve a high-level motion system. Control Sequence control Motion control Operation switch Operation status lamp Servo amplifier SSCNET Servo motor Servo amplifier Servo motor Interaction with Motion CPUs for motion control is enhanced in Universal model QCPUs.
CHAPTER 1 OVERVIEW (b) Synchronous processing with a motion control 1 An interrupt program which is synchronized with the operation cycle of a Motion CPU (multiple CPU synchronous interrupt program) can be executed. Command input or output from a Motion CPU can be synchronized with the operation cycle of the Motion CPU, which enables high-speed data transfer independent of scan time. ( Page 166, Section 6.
(c) Checking data send/receive timing between CPU modules With the sampling trace function of Universal model QCPUs, the data communications timing with a Motion CPU can be checked. Timing can also be checked between Universal model QCPUs. The sampling trace function facilitates the processing for checking the data send/receive timing between CPU modules, and reduces the time for debugging the multiple CPU system.
CHAPTER 1 OVERVIEW 1 (3) Data communications among CPU modules The following data communications can be performed among CPU modules in a multiple CPU system. (a) Transferring data among CPU modules Data can be transferred among CPU modules by setting auto refresh using a programming tool. ( Page 122, Section 6.1.1 to Page 135, Section 6.1.2) (b) Reading data from other CPU modules Each CPU module can read data from other CPU modules whenever required using the following instructions.
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM 2.1 CPU Numbers CPU numbers are assigned to identify CPU modules contained in a multiple CPU system. A CPU module mounted in the CPU slot of a main base unit will be CPU No.1. CPU No.2, No.3, and No.4 will be assigned sequentially to the right of CPU No.1. CPU slot: CPU No.1 Slot 0: CPU No.2 Slot 1: CPU No.3 Slot 2: CPU No.
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM (2) Uses of CPU numbers CPU numbers are used for the following purposes. 2 (a) Setting control CPUs CPU numbers are used to set a control CPU for each I/O module and intelligent function module. CPU 0 1 2 3 4 5 6 7 1 2 1 1 1 1 2 2 2 Slot number Control CPU setting Controlled by CPU No.1. Controlled by CPU No.2. Set control CPUs in PLC parameter ("I/O Assignment").
(b) Specifying a connection target using a programming tool (personal computer) CPU numbers are used to specify a CPU module to which a programming tool is connected. CPU 0 1 2 1 2 3 4 Slot number CPU number A programming tool communicates with CPU No.2. Specify "PLC No.2". (3) Checking the host CPU number The host CPU number of a QCPU is stored in SD395 (Multiple CPU system information). A host CPU number check program (refer to an example below) should be created.
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM 2.2 I/O Number Assignment A multiple CPU system uses the following two I/O numbers. 2 • I/O numbers used by CPU modules to communicate with I/O modules and intelligent function modules ( Page 27, Section 2.2.1) • I/O numbers used by CPU modules to communicate with other CPU modules ( 2.2.1 Page 30, Section 2.2.
● Some CPU modules occupy two or more slots. When this type of CPU module is used, the second slot and after are treated as empty slots. In the case of a PC CPU module, for example, the right slot of the occupied two slots is treated as an empty slot having 16 points. (An empty slot occupies 16 points by default.) For this reason, the start I/O number of the module mounted on the right of the PC CPU module will be "10H".
CHAPTER 2 CONCEPT OF MULTIPLE CPU SYSTEM Ex. Example of I/O number assignment Main base unit.........When 32-point modules are mounted in each slot 2 Q series power supply module 7 8 9 10 11 E0 to FF 6 100 to 11F 5 C0 to DF 4 80 to 9F 3 A0 to BF 2 60 to 7F 1 40 to 5F 0 20 to 3F CPU 00 to 1F Q312B (12 slots occupied) ...... Slot number ...... I/O number CPU No.4 CPU No.3 CPU No.2 CPU No.1 Extension base unit .........
2.2.2 I/O numbers of CPU modules In multiple CPU systems, I/O numbers are assigned to each CPU module to specify mounted CPU modules. The I/O number for each CPU module is fixed at the corresponding slot, and cannot be changed in PLC parameter ("I/O Assignment"). The following is the list of I/O numbers that can be assigned to CPU modules.
CHAPTER 3 SYSTEM CONFIGURATION CHAPTER 3 SYSTEM CONFIGURATION In a multiple CPU system, QCPUs, motion CPUs, C Controller modules, and PC CPU modules can be mounted in the CPU slot to slot 2 of the main base unit. I/O modules and intelligent function modules are mounted to the right of CPU modules. 3 This chapter describes the system configurations according to the QCPU used as CPU No.1. Remark ● For a multiple CPU system using a C Controller module as CPU No.
3.1 System Using Basic Model QCPU as CPU No.1 This section describes the system configuration using a Basic model QCPU as CPU No.1. 3.1.1 Available CPU modules, base units, power supply modules, and extension cables Available CPU modules and the number of mountable modules differ depending on the main base unit used.
CHAPTER 3 SYSTEM CONFIGURATION (b) Precautions • If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124) occurs. • "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). • When a C Controller module which occupies three slots is used, the maximum number of mountable I/O modules will be two smaller than the number defined in the table on Page 32, Section 3.1.1 (1) (a). • A PC CPU module occupies two slots.
(2) When a redundant power main base unit (Q3RB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description 2 CPU modules Number of CPU CPU No.1 (Basic model QCPU) modules CPU No.
CHAPTER 3 SYSTEM CONFIGURATION (3) When a slim type main base unit (Q3SB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules 3 2 CPU modules CPU No.1 (Basic model QCPU) CPU No.
(4) When a multiple CPU high speed main base unit (Q3DB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description 2 CPU modules Number of CPU CPU No.1 (Basic model QCPU) modules CPU No.
CHAPTER 3 SYSTEM CONFIGURATION 3.1.2 CPU module combinations and mounting positions This section describes the combinations and mounting positions of CPU modules when a Basic model QCPU is used as CPU No.1. Note that the CPU modules that can be mounted differ depending on the main base unit used. ( Page 32, Section 3.1.1) 3 (1) Combinations Number of CPU modules that can be mounted as CPU No.2 or others High Motion CPU Performance CPU No.
(c) C Controller module or PC CPU module Either a C Controller module or PC CPU module can be mounted on the extreme right of the other CPU module(s). No CPU module can be mounted on the right of the C Controller module or PC CPU module. 1 Slot number 2 Motion CPU 0 PC CPU module Basic model QCPU Power supply module CPU (d) Empty slot setting Empty slots can be reserved for future addition of CPU modules. Set the number of CPU modules including empty slots in "No.
CHAPTER 3 SYSTEM CONFIGURATION ● When a Basic model QCPU is used, "PLC (Empty)" can be set between CPU modules. This is useful when adding a Motion CPU to the system where a Basic model QCPU and a C Controller module or PC CPU module are used. No program modification is required because the CPU number of the C Controller module or PC CPU module does not need to be changed even after the new module is added.
3.1.3 Available I/O modules and intelligent function modules This section describes I/O modules and intelligent function modules that can be used. (1) I/O modules and interrupt module I/O modules (QX and QY) and interrupt module (QI60) can be used. Any CPU module can be set as a control CPU. (2) Intelligent function modules Intelligent function modules with function version B or later can be used. Any CPU module can be set as a control CPU.
CHAPTER 3 SYSTEM CONFIGURATION 3.2 System Using High Performance Model QCPU or Process CPU as CPU No.1 This section describes the system configuration using a High Performance model QCPU or Process CPU as CPU No.1. 3.2.1 Available CPU modules, base units, power supply modules, and extension cables 3 Available CPU modules and the number of mountable modules differ depending on the main base unit used.
Item Description Maximum number of mountable I/O modules 65 - (Number of CPU modules) Applicable main base unit Q33B, Q35B, Q38B, Q312B Type requiring no power supply module (Q series) Q52B, Q55B Type requiring power supply module (Q series) Q63B, Q65B, Q68B, Q612B Type requiring no power supply module (AnS series)*3*4 Applicable extension base unit Type requiring power supply module QA1S65B, QA1S68B, QA1S6ADP+A1S6B*6 (AnS series)*3*5 Type requiring no power supply module (A series)*3 Type req
CHAPTER 3 SYSTEM CONFIGURATION (2) When a redundant power main base unit (Q3RB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules High Performance model QCPU Q02(H)CPU, Q06HCPU, Q12HCPU, Q25HCPU Function version B Process CPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU No function version restriction Universal model QCPU Q03UD(E)CPU, Q03UDVCPU, Q04UD(E)HCPU, Q04UDVCPU, Q06UD(E)HCPU, Q06UDVCPU, Q10UD(E)HCPU, Q13
(3) When a slim type main base unit (Q3SB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules 3 CPU modules High Performance model QCPU Q02(H)CPU, Q06HCPU, Q12HCPU, Q25HCPU Function version B Universal model QCPU Q03UD(E)CPU, Q03UDVCPU, Q04UD(E)HCPU, Q04UDVCPU, Q06UD(E)HCPU, Q06UDVCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q13UDVCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q26UDVCPU, Q50UDEHCPU, Q100UDEHCPU No function version res
CHAPTER 3 SYSTEM CONFIGURATION (4) When a multiple CPU high speed main base unit (Q3DB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules • Function version B • Function version B with a serial number (first five digits) of "03051" or later when a module is used as CPU No.
(b) Precautions • If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124) occurs. • "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). • A C Controller module (Q24DHCCPU-V) occupies three slots. When this module is used, the maximum number of mountable I/O modules will be two smaller than the number defined in the table on Page 45, Section 3.2.1 (4) (a).
CHAPTER 3 SYSTEM CONFIGURATION 3.2.2 CPU module combinations and mounting positions This section describes the combinations and mounting positions of CPU modules when a High Performance model QCPU or Process CPU is used as CPU No.1. Note that the CPU modules that can be mounted differ depending on the main base unit used. ( Page 41, Section 3.2.1) 3 (1) Combinations Number of CPUs that can be mounted as CPU No.
(2) Mounting positions The following shows the possible combinations of mounting positions of CPU modules in a multiple CPU system. CPU No.1 CPU No.2 CPU No.3 CPU No.4 Q Q Q Q M C P M M C P C C P M M M C P C C P C P *1 48 C C Q : QCPU*1 M : Motion CPU C : C Controller module P : PC CPU module The QCPU used as CPU No.1 indicates a High Performance model QCPU or Process CPU. The QCPU used as CPU No.
CHAPTER 3 SYSTEM CONFIGURATION (a) High Performance model QCPU or Process CPU Up to four High Performance model QCPUs and/or Process CPUs can be mounted in the CPU slot (the slot on the right of the power supply module) to slot 2 of the main base unit. (b) Universal model QCPU Up to three Universal model QCPUs can be mounted in slot 0 to slot 2 of the main base unit.
(f) Empty slot setting Empty slots can be reserved for future addition of CPU modules. Set the number of CPU modules including empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of a target slot from the right in PLC parameter ("I/O Assignment"). Ex.
CHAPTER 3 SYSTEM CONFIGURATION 3.2.3 Available I/O modules and intelligent function modules This section describes the I/O modules and intelligent function modules that can be used. (1) I/O modules, interrupt modules, and intelligent function modules Refer to the system configuration using a Basic model QCPU as CPU No.1. ( Page 40, Section 3.1.3 (1), Page 40, Section 3.1.
(3) Number of mountable modules Refer to Page 68, Section 3.5. (4) Access ranges of controlled and non-controlled modules. Refer to the system configuration using a Basic model QCPU as CPU No.1. ( 52 Page 40, Section 3.1.
CHAPTER 3 SYSTEM CONFIGURATION 3.3 System Using Universal Model QCPU as CPU No.1 This section describes the system configuration using a Universal model QCPU as CPU No.1. 3.3.1 Available CPU modules, base units, power supply modules, and extension cables 3 Available CPU modules and the number of mountable modules differ depending on the main base unit used.
Item Description Applicable CPU PC CPU module module*1 PPC-CPU852(MS)-512 • Driver S/W (PPC-DRV-02) version 1.03 or later when used with the Q00UCPU or Q01UCPU • Driver S/W (PPC-DRV-02) version 1.01 or later when used with the Q02UCPU • Driver S/W (PPC-DRV-02) version 1.01 or later when used with the Q03UDCPU, Q04UDHCPU, or Q06UDHCPU • Driver S/W (PPC-DRV-02) version 1.02 or later when used with the Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q13UD(E)HCPU, or Q26UD(E)HCPU • Driver S/W (PPC-DRV-02) version 1.
CHAPTER 3 SYSTEM CONFIGURATION (b) Precautions • If I/O modules are mounted exceeding the maximum number, "SP.UNIT LAY ERR" (error code: 2124) occurs. • "Number of CPU modules" indicates the number set in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). • When a C Controller module which occupies three slots is used, the maximum number of mountable I/O modules will be two smaller than the number defined in the table on Page 53, Section 3.3.1 (1) (a). • A PC CPU module occupies two slots.
(2) When a main base unit (Q3B) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules 4 CPU modules Q00UCPU, Q01UCPU, Q02UCPU Q03UD(E)CPU, Q03UDVCPU, Q04UD(E)HCPU, Q04UDVCPU, Q06UD(E)HCPU, Q06UDVCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q13UDVCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q26UDVCPU, Q50UDEHCPU, Q100UDEHCPU Universal model QCPU Q02(H)CPU, Q06HCPU, Q12HCPU, Q25HCPU Function version B Process CPU Q02PHCPU, Q06PHCPU, Q12P
CHAPTER 3 SYSTEM CONFIGURATION Item Description Maximum number of mountable I/O modules 65 - (Number of CPU modules), when the Q00UCPU or Q01UCPU is used: 25 - (Number of CPU modules), when the Q02UCPU is used: 37 - (Number of CPU modules) Applicable main base unit Q33B, Q35B, Q38B, Q312B Type requiring no power supply module (Q series) Q52B, Q55B Type requiring power supply module (Q series) Q63B, Q65B, Q68B, Q612B Type requiring no power supply module (AnS series)*3*5 Applicable extension base
(3) When a redundant power main base unit (Q3RB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules 4 CPU modules Q00UCPU, Q01UCPU, Q02UCPU The modules can be used as CPU No.1.
CHAPTER 3 SYSTEM CONFIGURATION (4) When a slim type main base unit (Q3SB) is used (a) Available modules, the number of extension base units, and the number of mountable modules Item Description Number of CPU modules Universal model QCPU High Performance model QCPU Q00UCPU, Q01UCPU, Q02UCPU The modules can be used as CPU No.1.
3.3.2 CPU module combinations and mounting positions This section describes the combinations and mounting positions of CPU modules when a Universal model QCPU is used as CPU No.1. Note that the CPU modules that can be mounted differ depending on the main base unit used. ( Page 53, Section 3.3.1) (1) Combinations Number of CPU modules that can be mounted as CPU No.2 or others CPU No.
CHAPTER 3 SYSTEM CONFIGURATION (2) Mounting positions The following shows the possible combinations of mounting positions of CPU modules in a multiple CPU system. • When the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1 *1 CPU No.1 CPU No.2 CPU No.3 Q M C Q : QCPU*1 P M : Motion CPU C C : C Controller module P P : PC CPU module 3 The QCPU indicates the Q00UCPU, Q01UCPU, or Q02UCPU. 3.3 System Using Universal Model QCPU as CPU No.1 3.3.
• When a CPU module other than the Q00UCPU, Q01UCPU, or Q02UCPU is used as CPU No.1 CPU No.1 CPU No.2 CPU No.3 CPU No.4 Q Q Q *2 Q M C P *2 Q M M C P C C P *2 M Q *2 Q M C P *2 M Q M C P C Q : QCPU*1 M : Motion CPU C : C Controller module P : PC CPU module C P C P *1 *2 62 C C The QCPU used as CPU No.1 indicates a Universal model QCPU (except the Q00UCPU, Q01UCPU, and Q02UCPU). The QCPU used as CPU No.
CHAPTER 3 SYSTEM CONFIGURATION (a) Universal model QCPU Only one Q00UCPU, Q01UCPU, or Q02UCPU can be mounted in the CPU slot (the slot on the right of the power supply module). Up to four Universal model QCPUs other than the Q00UCPU, Q01UCPU, and Q02UCPU can be mounted in the CPU slot (the slot on the right of the power supply module) to slot 2 of the main base unit.
(f) Empty slot setting Empty slots can be reserved for future addition of CPU modules. Set the number of CPU modules including empty slots in "No. of PLC" of PLC parameter ("Multiple CPU Setting"). Then, set "PLC (Empty)" to the type of a target slot in PLC parameter ("I/O Assignment").
CHAPTER 3 SYSTEM CONFIGURATION 3.4 Applicable Software This section describes software packages applicable in a multiple CPU system. (1) Applicable GX Works2, GX Developer, and PX Developer The following table lists the applicable versions of GX Works2, GX Developer, and PX Developer. QCPU Basic model QCPU High Performance model QCPU Version GX Works2 1.15R or later Q02PHCPU, Process CPU Q06PHCPU Q12PHCPU, 3 GX Developer 8.00A or later 6.00A or later PX Developer Use prohibited 8.
(2) Applicable GX Configurator The following tables list the applicable versions of GX Configurator. Applicable GX Configurator versions differ depending on the intelligent function module used.
CHAPTER 3 SYSTEM CONFIGURATION (b) When a Universal model QCPU is used Version compatible with the Universal model QCPU Product Used with Q02U/Q03UD/Q04UDH/ Q06UDHCPU *1 GX Configurator-AD 2.05F or later GX Configurator-DA 2.06G or later*1 GX Configurator-SC 2.12N or later*1 *1 Used with Used with Used with Q03UDE/Q04UDEH/ Q00U/Q01U/Q10UDH/ Q13UDH/Q26UDHCPU Q06UDEH/Q13UDEH/ Q20UDH/Q10UDEH/ Q26UDEHCPU Q20UDEHCPU *3 2.05F or later 2.05F or later*4 2.06G or later*2 2.06G or later*3 2.
3.5 Precautions for System Configuration This section describes restrictions and precautions on system configuration. (1) Number of mountable modules The number of mountable modules and supported functions are restricted depending on the CPU module used. For the number of modules that can be connected to each Motion CPU, C Controller module, or PC CPU module, refer to the manual for the CPU module used.
CHAPTER 3 SYSTEM CONFIGURATION (b) When a High Performance model QCPU or Process CPU is used Product Model CC-Link IE Controller Network • QJ71GP21-SX module*4 • QJ71GP21S-SX Maximum number of modules/units per system Up to 2 modules • QJ71LP21 • QJ71BR11 Up to 4 modules in total • QJ71LP21-25 MELSECNET/H module • QJ71LP21S-25 3 Up to 4 modules • QJ71LP21G • QJ71LP21GE • QJ71NT11B • QJ71E71 Ethernet interface module • QJ71E71-B2 Up to 4 modules • QJ71E71-B5 • QJ71E71-100 CC-Link system mast
Remark For the restrictions on mounting A-series modules on the QA6B or QA6ADP+A5B/A6B, refer to the following. QA65B/QA68B Extension Base Unit User's Manual QA6ADP QA Conversion Adapter Module User's Manual For the restrictions on mounting AnS-series modules on the QA1S6ADP+A1S5B/A1S6B, refer to the following.
CHAPTER 3 SYSTEM CONFIGURATION (c) When a Universal model QCPU is used Product Model CC-Link IE Controller Network • QJ71GP21-SX module*4 • QJ71GP21S-SX Maximum number of modules/units per system Up to 4 modules in total • QJ71LP21 • QJ71BR11 • QJ71LP21-25 MELSECNET/H module • QJ71LP21S-25 • QJ71LP21G • QJ71LP21GE With the Q00UCPU, Q01UCPU, or Q02UCPU, the maximum number of connectable modules is as follows: 3 • Q02UCPU: Up to 2 modules in total • Q00UCPU or Q01UCPU: Only 1 module • QJ71NT11B
*1 *2 *3 *4 *5 *6 *7 *8 *9 One CPU module can control the following number of modules by setting CC-Link network parameters. • Q00UCPU or Q01UCPU: Up to 2 modules • Q02UCPU: Up to 4 modules • Other CPU modules: Up to 8 modules There is no restriction on the number of mounted modules when the parameters are set with the CC-Link dedicated instructions. For the applicable GOT models, refer to the connection manual for the GOT used. The number indicates interrupt modules with no interrupt pointer setting.
CHAPTER 3 SYSTEM CONFIGURATION (2) Modules that have restrictions when used with an Universal model QCPU For modules that have restrictions when used with an Universal model QCPU, refer to the following manual. QnUCPU User's Manual (Function Explanation, Program Fundamentals) (3) Combinations of power supply modules, base units, and QCPUs There are some restrictions on combinations of power supply modules, base units, and QCPUs. ( QCPU User's Manual (Hardware Design, Maintenance and Inspection) 3 Ex.
(7) Precautions for connecting a GOT The following GOT series can be used. • GOT-A900 series*1 • GOT-F900 series (The Q-mode compatible operating system and communication driver must be installed.)*1 • GOT1000 series The GOT800 series, A77GOT, and A64GOT cannot be used. *1 74 Universal model QCPUs do not support the GOT-A900 and GOT-F900 series.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM This chapter describes the procedure for starting up a multiple CPU system. 4.1 Procedure Before Operation 4 Check box Determine the role of each CPU module. Determine the role (controls and functions) of each CPU module used in a multiple CPU system. Study details of device assignment. Study details of device assignment. To perform auto refresh of the CPU shared memory, the refresh range must be set consecutively.
Connect to a programming tool. Connect the CPU No.1 and a personal computer where a programming tool has been installed.*1 Write data to the CPU modules. Write programs and parameters to the CPU modules. To write data to the CPU No.2 and later, select the target CPU module in the Transfer Setup window of the programming tool. Page 112, Section 5.3 Run all the CPU modules. Set the RUN/STOP switch of all the CPU modules to the RUN position. Reset the CPU No.1.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 4.2 Operation Settings This section describes the settings required to operate a multiple CPU system. A system where three Universal model QCPUs are mounted shall be used as an example. (1) Parameters required (a) Basic model QCPU, High Performance model QCPU, and Process CPU Settings of parameters in double-lined squares, except some parameters, must be the same in all the CPU modules used in a multiple CPU system. ( Multiple CPU Setting Page 172, Appendix 1.
(b) Universal model QCPU Settings of parameters in double-lined squares, except some parameters, must be the same in all the CPU modules used in a multiple CPU system. ( Multiple CPU Setting Page 172, Appendix 1.1) No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 4.2.1 System configuration example This section describes the procedure for setting parameters required in a multiple CPU system, using the following system as an example. 4 5 6 7 Input module Output module Input module Output module Intelligent function module 1 1 2 2 2 2 3 9 10 3 3 3 11 12 13 14 15 4 Slot number Control CPU setting Slot number Control CPU setting 4.2 Operation Settings 4.2.
4.2.2 Parameter settings This section describes parameters required for the system configuration on Page 79, Section 4.2.1. Use a programming tool to set parameters. • Settings of parameters in double-lined squares on Page 77, Section 4.2 (1) must be the same in all the CPU modules in a multiple CPU system. • The necessity of parameters differs depending on the QCPU used. ( Page 77, Section 4.2 (1)) (1) Setting parameters (for the first time) 1.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM Item Description Default Set the number of CPU modules mounted on the main base unit in the multiple CPU system. The number of modules differs depending on the CPU No. of PLC module used as CPU No.1 and the main base unit used. ( Page 31, 1 CHAPTER 3) This parameter must be set. Set this parameter to check the host CPU number in the multiple CPU system.
Item Description (1) Default Basic model QCPU This parameter is not supported. (2) Process CPU Check the checkbox to enable online module change. Online Module Change (3) Not selected High Performance model QCPU and Universal model QCPU Check the checkbox if online module change is enabled with a Process CPU. Modules controlled by a High Performance model QCPU or Universal model QCPU cannot be replaced online.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 3. Set the types and points for the mounted modules in the "I/O Assignment" window of PLC parameter. Project window [Parameter] [PLC Parameter] [I/O Assignment] 4 Item Description Default Select the type of a mounted module. To reserve an empty slot for the future addition of a CPU module, select "PLC (Empty)". The slots where "PLC (Empty)" can be set differ depending on the CPU module used as CPU No.1. • When a Basic model QCPU is used as CPU No.1 - 4.
4. Click the button in the "I/O Assignment" window, and set a control CPU for each I/O module and intelligent function module. Item Description Set the CPU module that controls each I/O module and intelligent function Control PLC module mounted. 5. 6. PLC No.1 Set other parameters required. Save the project using the programming tool so that the multiple CPU system parameter settings can be used in other CPU modules.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM (2) Using the multiple CPU system parameters set to another CPU module 1. Click the button in the "Multiple CPU Setting" window of PLC parameter. Select and open the project file from which the settings will be imported. Project window [Parameter] [PLC Parameter] [Multiple CPU Setting] 4 The settings of a project file created with a different programming tool cannot be used. Reuse such settings as follows.
4. Check the "Points Occupied by Empty Slot" setting in the "PLC System" window of PLC parameter. Project window [Parameter] [PLC parameter] [PLC System] "Points Occupied by Empty slots" 5. Check the settings in the "I/O Assignment" window of PLC parameter. Project window [PLC parameter] 6. Click the 7. Set other parameters required. 8. Save the project using the programming tool.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 4.3 Program Examples for Communications by Auto Refresh 4.3.1 Program examples for Basic model QCPU, High Performance model QCPU, and Process CPU This section provides program examples for communicating data by auto refresh between the CPU modules in the following system.
(b) Auto refresh setting Set auto refresh parameters. ( Project window Page 123, Section 6.1.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM (2) Program examples (a) Sending bit data and word data from CPU No.1 to CPU No.2 • Devices used in CPU modules Device used in CPU No.1 M0 D0 and D1 Send data from CPU No.1 to CPU No.2 Device used in CPU No.2 M0 D0 and D1 D100 - Send data from CPU No.1 to CPU No.2 Storage device for data received from CPU No.1 YE0 Data reception flag (for data from CPU No.1) SM400 Always ON 4 • Program example of CPU No.1 CPU No.1 send data (bit) Send command CPU No.
(b) Continuously sending data from CPU No.1 to CPU No.2 • Devices used in CPU modules Device used in CPU No.1 M40 Send data from CPU No.2 to CPU No.1 D10 to D18 D81 to D88 SM400 Send data from CPU No.1 to CPU No.2 Storage device of send data to CPU No.2 Device used in CPU No.2 M40 D10 to D18 Send data from CPU No.2 to CPU No.1 Send data from CPU No.1 to CPU No.2 D121 to Storage device for data received from CPU D128 No.1 Always ON - For handshake between CPU No.1 and No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM (c) Continuously reading/writing data between CPU No.1 and No.2 using the user setting area Data can be read/write between CPU modules by programs using the user setting area in the CPU shared memory. The same number of points must be set for CPU No.1 and CPU No.2 in the auto refresh setting. 4 Consequently, the user setting area will be a range from 0822H to 0FFFH. ( Page 118, Section 6.
• Devices used in CPU modules Device used in CPU No.1 M31 Send data from CPU No.1 to CPU No.2 M63 D100 to D149 Device used in CPU No.2 M31 Send data from CPU No.1 to CPU No.2 Send data from CPU No.2 to CPU No.1 M63 Send data from CPU No.2 to CPU No.1 Storage device for data received from CPU D200 to No.2 D249 - Storage device of send data to CPU No.1 M100 Write completion bit of the S.TO instruction SM400 Always ON • Program example of CPU No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 4.3.2 Program examples for Universal model QCPU This section provides program examples for communicating data by auto refresh (using the multiple CPU high speed transmission area) between the CPU modules in the following system.
(b) Auto refresh setting Set auto refresh parameters. ( Project window Page 138, Section 6.1.2 (3)) [Parameter] [PLC Parameter] [Multiple CPU Setting] High Speed Transmission Area Setting" Setting of CPU No.1 94 Setting of CPU No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM (2) Program examples (a) Sending bit data and word data from CPU No.1 to CPU No.2 • Devices used in CPU modules Device used in CPU No.1 M0 D0 and D1 Send data from CPU No.1 to CPU No.2 Device used in CPU No.2 M0 D0 and D1 D100 - Send data from CPU No.1 to CPU No.2 Storage device for data received from CPU No.1 YE0 Data reception flag (for data from CPU No.1) SM400 Always ON 4 • Program example of CPU No.1 CPU No.1 send data (bit) Send command CPU No.
(b) Continuously sending data from CPU No.1 to CPU No.2 • Devices used in CPU modules Device used in CPU No.1 M40 Send data from CPU No.2 to CPU No.1 D10 to D18 D81 to D88 SM400 Send data from CPU No.1 to CPU No.2 Storage device of send data to CPU No.2 Device used in CPU No.2 M40 D10 to D18 Send data from CPU No.2 to CPU No.1 Send data from CPU No.1 to CPU No.2 D121 to Storage device for data received from CPU D128 No.1 Always ON - For handshake between CPU No.1 and No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM (c) Continuously reading/writing data between CPU No.1 and CPU No.2 using the user setting area in the multiple CPU high speed transmission area Data can be read/write between CPU modules using the user setting area in the CPU shared memory. The same number of points must be set for CPU No.1 and CPU No.2 in the auto refresh setting. Setting of CPU No.1 Setting of CPU No.2 4 The user setting area will be 3E0\G10000 and later for CPU No.
• Devices used in CPU modules Device used in CPU No.1 M31 Send data from CPU No.1 to CPU No.2 M63 D100 to D149 Device used in CPU No.2 M31 Send data from CPU No.1 to CPU No.2 Send data from CPU No.2 to CPU No.1 M63 Send data from CPU No.2 to CPU No.1 Storage device for data received from CPU D200 to No.2 D249 - SM400 Storage device of send data to CPU No.1 Always ON • Program example of CPU No.2 Always ON Write head data CPU No.2 write flag Write final data Write head data CPU No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 4.4 Clock Data This section describes clock data of CPU modules and intelligent function modules. 4.4.1 Clock data of CPU modules Set clock data to CPU No.1 in the multiple CPU system using the programming tool. [Online] [Set Clock] 4 The clock data settings for CPU No.2 to No.4 differ depending on the CPU module used. CPU module Setting of CPU No.2 to No.4 • Universal model QCPU Clock data do not need to be set. The clock data of CPU No.
4.4.2 Clock data of intelligent function modules When an error has occurred, some intelligent function modules store the code and time (clock data read from the QCPU) corresponding to the error into the buffer memory. Those modules store the clock data of CPU No.1 as the error time regardless of whether the modules are controlled by CPU No.1 or not.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM 4.5 Resetting a Multiple CPU System In a multiple CPU system, resetting the QCPU used as CPU No.1 resets all the modules (CPU modules, I/O modules, and intelligent function modules) in the system. (1) If a stop error exists any of the CPU modules in the multiple CPU system Reset CPU No.1 or power off and on the multiple CPU system. The system cannot be restored by resetting any CPU module other than CPU No.1.
4.6 System Operation When a Stop Error Occurs The multiple CPU system operation differs depending on the CPU module where a stop error has occurred. (1) When a stop error has occurred in CPU No.1 "MULTI CPU DOWN" (error code: 7000) occurs in all the other CPU modules and the operation of the multiple CPU system stops. (2) When a stop error has occurred in a CPU module other than CPU No.
CHAPTER 4 STARTING UP MULTIPLE CPU SYSTEM If a stop error occurs, "MULTI CPU DOWN" (error code: 7000) will occur in the CPU module where the stop error has been detected. Depending on the timing of error detection, "MULTI CPU DOWN" may be detected in another CPU module due to secondary-occurred "MULTI CPU DOWN". For example, if a stop error occurs in CPU No.2, the operation of CPU No.3 stops. Depending on the timing of error detection, the operation of CPU No.1 may stop due to the stop error of CPU No.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES This chapter describes the access between CPU modules and other modules (I/O modules and intelligent function modules). 5.1 Access to Controlled Modules In a multiple CPU system, CPU modules access I/O modules and intelligent function modules in the same way as in a single CPU system. (CPU modules refresh input (X) and output (Y) data, and read/write data from/to the buffer memory of intelligent function modules.) 5.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5.2.1 Loading input (X) data Data in the input (X) of input modules and intelligent function modules controlled by other CPU modules can be loaded in accordance with the "I/O Sharing When Using Multiple CPUs" setting in PLC parameter ("Multiple CPU Setting"). I/O Sharing When Using Multiple CPUs All CPUs Can Read All Inputs: Input data can be loaded from the modules controlled by other CPU modules.
(a) Modules that can load input (X) data Data in the input (X) can be loaded from the following modules mounted on the main base unit or extension base unit.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5.2.2 Loading output (Y) data Data in the output (Y) of output modules and intelligent function modules controlled by other CPU modules can be loaded in accordance with the "I/O Sharing When Using Multiple CPUs" setting in PLC parameter ("Multiple CPU Setting"). I/O Sharing When Using Multiple CPUs All CPUs Can Read All Outputs: Output data can be loaded from the modules controlled by other CPU modules.
(a) Modules that can load output (Y) data Data in the output (Y) can be loaded from the following modules mounted on the main base unit or extension base unit.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5.2.3 Output to output modules and intelligent function modules The on/off data cannot be output to non-controlled modules. If the output status of the output module or intelligent function module controlled by other CPU modules is turned on/off by the program, the corresponding output status changes only within the CPU module. (The on/off data is not output to the corresponding output module or intelligent function module.
5.2.4 Access to the intelligent function module buffer memory Data in the buffer memory of intelligent function modules controlled by other CPU modules can be read regardless of the "I/O Sharing When Using Multiple CPUs" setting in PLC parameter ("Multiple CPU Setting"). (1) Reading data from the buffer memory Data can be read from the buffer memory of intelligent function modules controlled by other CPU modules in the same way as in a single CPU system.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5.2.5 Access using the link direct device Only the control CPU can execute instructions using the link direct device to access I/O modules and intelligent function modules. The link direct device cannot be used to access modules controlled by other CPU modules. If an instruction using the link direct device is executed to access a module controlled by another CPU module , "OPERATION ERROR" (error code: 4102) occurs.
5.3 Access From a Programming Tool This section describes access from a programming tool to modules in a multiple CPU system. (1) Access to QCPUs A programming tool can read/write parameters and programs from/to the QCPU connected as well as monitor and test the entire system. To access another QCPU via the QCPU connected, specify the target CPU No. in "Multiple CPU Setting" on the "Transfer Setup" window.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES (2) Access to controlled and non-controlled modules A programming tool can access modules both controlled and not controlled by the QCPU connected. The programming tool connected to one QCPU can access all the modules controlled by any QCPU in the multiple CPU system. The programming tool can also access QCPUs on other stations in the same network such as CC-Link IE, MELSECNET/H, or Ethernet.
(3) Access from the programming tool connected to another station The programming tool connected to another station in the same network can access all the QCPUs in the multiple CPU system. Ex. Over MELSECNET/H PLC to PLC network Station No. 2 (normal station) Station No. 3 (normal station) Control CPU setting MELSECNET/H PLC to PLC network Station No.
CHAPTER 5 ACCESS BETWEEN CPU MODULES AND OTHER MODULES 5.4 Accessible QCPUs when GOT is connected For the connected GOT, QCPUs that can be accessed differ depending on the connection method. ( Manual for the GOT used) 5 5.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES This chapter describes data communications among CPU modules in a multiple CPU system. (1) Communication methods The following table lists the communication methods available among CPU modules. Item Description Communications using the CPU shared Data communications is performed among CPU modules using memory the internal memory of each CPU module.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (2) Communications among CPU modules Communications availability differs depending on the CPU modules used as the communication source and target.
6.1 Communications Using the CPU Shared Memory This section describes data communications among CPU modules in a multiple CPU system using the CPU shared memory. (1) CPU shared memory The CPU shared memory is a data storage area in a CPU module and used to read/write data among CPU modules in a multiple CPU system. The CPU shared memory consists of the areas listed below.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (2) CPU shared memory configuration and availability of data communications by programs The following shows the CPU shared memory configuration and the availability of data communications by programs using the CPU shared memory.
• Universal model QCPU Host CPU CPU shared memory (0H) to (1FFH) (200H) G0 to G511 G512 to (7FFH) (800H) to G2047 G2048 to to Write Other CPU Read Write Read Host CPU operation information area System area Auto refresh area User setting area (FFFH) G4095 (1000H) G4096 to to (270FH) G9999 (2710H) G10000 to to Max.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (3) Host CPU operation information area (a) Information stored The following information about the host CPU module is stored in this area.*1 In a single CPU system, all the values are set to 0. Shared memory Name Description*2 Meaning address Corresponding special register This is an area to check whether information is stored in the 0H Information Information existence existence flag host CPU operation information area (1H to 1FH).
6.1.1 Communications by auto refresh (using the auto refresh area) This section describes data communications by auto refresh using the auto refresh area in the CPU shared memory. Data communications by auto refresh can also be performed using the auto refresh area in the multiple CPU high speed transmission area. Use of the multiple CPU high speed transmission area can reduce the increase in scan time. Some conditions apply to using the area. ( Page 135, Section 6.1.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (b) Executing auto refresh Auto refresh is executed when the CPU modules are in RUN, STOP, or PAUSE status. Auto refresh cannot be executed when a stop error has occurred in any of the CPU modules. If a stop error occurs in a CPU module, the other modules will hold the data prior to the stop error. In the figure on Page 122, Section 6.1.1 (1) (a), for example, if the status of B20 is on when a stop error occurs in CPU No.2, the B20 in CPU No.1 will remain on.
(a) "Change Screens" Up to four auto refresh ranges can be set. Set and switch the ranges in this parameter. With different settings, on/off data in bit devices and other data in word devices can be auto-refreshed separately. (b) "CPU Specific Send Range" Set the number of points in the CPU shared memory in increments of two points (two words). (If a bit device is specified in "PLC Side Device", two points equal to 32 points.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES Ex. To refresh data in B0 to B1F (32 points) of CPU No.1 and B20 to B3F (32 points) of CPU No.2, set "2" in "Points" because the link relay (B) is a bit device. When the number of points in the CPU shared memory is set to "2" and a bit device is specified for "PLC Side Device", 32 points of data can be refreshed. Since the number of points for CPU No.3 and No.4 is set to "0", data are not refreshed. [Auto refresh processing] CPU No.1 CPU No.
(c) "PLC Side Device" Set auto refresh target devices. The following devices can be set. Device Restriction Data register (D), Link register (W), – File register (R, ZR) Link relay (B), Internal relay (M), Specify 0 or multiples of 16 for the start number. Output (Y) There are two auto refresh device range setting methods.*1 • Setting device ranges sequentially from the start device number of CPU No.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES • Different devices can be set for Setting 1 to 4. The same device can also be set as long as the device ranges for Setting 1 to 4 are not overlapped. Setting 1: The link relay (B) is specified. Different devices can be set for Setting 1 to 4. Setting 2: The link register (W) is specified. The same device can also be set for Setting 1 to 4. Make sure the device ranges are not overlapped.
• Devices of Setting 1 to 4 can be set independently for each CPU module. For example, while the link relay (B) is set for CPU No.1, the internal relay (M) can be set for CPU No.2. Refresh setting of CPU No.1 The same device is set for CPU No.1 and No.2. The same number of points is set for all the CPU modules. Refresh setting of CPU No.2 Different devices are set for CPU No.1 and No.2. [Auto refresh processing] CPU No.1 CPU No.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES Ex. Operations when executing auto refresh of four ranges (Setting 1: link relay (B), Setting 2: link register (W), Setting 3: data register (D), Setting 4: internal relay (M)) CPU No.1 send data (No.3) CPU No.4 Maximum 2K words CPU No.4 send data (No.1) CPU No.4 send data (No.2) CPU No.4 send data (No.3) CPU No.4 send data (No.4) g. sin es D . Maximum 2K words CPU No.1 send data (No.4) pro wr itt e n ce du ss ing rin g CPU No.1 send data (No.
• There are following advantages if device ranges are set for each CPU module freely. • The order of the send ranges can be changed for each CPU module. • Since unnecessary refresh can set to be disabled, the system scan time will be reduced. Ex. Changing the order of send ranges for each CPU module The following is a setting example of auto refresh between the High Performance model QCPU used as CPU No.1 and the Motion CPU used as CPU No.2.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES Ex. Disabling unnecessary refresh Unnecessary refresh can set to be disabled by not setting the device ranges of other CPU modules where auto refresh is not required. The device ranges of the host CPU module must be set. The following is a setting example of auto refresh between CPU No.1 and each of other CPU modules (CPU No.2 to No.4). Setting of CPU No.1 Setting of CPU No.2 6 Setting of CPU No.3 CPU No.1 Setting of CPU No.4 CPU No.3 CPU No.
(3) Precautions (a) Local device setting (except the Basic model QCPU) Device ranges set for the auto refresh target cannot be set as local devices. If set, the refresh data will not be updated. (b) Using the same file name as that of the program in the file register (except the Basic model QCPU) Do not set the file register of each program as an auto refresh target device. If set, data are automatically refreshed to the file register corresponding to the scan execution type program executed last.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES Ex. Auto refresh between a QCPU and a Motion CPU The following are the program examples for the Basic model QCPU and Motion CPU when PLC parameters ("Communication Area Setting (Refresh Setting)" of "Multiple CPU Setting") are set as shown below. [Parameter setting] Setting No. ("Change CPU Specific Send Range PLC Screens") Setting 1 Setting 2 PLC No.1 Points Start End Start End 2 00C0 00C1 M0 M31 PLC No.2 2 0800 0801 M32 M63 PLC No.
Ex. Auto refresh between QCPUs The following are the program examples for the High Performance model QCPUs when PLC parameters ("Communication Area Setting (Refresh Setting)" of "Multiple CPU Setting") are set as shown below. [Parameter setting] Setting No. CPU Specific Send Range ("Change PLC Points Screens") Setting 1 Start PLC Side Device End Start End PLC No.1 1024 0000 03FF D0 D1023 PLC No.2 1024 0000 03FF D1024 D2047 Use D0.0 as an interlock device of CPU No.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES 6.1.2 Communications by auto refresh (using the multiple CPU high speed transmission area) This section describes data communications by auto refresh using the multiple CPU high speed transmission area in the CPU shared memory. (1) Conditions for data communications Data communications by auto refresh using the multiple CPU high speed transmission area can be performed only when the following conditions are all met.
(2) Communications by auto refresh (a) Overview Auto refresh communicates data using the auto refresh area of the multiple CPU high speed transmission area in the CPU shared memory. The data written to the auto refresh area of the multiple CPU high speed transmission area is sent to that of the other CPU modules at regular intervals (multiple CPU high speed transmission cycles).
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (b) Memory configuration of the multiple CPU high speed transmission area The following shows the memory configuration of the multiple CPU high speed transmission area. For the CPU shared memory configuration, refer to Page 118, Section 6.1. 2) CPU No.1 send area 3) User setting area 2) CPU No.2 send area 4) Auto refresh area 1) Multiple CPU high speed transmission area 2) CPU No.3 send area 2) CPU No.4 send area No.
(3) Multiple CPU high speed transmission area settings To perform auto refresh of data in the CPU shared memory, set the ranges (number of points) to be sent by each CPU module ("CPU Specific Send Range") and the devices for storing data ("Auto Refresh Setting") in PLC parameter ("Multiple CPU Setting").
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES To check the auto refresh directions, specify the CPU number in "Host Station" of PLC parameter ("Multiple CPU Setting"). • Multiple CPU Setting window • Auto Refresh Setting window • Multiple CPU High Speed Transmission Area Assignment Confirmation window Multiple CPU High Speed Transmission Area Assignment Confirmation window Multiple CPU Setting window Click the Assignment Confirmation button. 6 Click the Refresh button.
(a) "CPU Specific Send Range" Set the number of points for the multiple CPU high speed transmission area used in each CPU module. Item Description CPU Specific Send Range Setting/displayed range Set the number of send data points for each CPU module.*1 Setting range: 0 to 14K points*2 If a CPU module not listed on Page 135, Section 6.1.2 (1) is Setting unit: 1K points used, set "0" point to the corresponding CPU module.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES The number of points for the system area used by dedicated instructions can be changed to 2K points by checking the "Advanced Setting" checkbox. This increases the number of dedicated instructions can be executed simultaneously in one scan. 6 CPU Specific Send Range Description Set the number of send data points for each CPU module.
(b) "Auto Refresh Setting" Set auto refresh target devices to communicate data by auto refresh using the multiple CPU high speed transmission area. Up to 32 ranges can be set for each CPU module. Item Points Description Setting range Set the number of points for data communications • Setting range: 2 to 14336 points*1 in increment of 2 points (word units). • Setting unit: 2 points*2 • Device that can send data*3 Specify the auto refresh target device.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (4) Auto refresh setting examples and data flow The data flow among CPU modules will be as follows in a multiple CPU system containing three CPU modules with two auto refresh range settings. (a) Auto refresh setting examples The following are the examples of auto refresh settings to explain the data flow. (a) Send device setting (CPU No.1) (b) Receive device setting (CPU No.1) (c) Receive device setting (CPU No.1) 6 (f) Receive device setting (CPU No.
(b) Flow of data sent from CPU No.1 to other CPU modules Refer to those related to the data communications of CPU No.1 ((a) to (c)) among the auto refresh setting examples on Page 143, Section 6.1.2 (4) (a). (a) Send device setting (CPU No.1) (b) Receive device setting (CPU No.1) (c) Receive device setting (CPU No.1) (1) Auto refresh setting of CPU No.1 (2) Auto refresh setting of CPU No.2 (3) Auto refresh setting of CPU No.3
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (c) Flow of data sent from CPU No.2 to other CPU modules Refer to those related to the data communications of CPU No.2 ((d) to (f)) among the auto refresh setting examples on Page 143, Section 6.1.2 (4) (a). (d) Receive device setting (CPU No.2) (e) Send device setting (CPU No.2) (f) Receive device setting (CPU No.2) (1) Auto refresh setting of CPU No.1 (2) Auto refresh setting of CPU No.2 (3) Auto refresh setting of CPU No.
(d) Flow of data sent from CPU No.3 to other CPU modules Refer to those related to the data communications of CPU No.3 ((g) to (i)) among the auto refresh setting examples on Page 143, Section 6.1.2 (4) (a). (g) Receive device setting (CPU No.3) (h) Receive device setting (CPU No.3) (i) Send device setting (CPU No.3) (1) Auto refresh setting of CPU No.1 (2) Auto refresh setting of CPU No.2 (3) Auto refresh setting of CPU No.3
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES If "Start" and "End" fields are left blank in "Auto Refresh Setting", auto refresh is not performed. (Only the receive area can be left blank.) Ex. When the auto refresh setting of CPU No.2 is left blank in "Flow of data sent from CPU No.3 to other CPU modules" described on Page 146, Section 6.1.2 (4) (d) CPU No.2 does not auto-refresh the data received from CPU No.3 to W40 to W5F. (g) Receive device setting (CPU No.3) (h) Receive device setting (CPU No.
(5) Precautions (a) Local device setting Device ranges set for the auto refresh target cannot be set as local devices. If set, the refresh data will not be updated. (b) Using the same file name as that of the program in the file register Do not set the file register of each program as an auto refresh target device. If set, data are automatically refreshed to the file register corresponding to the scan execution type program executed last.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES Ex. Program example for providing an interlock between CPU No.1 and No.2 [Parameter setting] CPU No.1 auto refresh setting PLC PLC No.1 PLC No.2 CPU Specific Send Setting No. Range Points Start End CPU No.2 auto refresh setting Auto Refresh Start 1 2 0 1 M0 M31 10 2 11 D0 D9 2 0 1 M32 PLC M63 PLC No.1 PLC No.2 CPU Specific Send Setting Range No.
6.1.3 Communications by programs using the CPU shared memory This section describes data communications by programs using the CPU shared memory. The QCPU in the multiple CPU system communicates data by executing programs in the following cases.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (2) Instructions used to read/write data from/to the CPU shared memory The QCPU in the multiple CPU system communicates data with other CPU modules by executing read/write instructions. The following read/write instructions can be used. Item Description • Instructions using the cyclic transmission area device (U3En\G)*1 Write instruction*3*4 • TO/DTO instructions (except for High Performance model QCPUs and Process CPUs) • S.
(4) Overview (when the user setting area is used) The data written to the CPU shared memory in the host CPU module by a write instruction can be read by other CPU modules by a read instruction. Unlike the auto refresh using the CPU shared memory, the up-to-date data at the time of an instruction execution can be read directly. The following shows the operations when data written to the CPU shared memory of CPU No.1 by a write instruction is read by CPU No.2 by a read instruction. CPU No.1 CPU No.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (5) Overview (when the user setting area in the multiple CPU high speed communication area is used) The data written to the multiple CPU high speed transmission area of the host CPU module by a write instruction is sent to other CPU modules at regular intervals. Other CPU modules read the receive data by a read instruction. Unlike the auto refresh using the CPU shared memory, the up-to-date data at the time of an instruction execution can be read directly.
(6) Parameter settings To use the user setting area in the multiple CPU high speed transmission area, set the ranges (number of points) to be sent by each CPU module ("CPU Specific Send Range") in PLC parameter ("Multiple CPU Setting"). For setting details, refer to Page 135, Section 6.1.2. (7) Assurance of send data Old data and new data may coexist (data inconsistency) in each CPU module due to the timing of reading data in the host CPU module and writing/sending data in other CPU modules.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (b) Preventing inconsistency of data exceeding 32 bits • When the user setting area is used The read instruction reads data in order starting from the start address to the end address of the user setting area. On the other hand, the write instruction writes data in order starting from the end address to the start address of the user setting area. To prevent data inconsistency, set an interlock device at the start of data to be communicated. Ex.
• When the user setting area in the multiple CPU high speed transmission area is used The read instruction reads data in order of those were written to the user setting area. To prevent data inconsistency, use the device written after the transfer data as an interlock regardless of the device type and address. Ex. Program example for providing an interlock between CPU No.1 and No.2 Program example (CPU No.1, sending side) Program example (CPU No.2, receiving side) 3) Write command U3E0\ M0 G10010.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (8) Precautions (a) Start I/O numbers of CPU modules Set the following start I/O numbers to each CPU module for the read/write instructions. CPU No. CPU No.1 CPU No.2 CPU No.3 CPU No.4 Start I/O number 3E0H 3E1H 3E2H 3E3H (b) Writing data to the CPU shared memory Do not write data to the following areas in the CPU shared memory. ( Page 118, Section 6.
(g) Writing data to the CPU shared memory of its own • Basic model QCPU Data can be written with any write instruction. • High Performance model QCPU or Process CPU Data can be written with the S.TO instruction. However, data cannot be written with instructions using the cyclic transmission area device (U3En\G). If used, "SP.UNIT ERROR" (error code: 2114) will occur. • Universal model QCPU Data can be written with any write instruction.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES 6.1.4 Communications among CPU modules when an error is detected This section describes the operations performed when an error is detected during data communications among CPU modules using the CPU shared memory. (1) Operation when improper data is received If a CPU module receives improper data during data communications among CPU modules due to noise or failure, the module discards the receive data.
6.2 Control Directions from QCPU to Motion CPU Control directions can be issued from the QCPU to Motion CPU in a multiple CPU system by using the following motion dedicated instructions. (Control directions cannot be issued from the Motion CPU to another Motion CPU.) For details on the motion dedicated instructions and their availabilities, refer to the manual for the motion CPU used.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES Remark C Controller modules have functions that direct control to Motion CPUs. ( Manual for the C Controller module used) Ex. S.SFCS instruction The motion SFC programs in a Motion CPU can be started up from the QCPU. Motion CPU QCPU Start request Motion SFC S.SFCS instruction 6 One QCPU can execute up to total of 32 motion dedicated instructions and multiple CPU transmission dedicated instructions (except the S(P).GINT instruction) simultaneously.
6.3 Communications Among CPU Modules By Dedicated Instructions 6.3.1 Reading/writing device data from/to Motion CPU The QCPU can read/write device data from/to the Motion CPU by executing the multiple CPU transmission dedicated instructions and multiple CPU high-speed transmission dedicated instructions. (The Motion CPU cannot read/write device data from/to other CPU modules including the Motion CPU.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (2) Multiple CPU high-speed transmission dedicated instructions The Universal model QCPU reads/writes device data from/to the Q172DCPU(-S1), Q173DCPU(-S1), Q172DSCPU, and Q173DSCPU by executing the multiple CPU high-speed transmission dedicated instructions listed below. : Available, ×: Not available QCPU Basic model QCPU, Instruction Description High Performance model QCPU, Process CPU D.DDWR, Writes device data in the host CPU module DP.
6.3.2 Starting interrupt programs from QCPU to C Controller module/PC CPU module The QCPU can start interrupt programs to the C controller unit/PC CPU module by executing the multiple CPU transmission dedicated instructions and multiple CPU high-speed transmission dedicated instructions. Instruction Description S.GINT, Requests startup of interrupt programs in other CPU modules. SP.GINT For the availabilities, refer to the following. D.GINT, Manual for the C Controller module used DP.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES 6.3.3 Reading/writing device data between QCPUs The Universal model QCPU can read/write device data from/to another Universal model QCPU by executing the multiple CPU high-speed transmission dedicated instructions listed below. : Available, ×: Not available QCPU Basic model QCPU, *2 Instruction Description High Performance model QCPU, Process CPU D.DDRD, Loads device data in other CPU modules to DP.DDRD the devices in the host CPU module. D.
6.4 Multiple CPU Synchronous Interrupt This function executes interrupt programs (multiple CPU synchronous interrupt programs) at the start timing of each multiple CPU high speed transmission cycle. The function enables data communications among CPU modules in synchronization with the multiple CPU high speed transmission cycles.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (3) Applicable CPU modules The multiple CPU synchronous interrupt function can be executed when any of the following CPU modules is used.
6.5 Multiple CPU synchronous startup This function synchronizes the startups of CPU No.1 to No.4. Since the function monitors the startup of each CPU module, an interlock program normally used to check the startup of another CPU module before accessing is no longer required. This function, however, synchronizes the startups with the slowest one. As a result, the startup of the system may be slow.
CHAPTER 6 COMMUNICATIONS AMONG CPU MODULES (3) Precautions If a CPU module that does not support this function is used, uncheck the checkbox of the corresponding CPU number in PLC parameter. Ex. When High Performance model QCPUs are used as CPU No.2 and No.4 Uncheck the checkboxes of CPU No.2 and No.4. Remark If this function is not used (each CPU module starts up asynchronously), create a program to check the startup of each CPU module using SM220 (CPU No.1 preparation completed) to SM223 (CPU No.
APPENDICES Appendix 1 Parameters for a Multiple CPU System (1) Parameters required For a multiple CPU system, the following PLC parameters shall be set additionally to those for a single CPU system. • "Multiple CPU Setting" • "Control PLC" setting in "Detailed Setting" of "I/O Assignment" The same PLC parameters must be set to all the CPU modules used in a multiple CPU system, except some parameters. ( Page 172, Appendix 1.
APPENDICES (3) Checking the multiple In a multiple CPU system, whether the same multiple CPU parameters are set to all the CPU modules is checked at the following timing. • When a multiple CPU system is powered on • When CPU No.1 is reset • When the operating status of the CPU modules are switched from STOP to RUN • When any parameter is changed This check is called a consistency check. (For the parameters to be checked, refer to the items marked and in the Consistency column on Page 172, Appendix 1.1.
Appendix 1.1 List of parameters (1) For Basic model QCPU, High Performance model QCPU, and Process CPU The following table lists PLC parameters need to be set for a Basic model QCPU, High Performance QCPU, or Process CPU.
APPENDICES (2) For Universal model QCPU The following table lists PLC parameters need to be set for a Universal model QCPU.
*1 : Item that must be set in a multiple CPU system (A system does not operate without setting.
APPENDICES Appendix 2 Comparison with a Single CPU System This section describes comparison between a single CPU system and multiple CPU system. (1) When a Basic model QCPU is used Item Single CPU system Multiple CPU system Maximum number of 4 levels extension levels Maximum number of 25 - (Number of CPU modules)*1*2 24 mountable I/O modules Main base unit*3 Q3B, Q3SB, Q3RB, Q3DB System Extension cable QC05B, QC06B, QC12B, QC30B, QC50B, QC100B Within 13.
Item Number of CPU modules and mounting position I/O number assignment Single CPU system Multiple CPU system Only 1 module in the CPU slot 3 modules in the CPU slot to slot 1 Slot 0 is 00H. Concept Reference Page 60, Section 3.3.2 A slot on the right of the rightmost Page 27, CPU module is 00H.*1 Section 2.
APPENDICES Item Single CPU system Multiple CPU system Reference Basic model QCPU = 320 points, Motion CPU = 2048 points, Communications by auto refresh using the CPU Not supported shared memory C Controller module = 2048 points, Page 122, PC CPU module = 2048 points, Section 6.1.1 Total of all CPU modules: 4416 points Data communications is performed Communications by Communications programs using the CPU among CPU shared memory by using the TO, S.
(2) When a High Performance model QCPU is used Item Single CPU system Multiple CPU system Maximum number of 7 levels extension levels Maximum number of Main base unit*3 Extension base unit*3*6 configuration Extension cable 65- (Number of CPU modules)*1*2 64 mountable I/O modules System Q3B, Q3SB, Q3RB, Q3DB QA1S6ADP+A1S5B/A1S6B, QA6B, QA6ADP+A5B/A6B Within 13.
APPENDICES Item Access from CPU module(s) to other modules Access from GOTs Access with instructions using the link direct device Single CPU system Multiple CPU system Relations between CPU modules All modules can be controlled. and other modules must be set in "Control PLC" of PLC parameter. Accessible Accessible Reference Page 104, CHAPTER 5 A GOT can access a High Manual for Performance model QCPU of the the GOT specified CPU No. used Only control CPU is accessible. Page 104, Section 5.
Item Single CPU system Multiple CPU system Reference • Writing data during RUN • Time reserved for communication Scan time Factors that increase scan time • Writing data during RUN • Time reserved for communication processing processing • Refresh processing among CPU modules in the multiple CPU Page 192, Appendix 4 system • Waiting time • Number of CPU modules ("Multiple CPU Setting") • Control PLC setting ("I/O Assignment") • Out-of-group I/O setting ("Multiple CPU Setting") Parameter Parameters
APPENDICES (3) When a Process CPU is used. Item Single CPU system Multiple CPU system Maximum number of 7 levels extension levels Maximum number of Main base unit*3 configuration Extension base unit 65 - (Number of CPU modules)*1*2 64 mountable I/O modules System Q3B, Q3RB, Q3DB *3 Extension cable Q5B, Q6B, Q6RB Section 3.2.1 Within 13.
Item Access from CPU module(s) to other modules Access from GOTs Access with instructions using the link direct device Single CPU system Multiple CPU system Relations between CPU modules All modules can be controlled. and other modules must be set in "Control PLC" of PLC parameter. Accessible Accessible A GOT can access a Process CPU of the specified CPU No. Only control CPU is accessible. Reference Page 104, CHAPTER 5 Manual for the GOT used Page 104, Section 5.
APPENDICES Item Single CPU system Multiple CPU system Reference • Writing data during RUN • Time reserved for communication Scan time Factors that increase scan time • Writing data during RUN processing • Time reserved for • Refresh processing among CPU communication processing modules in a multiple CPU Page 192, Appendix 4 system • Waiting time • Number of CPU modules ("Multiple CPU Setting") • Control PLC setting ("I/O Assignment") • Out-of-group I/O setting ("Multiple CPU Setting") Paramete
(4) When a Universal model QCPU is used Item Single CPU system Maximum number of Multiple CPU system Reference 7 levels (Q00UCPU, Q01UCPU, or Q02UCPU: 4 levels) extension levels 65 - (Number of CPU modules)*1*2 Maximum number of mountable I/O modules 64 (Q00UCPU or Q01UCPU: (Q00UCPU or Q01UCPU: 24, 25 - (Number of CPU modules), Q02CPU: 36) Q02UCPU: 37 - (Number of CPU modules)) System Main base unit*3 configuration Extension base unit*3*4*5 Extension cable Q3B, Q3SB, Q3RB, Q3DB QA1S6ADP+A1
APPENDICES Item Number of CPU modules and mounting position I/O number assignment Single CPU system Only 1 module in the CPU slot Slot 0 is 00H. Concept Multiple CPU system 4 modules in the CPU slot to slot 2 Reference Page 60, Section 3.3.2 A slot on the right of the rightmost Page 27, CPU module is 00H.*1 Section 2.
Item Single CPU system Multiple CPU system Reference The entire system is reset by Operation when a CPU module is reset. The entire system is reset by resetting the Process CPU (CPU resetting the Universal model No.1). QCPU. (Resetting CPU No.2 to No.4 Page 102, Section 4.6 individually is not allowed.) If a stop error has occurred in the Process CPU (CPU No.1), the system stops.
APPENDICES Item Single CPU system Multiple CPU system Reference • Number of CPU modules ("Multiple CPU Setting") • Control PLC setting ("I/O Assignment") • Out-of-group I/O setting ("Multiple CPU Setting") • Operation mode when a stop error has occurred in a CPU module ("Multiple CPU Setting") Parameters added for Parameter multiple CPU systems Not supported • Multiple CPU synchronous startup ("Multiple CPU Setting") • Multiple CPU high speed transmission area setting Page 80, Section 4.2.
Appendix 3 Precautions for Using AnS/A Series Modules (1) Multiple CPU system configuration for using AnS/A series modules AnS/A series modules can be used in a multiple CPU system configuration where all of the following conditions are met. (a) CPU No.1 The following QCPU must be used. • Universal model QCPU with a serial number (first five digits) of "13102" or later • High Performance model QCPU (b) CPU No.2 to No.4 The following CPU module must be used.
APPENDICES Ex. When CPU No.2 is set as a control CPU Set CPU No.2 as the control CPU of all slots where AnS/A series modules are mounted. If a different CPU No. is set as a control CPU for any of the AnS/A series modules, "PARAMETER ERROR" (error code: 3009) will occur and the multiple CPU system will not start. A control CPU is set for each slot.
(3) Access ranges of controlled and non-controlled modules Access ranges of the controlled and non-controlled modules in a multiple CPU system is shown below.
APPENDICES (4) Precautions (a) Accessible device ranges When the following AnS/A series modules are used, accessible device ranges are restricted.
Appendix 4 Appendix 4.1 Processing Time Concept of scan time The concept of scan time in a multiple CPU system is the same as that in a single CPU system. This section describes how to calculate the processing time when a multiple CPU system is configured. (1) I/O refresh time For the calculating formula of I/O refresh time, refer to the following.
APPENDICES (3) Common processing time In a multiple CPU system, the common processing time increases as shown below. QCPU Q00CPU, Q01CPU Q02CPU Common processing time (0.05 to 0.13) × (Number of other CPU modules) ms 0.02ms Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU Q02PHCPU, Q06PHCPU, Q12PHCPU, 0.03ms Q25PHCPU Q00UCPU, Q01UCPU, Q02UCPU, Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, 0.
Appendix 4.2 Factors that increase scan time The processing time in a multiple CPU system increases from that in a single CPU system when the following functions are used. When any of the following functions is used, add the time values described in this section to the values calculated on Page 192, Appendix 4.1.
APPENDICES • For the High Performance model QCPU and Process CPU (Auto refresh time) = (N1 + (Number of receive word points) + (N3 + (Number of send word points) N2) (Number of other CPU modules) N4) (µs) The number of receive word points is the sum of the number of word points sent by other CPU modules. Ex. When the number of CPU modules is 4 and the host CPU is CPU No.1 The number of receive word points will be the sum of the number of word points sent by CPU No.2 to No.4.
• For the Universal model QCPU (Auto refresh time) = (N1 + (Number of send word points) N2) + (N3 + (Number of other CPU modules) N4 + (Number of receive word points) N5) (µs) The number of receive word points is the sum of the number of word points sent by other CPU modules. Ex. When the number of CPU modules is 4 and the host CPU is CPU No.1 The number of receive word points will be the sum of the number of word points sent by CPU No.2 to No.4.
APPENDICES (c) When auto refresh is executed by another CPU module during auto refresh processing The auto refresh time increases by the time obtained by the following calculation. • For the Basic model QCPU (Extended time) = 4 (Number of receive word points) N6 (Number of other CPU modules) (µs) Use the following value for N6. N6 Basic model QCPU Q00CPU, Q01CPU System with a main base unit System including extension only base unit(s) 0.54µs 1.
(2) Refresh of CC-Link IE and MELSECNET/H (a) Refresh time of CC-Link IE and MELSECNET/H This is the time required for executing refresh between a QCPU and a CC-Link IE module or MELSECNET/H module. For each refresh time, refer to the following.
APPENDICES (3) Auto refresh of CC-Link (a) Auto refresh time of CC-Link This is the time required for executing refresh between a QCPU and a CC-Link master/local module. For details, refer to the following.
Appendix 4.3 Reducing processing time (1) Multiple CPU system processing CPU modules access I/O modules and intelligent function modules through a bus (base unit pattern or extension cable). Note that only one CPU module can use the bus at a time. If more than one CPU module attempts to use the bus simultaneously, the CPU module attempted access later is placed in Standby status until the processing of the first CPU module is completed.
INDEX Comparison with a single CPU system . . . . . . . . . 175 Concept of multiple CPU system . . . . . . . . . . . . . . 24 Concept of scan time . . . . . . . . . . . . . . . . . . . . . 192 Control CPU (Control PLC) . . . . . . . . . . . . . . . 17,84 Control directions from QCPU to Motion CPU . . . . 160 Controlled module . . . . . . . . . . . . . . . . . . . . . . . . 17 CPU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CPU module combinations and mounting positions A A series . .
H N High Performance model QCPU . . . . . . . . . . . . . . 15 High-speed Universal model QCPU . . . . . . . . . . . . 15 Host CPU operation information area . . . . . . . 118,121 Host station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 How to check the host CPU number . . . . . . . . . . . . 26 How to check the multiple CPU parameter settings No. of PLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Non-controlled module . . . . . . . . . . . . . . . . . . . . .
R V Reading data from the buffer memory . . . . . . . . . . 110 Reading/writing device data from/to Motion CPU . . 162 Reducing processing time . . . . . . . . . . . . . . . . . . 200 Redundant power extension base unit . . . . . . . . . . . 16 Redundant power main base unit . . . . . . . . . . . . . . 16 Redundant power supply base unit . . . . . . . . . . . . . 16 Redundant power supply module . . . . . . . . . . . . . . 17 Refresh time of CC-Link IE and MELSECNET/H Version . . . . . . . . . . . . . . .
REVISIONS *The manual number is given on the bottom left of the back cover. Print date Manual number January 2004 SH(NA)-080485ENG-A May 2005 SH(NA)-080485ENG-B Revision First edition Partial correction TERMS, Chapter 1, Section 1.1, 2.1, 2.3, 2.4, 3.1, 3.3.1, 3.3.2, 3.4.1, 3.4.2, 3.8, 3.9, 3.10, 4.1.1, 4.1.2, 4.1.3, 6.1, 6.1.1, 7.1, 8.1, 8.2.2, 8.2.3, 8.2.4, 8.3.1, 8.3.4, Appendix 1.1 August 2005 SH(NA)-080485ENG-C Partial correction TERMS, Section 2.
Print date Manual number December 2008 SH(NA)-080485ENG-H Revision Addition of Universal model QCPU and C Controller module models Model addition Q00UCPU, Q01UCPU, Q10UDHCPU, Q20UDHCPU, Q10UDEHCPU, Q20UDEHCPU, Q61P-D Partial correction MANUALS, TERMS, Chapter 1, Section 1.1, 1.3, 2.1.1, 2.1.2, 2.1.3, 2.3, 2.4, 3.1, 3.1.2, 3.1.3, 3.2, 3.3.2, 3.7, 3.9, 4.1.1, 4.1.2, 4.1.3, 4.1.4, 4.1.5, 4.3.1, 4.3.3, 4.5, 5.1, 5.2, 7.1, 8.1, 8.2.
Print date Manual number September 2013 SH(NA)-080485ENG-P Revision C Controller model addition Model addition Q24DHCCPU-LS Partial correction MANUALS, TERMS, Chapter 1, Section 3.1.1, 3.1.2, 3.1.3, 3.2.1, 3.2.2, 3.2.3, 3.3.1, 3.3.2, 3.4, 3.5, 4.2.2, 4.4.1, 4.6, Chapter 6, Section 6.1.1, 6.1.2, 6.1.3, 6.1.4, 6.5, Appendix 2, 3, 4.2 January 2014 SH(NA)-080485ENG-Q Partial correction Section 3.1.3, 3.5, 4.6 July 2014 SH(NA)-080485ENG-R Model addition QA1S6ADP Partial correction TERMS, Section 3.2.
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