SAFETY PRECAUTIONS (Always read these cautions before using the product) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
REVISIONS *The manual number is given on the bottom left of the back cover. Print Date *Manual Number Revision Dec., 2008 SH (NA)-080809ENG-A First edition Mar., 2009 SH (NA)-080809ENG-B Partial corrections Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25, 7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8 Jul.
INTRODUCTION This manual explains the common instructions required for programming of the QCPU. • The common instructions refer to all instructions except those dedicated to special function modules (such as AJ71QC24 and AJ71PT32-S3) and to AD57 models, as well as PID control instructions, SFC instructions and ST instructions.
CONTENTS SAFETY PRECAUTIONS ..................................................................................................................A - 1 REVISIONS .......................................................................................................................................A - 2 INTRODUCTION ...............................................................................................................................A - 3 CONTENTS ..........................................................
2.5.11 2.5.12 2.5.13 2.5.14 2.5.15 2.5.16 2.5.17 2.5.18 2.5.19 2.5.20 2.5.21 2.5.22 Character string processing instructions .................................................................... 2 - 43 Special function instructions ....................................................................................... 2 - 46 Data control instructions ............................................................................................. 2 - 49 Switching instructions ...................................
5.2.3 5.2.4 5.2.5 5.3 Output Instructions 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.4 5.6 5.7 Comparison Operation Instructions 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 A-6 6 - 1 to 6 - 168 6-2 BIN 16-bit data comparisons (=,<>,>,<=,<,>=) ............................................................. 6 - 2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) .............................................
6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P)) ................................................................................................. 6 - 50 6.2.11 Multiplication and division of floating decimal point data (Single precision) (E*(P),E/(P)) ....................................................................................................... 6 - 54 6.2.
6.6 Program Execution Control Instructions 6.6.1 6.6.2 6.7 6.8 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) .......... 6 - 133 Recovery from interrupt programs (IRET) ................................................................ 6 - 139 I/O Refresh Instructions 6.7.1 Logical operation instructions 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.2 7.3 7.4 7.5 A-8 7 - 46 7 - 59 Bit set and reset for word devices (BSET(P),BRST(P)) ..............................
7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14 7.5.15 7.6 Structure creation instructions 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.7 7.8.2 7.9 7 - 160 Reading 1-/2-word data from the intelligent function module (FROM(P),DFRO(P))........................................................................................ 7 - 160 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) .....................
7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data (BCDDA(P),DBCDDA(P))................................................................................. 7 - 189 7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data (DABIN(P),DDABIN(P)).................................................................................... 7 - 192 7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data (HABIN(P),DHABIN(P))..............................................................
7.12.25 Common logarithm operation on floating-point data (Single precision) (LOG10(P))....................................................................................................... 7 - 300 7.12.26 Common logarithm operation on floating-point data (Double precision) (LOG10D(P)) .................................................................................................... 7 - 302 7.12.27 Random number generation and series updates (RND(P),SRND(P)) ..................... 7 - 304 7.12.
7.18.5 7.18.6 7.18.7 7.18.8 7.18.9 7.18.10 7.18.11 7.18.12 7.18.13 7.18.14 7.18.15 7.18.16 7.18.17 7.18.18 7.18.19 File register direct 1-byte write (ZRWRB(P)) ............................................................ 7 - 393 Indirect address read operations (ADRSET(P)) ....................................................... 7 - 395 Numerical key input from keyboard (KEY) ............................................................... 7 - 396 Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) .
12.1.4 12.1.5 12.1.6 12.1.7 12.1.8 12.1.9 Error code list (2000 to 2999) ................................................................................... 12 - 16 Error code list (3000 to 3999) ................................................................................... 12 - 34 Error code list (4000 to 4999) ................................................................................... 12 - 51 Error code list (5000 to 5999) .....................................................................
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following list. The numbers in the "CPU module" and the respective modules are as follows.
Related Manuals Manual name Description < Manual number (model code) > CC-Link IE Controller Network Reference Manual Specifications, procedures and settings before system operation, parameter < SH-080668ENG (13JV16) > setting, programming, and troubleshooting of the CC-Link IE controller network module Q Corresponding MELSECNET/H Network System Reference Explains the specifications for a MELSECNET/H network system for PLC to PLC Manual (PLC to PLC network) network.
MEMO A-16
1 1 GENERAL DESCRIPTION 1-1
This manual explains the common instructions required for programming of the QCPU. The common instructions refer to all instructions except those dedicated to special function modules (such as AJ71QC24 and AJ71PT32-S3) and to AD57 models, as well as PID control instructions, SFC instructions and ST instructions. 1.
(2) Basic model QCPU 1 Qn(H)/QnPH/ QnPRHCPU User's Manual (Function Explanation, Program Fundamentals) 2 Explains the functions, programming methods, devices and others that are necessary to create programs with the CPU. 3 4 This manual QCPU Programming Manual (Common Instructions) QCPU(Q Mode)/ QnACPU Programming Manual (PID Control Instructions) Describes the instructions Describes the instructions other than those described to perform PID control. in the manuals on the right.
(4) Universal model QCPU QnUCPU User's Manual (Function Explanation, Program Fundamentals) Explains the functions, programming methods, devices and others that are necessary to create programs with the CPU. This manual QCPU Programming Manual (Common Instructions) QCPU(Q Mode)/ QnACPU Programming Manual (PID Control Instructions) Describes the instructions Describes the instructions other than those described to perform PID control. in the manuals on the right.
1.2 Abbreviations and Generic Names 1 This manual uses the generic names and abbreviations shown below to refer to Q series CPU modules, unless otherwise specified. * indicates a part of the model or version.
(Continued) Generic Name/Abbreviation Description of Generic Name/Abbreviation ■ Base unit model Q3 B Generic term for Q33B, Q35B, Q38B and Q312B main base units on which CPU module (except Q00JCPU), Q series power supply module, Q series I/O module, and intelligent function module can be mounted.
(Continued) Generic Name/Abbreviation 1 Description of Generic Name/Abbreviation ■ Others Product name of Q series Corresponding SW D5C-GPPW-type GPP function software 2 package GX Developer : Version of the software 3 Check the GX Developer versions that can be used for each CPU module in "System Configuration," QCPU User's Manual (Hardware Design, Maintenance and Inspection).
MEMO 1-8
2 INSTRUCTION TABLES 2 2-1
2.1 Types of Instructions The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in Table 2.1 below. Table 2.
Table 2.1 Types of Instructions (Continued) Types of Instruction Instruction for Data Link Link refresh instruction Routing information read/write instruction Meaning Reference Chapter Designated network refresh 8 2 Writing to host CPU shared memory, Reading from other CPU shared memory 9 3 Writes/reads devices to/from another CPU.
2.2 How to Read Instruction Tables The instruction tables found from Section 2.3 to 2.5 have been made according to the following format: BIN 16-bit addition and subtraction operations 1) Processing Details + + S D +P +P S D (D)+(S) + + S1 S2 D +P +P S1 S2 D (S1)+(S2) 2) 3) Execution Condition (D) (D) 4) 5) See for Description Symbol Subset Category Number of Basic Steps Instruction Symbols Table 2.2 How to Read Instruction Tables 3 6-16 4 6-20 6) 7) 8) Description 1) .
3) ..........Shows symbol diagram on the ladder. + S D S1 S2 D + Indicates destination. Indicates source. Indicates destination. Indicates instruction symbol. Indicates instruction symbol. 2 Indicates source. Fig. 2.1 Symbol Diagram on the Ladder 3 Destination............ Indicates where data will be sent after operation. Source .................. Stores data prior to operation. 4 4) ..........Indicates the type of processing that is performed by individual instructions.
2.3 Sequence Instructions 2.3.
*2: The number of steps may vary depending on the device and type of CPU module being used. Number of Steps Device 2.3.
2.3.3 Output instructions Processing Details Execution Condition See for Description Symbol Subset Category Number of Basic Steps Instruction Symbol Table 2.5 Output Instructions 5-20 OUT • Device output *1 - 5-22 5-26 5-28 SET SET D • Sets device *2 RST RST D • Resets device *2 PLS PLS D • Generates 1 cycle program pulse at leading edge of input signal.
2.3.5 Master control instructions control Processing Details MC MCR 2.3.6 n D MCR n Execution Condition • Starts master control 2 • Resets master control 1 See for Description MC Master Symbol Subset Category Number of Basic Steps Instruction Symbol Table 2.7 Master Control Instructions - 5-47 Execution Condition 5-53 • Termination of sequence program END Other instructions PAGE • Terminates sequence operation after input condition has been met.
2.4 Basic instructions 2.4.
LDD= D S1 S2 ANDD= D S1 S2 D S1 S2 LDD<> D S1 S2 ANDD<> D S1 S2 D S1 S2 LDD> D S1 S2 ANDD> D S1 S2 (S1+1, S1) (S2+1, S2) • Non-Conductive status when D See for Description *1 4 4 *1 (S2+1, S2) 6 • Conductive status when (S1+1, S1) (S2+1, S2) • Non-Conductive status when 7 *1 (S2+1, S2) S1 S2 6-4 data comparisons LDD<= S1 S2 D S1 S2 D S1 S2 LDD< D S1 S2 ANDD< D S1 S2 D S1 S2 LDD>= D S1 S2 ANDD>= D S1 S2 D S1 S2 ANDD<= (S1+1, S1) (S2+1, S2) • Non-Condu
LDE= E S1 S2 ANDE= E S1 S2 E S1 S2 LDE<> E S1 S2 ANDE<> E S1 S2 E S1 S2 LDE> E S1 S2 ANDE> E S1 S2 decimal E S1 S2 LDE<= E S1 S2 ANDE<= E S1 S2 E S1 S2 LDE< E S1 S2 ANDE< E S1 S2 E S1 S2 LDE>= E S1 S2 ANDE>= E S1 S2 E S1 S2 ORE> point data comparisons (Single precision) 3 - 3 - 3 - See for Description Condition (S2+1, S2) • Conductive status when (S1+1, S1) (S2+1, S2) • Non-Conductive status when (S2+1, S2) • Conductive status when (S1+1, S1) (S2+
LDED= ANDED= ED ED S1 S2 • Conductive status when S1 S2 (S1+3, S1+2, S1+1, S1) (S2+3, S2+2, S2+1, S2) • Non-Conductive status when ED S1 S2 (S1+3, S1+2, S1+1, S1) (S2+3, S2+2, S2+1, S2) LDED<> ED S1 S2 • Conductive status when ANDED<> ED S1 S2 (S1+3, S1+2, S1+1, S1) (S2+3, S2+2, S2+1, S2) ORED= • Non-Conductive status when ED S1 S2 (S1+3, S1+2, S1+1, S1) (S2+3, S2+2, S2+1, S2) LDED> ED S1 S2 • Conductive status when ANDED> ED S1 S2 (S1+3, S1+2, S1+1, S1) (S2+3, S2+2, S2+1, S2)
LD$= $ S1 S2 AND$= $ S1 S2 $ S1 S2 LD$<> $ S1 S2 AND$<> $ S1 S2 $ S1 S2 LD$> $ S1 S2 AND$> $ S1 S2 OR$> Character $ S1 S2 $ S1 S2 $ S1 S2 string data comparisons LD$<= AND$<= OR$<= $ S1 S2 LD$< $ S1 S2 AND$< $ S1 S2 OR$< • Compares character string S1 and character string S2 one character at a time.
BIN 16-bit Block data comparisons 32-bit block data comparisons BKCMP= BKCMP S1 S2 D n BKCMP<> BKCMP S1 S2 D n BKCMP> BKCMP S1 S2 D n BKCMP<= BKCMP S1 S2 D n BKCMP< BKCMP S1 S2 D n BKCMP>= BKCMP S1 S2 D n BKCMP=P BKCMP P S1 S2 D n BKCMP<>P BKCMP BKCMP>P BKCMP P S1 S2 D n BKCMP<=P BKCMP BKCMP
=P BKCMP P S1 S2 D n DBKCMP= DBKCMP S1 S2 D n DBKCMP<> DBKCMP S1 S2 D n DBKCMP> DBKCMP S1 S2 D n DBKCMP<= DBKCMP S1 S2 D n DBKCMP< DBKCMP S1 S2 D
2.4.
*1: The number of steps may vary depending on the device and type of CPU module being used. Component Number of Device • Word device: • Bit device: High Performance model QCPU Process CPU • Constant: Redundant CPU Basic model QCPU Universal model QCPU Steps Internal device (except for file register ZR) Devices whose device Nos. are multiples of 16, whose digit designation is K8, and which use no indexing.
Processing Details B+ B+ S D B+P B+P S D • (D)+(S) BCD 4-digit addition B+ B+ S1 S2 D B+P B+P S1 S2 D B- B S D B-P B P S D Condition 3 (D) • (S1)+(S2) Execution 4 (D) See for Description Symbol Subset Category Number of Basic Steps Instruction Symbol Table 2.
E+ E+ Processing Details decimal point data addition E+P E+ E+P 3 S D E+ S1 S2 D E+P S1 S2 D E S D (D+1, D) *6 4 *5 *6 6-46 6-48 and subtraction operations (Single precision) E- • (D+1, D) E-P E- E P E Floating decimal point data addition ED+ (S2+1, S2) (D+1, D) S1 S2 D ED+ ED+P (D+1, D) S1 S2 D E P ED+ (S+1, S) S D ED+P ED+ S D S1 S2 D • (D+3, D+2, D+1, D)+(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 6-46 ED+P S1 S2 D (D+3, D+2, D+1, D) ED- ED S D • (D+3, D+2, D+1,
subtraction operations BK+ BK+ S1 S2 D n BK+P BK+P S1 S2 D n - BK- BK S1 S2 D n • This instruction substracts BIN 16-bit data stored in the n-point devices starting from the devices specified by (S2) from BIN 16bit data stored in n-point devices starting from the device specified by (S1) in batch.
*7: The number of steps may vary depending on the device and type of CPU module being used. Component High Performance model QCPU Process CPU Redundant CPU Basic model QCPU Universal model QCPU Device • Word device: • Bit device: • Constant: Internal device (except for file register ZR) Devices whose device Nos. are multiples of 16, whose digit designation is K8, and which use no indexing.
2.4.
DBL S D (S) 16-bit DBLP DBLP S D 32-bit WORD WORD S D conversion BIN Gray code BIN (D+1, D) BIN (-32768 to 32767) Conversion (S+1, S) WORDP WORDP S D GRY GRY S D GRYP GRYP S D DGRY DGRY S D conversions Gray code Conversion DGRYP DGRYP S D GBIN GBIN S D GBINP S D DGBIN DGBIN S D DGBINP DGBINP S D NEG D conversions NEG NEGP NEGP D DNEG DNEG D Conversion to gray code (S) (D) BIN (-32768 to 32767) Condition 3 - 6-88 3 - 6-89 3 - 3 - Conversion to
2.4.4 Data transfer instructions 16-bit data transfer MOV MOV Condition *4 S D ( D) (S) MOVP MOVP S D DMOV DMOV S D DMOVP DMOVP S D EMOV EMOV S D See for Description Execution Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
Exchange BXCH BXCHP S D n BXCHP SWAP 4 - 6-126 n (S) D b15 to b8 b7 to b0 8 bits (D) 8 bits 3 and lower bytes 4 b15 to b8 b7 to b0 8 bits 8 bits D SWAPP SWAPP - 6-128 4 *1: The number of steps may vary depending on the device and type of CPU module being used.
*3: The subset is effective only with QCPU. *4: The number of steps may vary depending on the device and type of CPU module being used. Component Device • Word device: • Bit device: QCPU • Constant: Internal device (except for file register ZR) Devices whose device Nos. are multiples of 16, whose digit designation is K4, and which use no indexing.
2.4.5 Program branch instructions Processing Details CJ CJ Pn SCJ SCJ Pn JMP JMP Pn Jump GOEND 2.4.6 Execution Condition • Jumps to Pn when input conditions are 2 met. • Jumps to Pn from the scan after the 6-129 2 meeting of input condition. • Jumps unconditionally to Pn. 2 • Jumps to END instruction when input GOEND See for Description Symbol Subset Category Number of Basic Steps Instruction Symbol Table 2.14 Program Branch Instructions 1 condition is met.
2.4.8 Other convenient instructions Condition See for Description Execution Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
2.5 Application Instructions 2.5.
DXOR DXOR S1 S2 D DXORP DXORP S1 S2 D (S2+1,S2) (S1+1,S1) Exclusive OR BKXOR BKXOR BKXORP BKXORP S1 S2 D n (S1) S1 S2 D n WXNR WXNR S D WXNRP WXNRP S D WXNR NON exclusive logical sum WXNRP (S2) DXNR S D DXNRP DXNRP S D (D+1,D) DXNR DXNR S1 S2 D DXNRP DXNRP S1 S2 D BKXNR BKXNR S1 S2 D n BKXNRP BKXNRP S1 S2 D n (S1) (D+1,D) (D+1,D) See for Description 7-25 7-27 7-30 *1 (S2+1,S2) (S2) - 4 (D) (S+1,S) 5 3 S1 S2 D DXNR 7-22 *3 (D) (D) (S) (S1+1,S1)
*1: The number of basic steps is three for the Universal model QCPU only. *2: The number of steps may vary depending on the device and type of CPU module being used. Component Device Number of 1 Steps • Word device: Internal device (except for file register ZR) High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit designation is K8, and which use no indexing.
2.5.2 Rotation instructions Condition ROR ROR D n RORP RORP D n Right rotation by n bits Carry flag D n b15 b15 (D) See for Description Execution Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
2.5.
2.5.
2.5.5 Data processing instructions 1 SERP SER S1 S2 D n SERP Condition 5 - (S2) (S1) (D): Match No. (D + 1): Number of matches S1 S2 D n 7-66 DSER DSERP DSER S1 S2 D n DSERP SUM S D SUMP SUMP S D DSUM DSUM S D DSUMP DSUMP S D DECO DECO S D n Decode S D n ENCO ENCO S D n ENCOP ENCOP S D n SEG S D SEG ment decode 5 SEGP S D - 6 (D): Match No.
S D n DISP DISP S D n UNI UNI S D n UNIP UNIP S D n NDIS NDIS S1 D S2 NDISP NDISP S1 D S2 Separating and linking NUNI NUNI S1 D S2 NUNIP NUNIP S1 D S2 WTOB WTOB S D n WTOBP WTOBP S D n BTOW BTOW S D n BTOWP BTOWP S D n MAX MAX S D n MAXP MAXP S D n Condition • Separates 16-bit data designated by (S) into 4-bit units, and stores at the lower 4 bits of n points from (D).
SORT SORT S1 n S2 D1 D2 · S2: Number of comparisons to be made during a single run · D1: Device to be turned ON at the completion of sort · D2: For system use Execution Condition WSUM WSUM S D n (n x (n-1)/2 scans required) - calculations WSUMP WSUMP S D n DWSUM DWSUM S D n (n x (n-1)/2 scans required) 6 • Adds 16 bit BIN data of n points from the 7-99 the device specified by (D). of averages MEAN S D n MEANP MEANP S D n 7-101 the device specified by (D).
2.5.6 Structure creation instructions FOR Number of repeats FOR NEXT n and NEXT . NEXT BREAK BREAK BREAKP D Pn BREAKP D Pn CALL Pn CALL CALL Pn S1 Sn CALLP Pn CALLP CALLP RET RET FCALL FCALL Pn Pn S1 Sn program calls FCALLP Pn FCALLP ECALL ECALL 1 - 3 - 7-105 7-108 • Executes subroutine program Pn when *1 input condition is met. (S1 to Sn are 2 arguments sent to subroutine program.
Processing Details EFCALL EFCALL EFCALL Pn S1toSn EFCALLP EFCALLP program Condition Pn EFCALLP Pn S1toSn • Performs non-execution processing of 3 conditions have not been met. (S1 to + Sn are arguments sent to subroutine n program. N - 7-125 5) input condition is met. XCALL XCALL Pn S1 Sn subroutine program Pn if input conditions have not been met. (S1 to Sn are arguments sent to subroutine program.
2.5.7 Data table operation instructions S D FIFWP FIFWP S D FIFR FIFR S D FIFRP FIFRP S D FPOP FPOP S D (S) (D) Pointer Condition FPOPP FPOPP FDEL S D n FDELP FDELP S D n - 7-151 3 - 7-153 3 - 7-155 4 - Device at pointer + 1 (S) Pointer (S) Pointer (D) Pointer - 1 Pointer - 1 S D FDEL 3 Pointer + 1 (D) Data table processing See for Description FIFW Execution Processing Details Subset FIFW Symbol Number of Basic Steps Category Instruction Symbol Table 2.
2.5.8 Buffer memory access instructions 1 FROM FROM Processing Details n1 n2 D n3 FROMP FROMP n1 n2 D n3 DFRO DFRO n1 n2 D n3 Execution Condition • Reads data in 16-bit units from an intelligent function module. 5 - See for Description Symbol Subset Category Number of Basic Steps Instruction Symbol Table 2.
2.5.10 Debugging and failure diagnosis instructions Condition See for Description Execution Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.27 Debugging and Failure Diagnosis Instructions 1 - 7-175 1 - 7-179 • The CHK instruction is executed when CHKST is executable. CHKST CHKST • Jumps to the step following the CHK instruction when CHKST is in a non-executable status.
2.5.
ASCII BCD DABCD S D DABCDP DABCDP S D DDABCD DDABCD S D DDABCDP Device comment read operation Character COMRD DDABCDP S D COMRD S D COMRDP COMRDP S D LEN LEN S D LENP LENP S D string length detection BIN STR STR S1 S2 D STRP STRP S1 S2 D DSTR DSTR S1 S2 D Decimal character string DSTRP DSTRP VAL VAL S1 S2 D S D1 D2 Decimal character VALP VALP S D1 D2 DVAL DVAL S D1 D2 DVALP DVALP S D1 D2 ESTR ESTR string BIN Floating decimal point Character string Chara
Hexadecimal BIN ASCII ASCII Hexadecimal BIN ASC ASC S D n ASCP ASCP S D n HEX HEX S D n HEXP HEXP S D n RIGHT RIGHT S D n RIGHTP RIGHTP S D n LEFT LEFT S D n Execution Condition See for Description Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
2.5.12 Special function instructions See for Description functions Subset Trigonometric Number of Basic Steps Category Instruction Symbol Table 2.
See for Description 3 - 7-275 (D+3, D+2, D+1, D) (S+3, S+2, S+1, S) Conversion from angle to radian 3 - 7-277 (D+1, D) (S+1, S) Conversion from radians to angles 3 - 7-279 (S+3, S+2, S+1, S) (D+3, D+2, D+1, D) Conversion from radian to angle 3 - 7-281 3 - 7-287 3 - 7-289 (D+1,D) 3 - 7-291 (D+3, D+2, D+1, D) 3 - 7-294 (D+1,D) 3 - 7-296 (D+3, D+2, D+1, D) 3 - 7-298 4 - 7-300 4 - 7-302 3 - 7-300 3 - 7-302 Processing Details RAD S D RADP RADP S D RADD RAD
RND D generation RNDP RNDP D Random SRND SRND D • Updates random number series SRNDP SRNDP D in the device designated by (S).
2.5.13 Data control instructions 1 LIMIT LIMIT S1 S2 S3 D Condition Upper and LIMITP S1 S2 S3 D 5 controls 2 • When (S2) (S3) ......... Stores value of (S2) at (D) 7-321 DLIMIT DLIMIT S1 S2 S3 D • When ((S3)+1, (S3)) ((S1)+1, S1) .. Stores value of ((S1)+1, (S1)) at ((D)+1, (D)) • When ((S1)+1, (S1)) ((S3)+1, (S3)) (S2+1, S2) .. Stores value of ((S3)+1, (S3)) at ((D)+1, (D)) DLIMITP S1 S2 S3 D • When ((S2), (S2)+1) ((S3), (S3)+1) ..
Execution Condition 4 - See for Description Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.30 Special Function Instructions (Continued) • Executes scaling for the scaling SCL SCL S1 S2 D conversion data (16-bit data units) specified by (S2) with the input value specified by (S1), and then stores the result into the device specified by (D).
2.5.14 Switching instructions 1 RSET S number switching RSETP RSETP S QDRSET QDRSET QDRSETP QDRSETP File name QCDSET QCDSET • Converts extension file register block number to number designated by (S). 2 - 7-337 2 + - • Sets file names used as comment files. 2 + 4 4 7-339 6 *1 File name 2 2 n File set QCDSETP File name Condition *1 File name • Sets file names used as file registers.
2.5.15 Clock instructions DATERD D DATERDP DATERDP D DATEWR DATEWR S Read/ (Clock elements) (D) +0 Year +1 Month +2 Day +3 Hour +4 Minute +5 Sec. +6 Day of the week Execution Condition See for Description DATERD Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
LDDT= ANDDT= ORDT= LDDT<> ANDDT<> ORDT<> LDDT< ANDDT< ORDT< Date comparison DT S1 S2 n DT S1 S2 n DT S1 S2 n DT S1 S2 n DT DT DT Condition See for Description Execution 1 2 4 S1 Year S2 Year S1 +1 Month S2 +1 Month S1 +2 Day S2 +2 Day Companson operation resuit 4 - 4 S1 S2 n DT DT Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
ANDTM= ORTM= LDTM<> ANDTM<> ORTM<> LDTM< ANDTM< ORTM< Clock comparison TM TM S1 S2 n S1 S2 n TM S1 S2 n S1 Hour S2 4 - Companson operation resuit 4 - See for Description Companson operation resuit Hour S1 +1 Minute S2 +1 Minute S1 +2 Second S2 +2 Second S1 S2 Companson operation resuit Hour Hour S1 +1 Minute S2 +1 Minute S1 +2 Second S2 +2 Second S1 S2 S1 S2 n TM S1 S2 n TM S1 S2 n TM - Condition S1 S2 n TM TM 4 Execution Processing Details S1 S2 n Hour
2.5.16 Expansion clock instruction 1 S.DATReading ERD (Clock elements) S.DATERD D data of the expansion clock SP.DATERD S.DATE+ SP.DATERD D S.DATE+ S1 S2 D Adding or subtracting SP.DATE+ data val- SP.DATE+ S1 S2 D ues of the expansion S.DATE- S.DATE S1 S2 D clock SP.DATE- SP.DATE S1 S2 D (S1) Hour Minute Sec. 1/1000 sec. Condition (D) +0 Year +1 Month +2 Day +3 Hour +4 Minute +5 Sec. +6 Day of the week +7 1/1000 sec. (S2) Hour Minute + Sec. 1/1000 sec.
2.5.17 Program control instructions File name PSTOPP PSTOPP File name POFF POFF File name Program control instructions POFFP File name PSCAN PSCAN File name PSCANP PSCANP File name PLOW PLOW File name PLOWP PLOWP LDPCHK PCHK File name status. • Turns OUT instruction coil of designated standby status. ORPCHK PCHK PCHK 2 + n 7-377 - 7-378 - 7-380 - 7-382 - 7-384 *1 2 + n execution type. 2 + n *1 • Registers designated program as low-speed execution type.
2.5.18 Other instructions 1 reset WDT WDTP Timing DUTY clock • Resets watchdog timer during sequence program. WDTP Condition 1 - 7-386 n1 scans n1 n2 D n2 scans 4 - 7-388 4 - 7-390 SM420 to SM424, SM430 to SM434 TIMCHK TIMCHK S1 S2 D 4 4 6 • Turns ON device specified by (D) if Time check 2 2 (D) DUTY Execution See for Description WDT WDT Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.
TYPERD n D TYPERDP TYPERDP n D - 1 - 1 - • Writes data to the designated file. 11 - • Reads data from the designated file. 11 - • Writes data to the device data storage file in the standard ROM. 9 - • Reads data from the device data storage file in the standard ROM. 8 - 3 - 3 - 4 - 4 - • This instruction reads the module information stored in the area starting from the I/O number specified by "n", and stores it in the area starting from the device specified by (D).
2.5.19 Instructions for Data Link 1 Q link instruction: Network refresh Reading routing information Registering routing information S.ZCOM S.ZCOM SP.ZCOM SP.ZCOM Jn S.ZCOM S.ZCOM SP.ZCOM SP.ZCOM Un Execution Condition See for Description Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.36 Instructions for Data Link Refreshes the designated network. 5 - 8-2 2 Un S.RTREAD n D SP.RTREAD SP.RTREAD n D Z.RTREAD Z.RTREAD n D ZP.
2.5.20 Multiple CPU dedicated instruction S. TO S.TO n1 n2 n3 n4 D SP. TO SP.TO n1 n2 n3 n4 D TO TO n1 n2 S n3 TOP TOP n1 n2 S n3 DTO DTO n1 n2 S n3 DTOP DTOP n1 n2 S n3 CPU shared memory Read from other FROM FROM n1 n2 D n3 FROMP FROMP n1 n2 D n3 DFRO DFRO n1 n2 D n3 DFROP DFROP n1 n2 D n3 CPU shared memory 2.5.21 Processing Details Execution Condition • Writes device data of the host station to the host CPU shared memory.
2.5.22 Redundant system instructions (For Redundant CPU) 1 Execution Condition See for Description Processing Details Subset Symbol Number of Basic Steps Category Instruction Symbol Table 2.39 Redundant System Instructions (For Redundant CPU) 8 - 11-2 Switches between the control system and System switching SP.CONTSW SP.CONTSW S D standby system at the END processing of the scan executed with the SP.CONTSW 2 4 4 instruction. 2 6 7 8 2.5 Application Instructions 2.5.
MEMO 2-62
3 CONFIGURATION OF INSTRUCTIONS 3 3-1
3.1 Configuration of Instructions Most CPU module instructions consist of an instruction part and a device part. Each part is used for the following purpose: • Instruction part ...... indicates the function of the instruction. • Device part ............ indicates the data that is to be used with the instruction. The device part is classified into source data, destination data, and number of devices. (1) Source (S) (a) Source is the data used for operations.
3.2 Designating Data The following six types of data can be used with CPU module instructions. Bit data ...................... Section 3.2.1 Data that can be handled by CPU module Numeric data Integer data Word data Real number (floating point) data Character string data .... Section 3.2.5 3.2.1 .......................Section 3.2.2 Double-word data ...........Section 3.2.3 Single-precision floating point data .... Section 3.2.4 (1) Double-precision floating point data .... Section 3.2.
3.2.2 Using word (16 bits) data Word data is 16-bit numeric data used by basic instructions and application instructions. The following two types of word data can be used with CPU module: • Decimal constants................. K-32768 to K32767 • Hexadecimal constants ......... H0000 to HFFFF Word devices and bit devices designated by digit can be used as word data. For direct access input (DX) and direct access output (DY), word data cannot be designated by digit.
(c) When destination (D) data is a word device The word device for the destination becomes 0 following the bit designated by digit designation at the source. Ladder Example Processing With 16-Bit Instruction K1X0 X3 X2 X1 X0 X010 MOV K1X0 Filled with 0s D0 3 b15 b4 b3 b2 b1 b0 D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0 Source (S) data Fig 3.
3.2.3 Using double word data (32 bits) Double word data is 32-bit numerical data used by basic instructions and application instructions. The two types of double word data that can be dealt with by CPU module are as follows: • Decimal constants................. K-2147483648 to K2147483647 • Hexadecimal constants ......... H00000000 to HFFFFFFFF Word devices and bit devices designated by digit designation can be used as double word data.
(c) When destination (D) data is a word device The word device for the destination becomes 0 following the bit designated by digit designation at the source. Ladder Example Processing With 32 bit Instructions K1X0 X3 X2 X1 X0 Filled with 0s X10 DMOV K1X0 D0 Source (S) data 3 b15 b4 b3 b2 b1 b0 D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b31 b16 4 Filled with 0s Fig 3.
(2) Using word devices A word device designates devices used by the lower 16 bits of data. A 32-bit instruction uses (designation device number) and (designation device number + 1). M0 DMOV K100 D0 Designation of 2 points of word devices D0 and D1 (32 bits) 32-bit data transfer instruction 3.2.4 Using real number data Real number data is floating decimal point data used with basic instructions and application instructions. Only word devices are capable of storing real number data.
• Variable part The 23 bits from b0 to b22, represents the XXXXXX... at binary 1.XXXXXX.... (2) Double-precision floating-point data Instructions which deal with double-precision floating-point datadesignate devices which are used for the lower 16 bits of data. Double-precision floating-point data are stored in the 64 bits which make up (designated device number) to (designated device number + 3).
1. The CPU module floating decimal point data can be monitored using the monitoring function of a peripheral device. 2. When floating-point data is used to express 0, all data in the following range are turned to 0. (a) Single-precision floating-point data: b0 to b31 (b) Double-precision floating-point data: b0 to b63 3. The setting range of floating decimal point data is as follows.
3.2.5 Using character string data Character string data is character data used by basic instructions and application instructions. The target ranges from the designated character to the NULL code (00H) that indicates the end of the character string. (1) When designated character is the NULL code 3 One word is used to store the NULL code.
3.3 Indexing (1) Overview of indexing (a) Indexing is an indirect setting made by using an index register. When an Indexing is used in a sequence program, the device to be used will become the device number specified directly plus the contents of the index register. For example, if D2Z2 has been specified, the specified device is calculated as follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.
2) Devices with limits for use with index registers Device Meaning Application Example T • Only Z0 and Z1 can be used for timer contacts and coils. C • Only Z0 and Z1 can be used for counter contacts and coils. T0Z0 K100 T1Z1 C0Z1 K100 C1Z0 1 2 3 Remark For timer and counter present values, there are no limits on index register numbers used.
• Specifing the 32-bit indexing using “ZZ” specification. The 32-bit indexing with “ZZ” specification is available only for the following CPU modules that the version of GX Developer is 8.68W or later. • The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher. • QnUDE(H)CPU (a) Example of specifing the range of index registers for use of 32-bit indexing. 1) Each index register can be set between -2147483648 and 2147483647. An example of indexing is shown below.
3) Device that indexing can be used Indexing can be used only for the device shown below. Device 1 Meaning ZR Serial number access format file register D Extended data register (D) W Extended link register (W) 2 4) Usable range of index registers The following table shows the usable range of index registers for indexing with 32-bit index registers. For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the specified register (Zn+1) are used.
(b) Example of specifing 32-bit indexing with “ZZ” specification. 1) One index register can specify 32-bit indexing by using “ZZ” specification such as “ZR0ZZ4”. The 32-bit indexing with “ZZ” specification is as follows. M0 M0 DMOVP K100000 Z4 Stores 100000 at Z4 and Z5.
5) The 32-bit indexing used “ZZ” specification and the acutual processing device are as follows. (Z0 (32-bit) 100000.Z2 (16-bit) 20) Ladder Example Actual Process Device X1 X0 DMOV K100000 Z0 MOV 2 ZR101000 D10 3 END MOV X1 K-20 Z2 Description MOV ZR1000ZZ0 D30Z2 ZR1000ZZ0 D30Z2 4 ZR(1000+100000)=ZR101000 D(30-20)=D10 2 Fig.3.
(4) Index modification using extended data register (D) and extended link register (W) (Universal model QCPU(except Q00UJCPU)) Like index modification using data register (D) and link register (W) of internal user device, a device can be specified by index modification within the range of the extended data register (D) and extended link register (W).
2) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) will not cause an error.
(5) Other index modifications (a) Bit data Device numbers can be index modified when performing digit designation. However, Indexing is not possible by digit designation. BIN K4X0Z2 D0 BIN K4Z3X0 D0 Setting is possible since this indicates Indexing for device number. If Z2=3, then (X0+3)=X3 Setting is not possible since this indicates Indexing by digit designation. (b) Both I/O numbers and buffer memory number can be performed indexing with intelligent function module devices*1.
(e) Index modification using extended data register (D) and extended link register (W) by 32 bits (Universal model QCPU(except Q00UJCPU)) Like index modification using file register (ZR), index modification using extended data register (D) and extended link register (W) by 32 bits can be performed by the following two methods. 1 2 • Specifing the index registers’ range used for indexing with 32-bit. • Specifing the 32-bit indexing using “ZZ” specification.
(b) Performing indexing with the CALL instruction Pulses can be output with the CALL instruction by use of the edge relay (V). However, pulse output using the PLS/PLF/pulse ( P) instruction is not allowed. [When edge relay is used] [When edge relay is not used] (M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.
3.4 Indirect Specification 1 (1) Indirect Specification (a) Indirect specification is a method that specifies address of the device to be used in a sequence program using two word devices (two points of word device). Use indirect specification as index modification when the index register is insufficient. ADRSET D100 D0 MOV K50 Z0 DMOV K50 W0 DMOV K10000 D150 DMOV K10000 D150 DMOV D100Z0 D110 W0 D10 D+ D0 Specification of D (100 + 50) = D150 MOV @D10 Stores the address of D100 to D0.
(3) Precautions (a) The address for indirect specification uses two words.Therefore, to substitute indirect specification for index modification, the addition/subtraction of 32-bit data is required. The following is the ladder used for the address addition/subtraction of the device stored in D1 and D0 for indirect specification.
3.5 Reducing Instruction Processing Time 1 3.5.1 Subset Processing 2 Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to increase processing speed. 3 However, the instruction symbol does not change. To shorten scans, run instructions under the conditions indicated below.
(2) Instructions for which subset processing can be used Types of Instructions Instruction Symbols LD,LDI,AND,ANI,OR,ORI,LDP,LDF,ANDP,ANDF,ORP,ORF,LDPI,ANDPI,ANDFI, Contact instructions ORPI,ORFI Output instructions OUT,SET,RST Comparison operation instruction • • +, Arithmetic operation , , , , , ,D ,*,/,INC,DEC,D+,D • B+,B ,B*,B/, E+,E ,D ,D ,D ,D ,D ,D*,D/,DINC,DDEC ,E*,E/ Data conversion instructions • BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT Data transfer instruction • MOV
3.6 Cautions on Programming (Operation Errors) 1 Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU module: • An error listed on the explanatory page for the individual instruction occurred. • When an intelligent function module device is used, no intelligent function module is installed at the specified I/O number position. • When an intelligent function module device is used, the specified buffer memory address does not exist.
2) Universal model QCPU The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when12 k points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287. DMOV K100 D12287 When D12287 is specified with the DMOV instruction, the target devices are D12287 and D12288. However, an operation error occurs because D12288 does not exist. The device range is checked even though indexing is executed.
2) Universal model QCPU The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when12 k points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287. 1 2 BMOV D0 D12287 K2 When D12287 is specified with the BMOV instruction, the target devices are D12287 and D12288. However, an operation error occurs because D12288 does not exist.
When performing the following access in Universal model QCPU, an error (error code: 4101) occurs.
Remark For the how to change the internal user device allocation, referto User’s Manual (Functions Explanation, Program Fundamentals) for the CPU module used. 1 2 (d) Device range checks are conducted when indexing is performed by direct access output (DY). (e) Set the following items so that the specification does not cross over theboundary between the internal user device and the extended data register (D) or extended link register (W).
(2) Device data check Device data checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: (a) When using BIN data No error is returned even if the operation results in overflow or underflow. The carry flag does not go on at such times, either. (b) When using BCD data 1) Each digit is check for BCD value (0 to 9). An operation error is returned if individual digits are outside the 0 to 9 (A to F) range.
3.7 Conditions for Execution of Instructions 1 The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic instructions, and application instructions: • Non-conditional execution...... Instructions executed without regard to the ON/OFF status of the device Example LD X0, OUT Y10 • Executed at ON...................... Instructions executed while input condition is ON 2 3 Example MOV instruction, FROM instruction • Executed at leading edge ......
3.8 Counting Step Number The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending on whether indirect setting of the device used is possible or not. (1) Counting the number of basic steps The basic number of steps for basic instructions and application instructions is calculated by adding the device number and 1.
(c) Devices with additional steps (Universal model QCPU(except Q00UJCPU)) 1) Instructions applicable to subset processing 1 The following table shows steps depending on the devices.
Added Steps Instruction Symbols Devices with Additional Steps (Number of Instruction Steps) Standard device register *2 Basic Number of Steps :-1 Serial number access format file register D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR, Extended data register (D), DANDP,DORP,DXORP,DXNRP Extended link register (W) (2 devices) :1, :1 constant, real constant WANDP,WORP,WXORP,WXNRP (3 devices)*1 3 Multiple CPU shared device Decimal constant, hexadecimal +,-,+P,-P,WAND,WOR,WXOR,WXNR, :3 Serial number access
Added Steps Instruction Symbols Devices with Additional Steps (Number of Basic Number of Instruction Steps) INC,INCP,DEC,DECP,DINC,DINCP, DDEC,DDECP Index register/Standard device register *2 Serial number access format file register Extended data register (D), Extended link register (W) Multiple CPU shared device Serial number access format file register Extended data register (D), MOV,MOVP Extended link register (W) Multiple CPU shared device Serial number access format file register Steps 1 2
Added Steps Locations Where Standard Device Regis- Instruction Symbols ter Is Used , *, *P, /, /P , or , , or Basic Number of (Number of Instruction Steps) Steps -2(1) , and 3 -1(2) and -2(1) , and -1(2) and and (only when that device that the D*, D*P, D/, D/P, E*, E*P number of steps does not increase is specified for ±0(3) 3 ) and (only when a serial number access format file register is specified for MOV,MOVP,DMOV,DMOVP,EMOV,EMOVP +2(5) ) and -1(1) 2 and -1(1) 2 BCD,BCDP,BI
3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device 1 The following describes the operation for executing multiple instructions of the OUT, SET/RST, or PLS/PLF that use the same device in one scan. 2 3 (1) OUT instructions using the same device Do not program more than one OUT instruction using the same device in one scan.
(2) SET/RST instructions using the same device (a) The SET instruction turns ON the specified device when the execution command is ON and performs nothing when the execution command is OFF. For this reason, when the SET instructions using the same device are executed two or more times in one scan, the specified device will be ON if any one of the execution commands is ON.
(3) PLS instructions using the same device The PLS instruction turns ON the specified device when the execution command is turned ON from OFF. It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF). If two or more PLS instructions using the same device are executed in one scan, each instruction turns ON the device when the corresponding execution command is turned ON from OFF and turns OFF the device in other cases.
• The X0 and X1 turn ON from OFF at the same time. X0 X0 PLS M0 X1 PLS M0 END END PLS M0 X1 PLS M0 END ON X0 OFF X1 OFF M0 OFF ON ON M0 turns ON because X1 goes ON (OFF ON). (M0 remains ON.) M0 turns ON because X0 goes ON (OFF ON). M0 turns OFF because X1 status is other than OFF ON. (M0 remains OFF.) M0 turns OFF because X0 status is other than OFF ON.
[Timing Chart] • The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON throughout the scan.) X0 X0 PLF M0 PLF M0 END END 2 PLF M0 X1 PLF M0 END X1 3 ON OFF X0 4 ON X1 1 OFF ON 2 M0 OFF M0 turns OFF because X1 status is M0 turns OFF because X1 other than ON OFF. status is other than ON OFF. (M0 remains OFF.) M0 turns ON because X0 goes OFF (ON OFF). M0 turns OFF because X0 status is other than ON OFF (M0 remains OFF.
3.10 Precautions for Use of File Registers This section explains the precautions for use of the file registers in the QCPU. (1) CPU modules that cannot use file registers The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use the CPU module of other than the Q00JCPU and Q00UJCPU. (2) Setting of file registers to be used When using the file registers, the file registers to be used must be set with the PLC parameter or QDRSET instruction.
Remark For the file register setting method and file register area securing method, refer to User’s Manual (Functions Explanation, Program Fundamentals) for the CPU module used. (4) Designation of file register number in excess of the registered number of points (a) CPUs other than Universal model QCPU An error will not occur if data are written or read to or from the file registers that have numbers greater than the registered number of points.
(b) Serial number access method In the serial number access method, specify the file registers beyond 32k points with consecutive device numbers. The file registers of multiple blocks can be used as consecutive file registers. Use "ZR" as the device name.
3) When a block number is switched by the RSET instruction, refresh is performed to the data of the file register (R) in the switched block number. When a block number is switched by the RSET instruction, refresh is performed to the data of the file register (R) in the block number at the time of the END instruction execution. To read/write the refresh data, specify the file register of the block number at the time of the END instruction execution.
MEMO 3-48
4 HOW TO READ INSTRUCTIONS 4 4-1
The description of instructions that are contained in the following chapters are presented in the following format. 1) 2) 3) 4) 5) 6) 7) 8) 1) Code used to write instruction (instruction symbol). 2) Section number and general category of instructions described. 3) Shows if instructions are enabled or disabled for each CPU module type.
9) 4 4) Indicates ladder mode expressions and execution conditions for instructions. Execution Condition Non-conditional Execution Code recorded on No symbol description page recorded Executed while ON Executed One Time at ON Executed while OFF Executed One Time at OFF 5) Indicates the data set for each instruction and the data type.
6) Devices which can be used by the instruction in question are indicated with circle.
5 7 SEQUENCE INSTRUCTIONS 7 7 7 5 7 Category Contact instruction Association instruction Processing Details Operation start, series connection, parallel connection Ladder block connection, creation of pulses from operation results, store/read operation results Section Section 5.1 Bit device output, pulse output, output reversal Section 5.3 Shift instruction Bit device shift Section 5.4 Master control instruction Master control Section 5.
LD,LDI,AND,ANI,OR,ORI 5.1 Contact Instructions 5.1.1 Operation start, series connection, parallel connection (LD,LDI,AND,ANI,OR,ORI) LD,LDI,AND,ANI,OR,ORI Basic High performance Process Redundant Universal Bit device number / Word device bit designation ( S ) X1/D0.1 LD X1/D0.1 LDI X2/D0.2 AND X2/D0.2 ANI OR X3/D0.3 ORI X3/D0.
LD,LDI,AND,ANI,OR,ORI AND, ANI (1) AND is the A contact series connection instruction, and ANI is the B contact series connection instruction. They read the ON/OFF data of the designated bit device*2, perform an AND operation on that data and the operation result to that point, and take this value as the operation result. *2: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of the designated bit.
LD,LDI,AND,ANI,OR,ORI Operation Error (1) There are no operation errors with LD, LDI, AND, ANI, OR, or ORI instruction. Program Example (1) A program using the LD, AND, OR, and ORI instructions. [Ladder Mode] [List Mode] Step b15 D0 Device Bit designated for word device b0 b5 1 Instruction 0 (2) A program linking contacts using the ANB and ORB instructions.
LDP,LDF,ANDP,ANDF,ORP,ORF 5.1.2 Pulse operation start, pulse series connection, pulse parallel connection (LDP,LDF,ANDP,ANDF,ORP,ORF) 1 LDP,LDF,ANDP,ANDF,ORP,ORF Basic High performance Process Redundant Universal 2 3 Bit device number / Word device bit designation ( S ) 4 X1/D0.1 LDP 5 X1/D0.1 LDF 6 X2/D0.2 ANDP X2/D0.2 7 ANDF ORP 8 X3/D0.3 X3/D0.
LDP,LDF,ANDP,ANDF,ORP,ORF (2) LDF is the trailing edge pulse operation start instruction, and is ON only at the trailing edge of the designated bit device (when it goes from ON to OFF). If a word device has been designated, it is ON only when the designated bit changes from 1 to 0. ANDP, ANDF (1) ANDP is a leading edge pulse series connection instruction, and ANDF is a trailing edge pulse series connection instruction.
LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI 5.1.3 Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection (LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI) 1 2 LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI Ver. Basic High performance Process Redundant Universal • QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. • QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. 3 4 Bit device number / Word device bit designation ( S ) X1/D0.1 LDPI 5 X1/D0.1 LDFI 6 X2/D0.
LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI (2) LDFI is the trailing edge pulse NOT operation start instruction that is on only at the trailing edge of the specified bit device (when the bit device goes from off to on) or when the bit device is on or off. If a word device has been specified, LDFI is on only when the specified bit is 0, 1, or changes from 0 to 1.
LDPI,LDFI,ANDPI,ANDFI,ORPI,ORFI Program Example 1 (1) The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is on, off, or turns from off to on. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 (2) The following program stores 0 into D0 when X0 is on and b10 (bit 11) of D0 is on, off, or turns from on to off. Ladder Mode] 5 [List Mode] Step Instruction 6 Device 7 8 5.1 Contact Instructions 5.1.
ANB,ORB 5.2 Association Instructions 5.2.1 Ladder block series connection and parallel connection (ANB,ORB) ANB,ORB Basic High performance Process Redundant Universal ANB ANB Block A Block B Block A ORB ORB Block B Internal Devices Setting Data Bit Word R, ZR J For parallel connection of 1 contact, OR or ORI is used. \ Bit U Word –– \G Zn Constants Other –– Function ANB (1) Performs an AND operation on block A and block B, and takes the resulting value as the operation result.
ANB,ORB Operation Error 1 (1) There are no operation errors associated with ANB or ORB instruction. 2 Program Example 3 (1) A program using the ANB and ORB instructions. [Ladder Mode] [List Mode] Step 4 Instruction Device 5 6 7 8 5.2 Association Instructions 5.2.
MPS,MRD,MPP 5.2.2 Operation results push,read,pop (MPS,MRD,MPP) MPS,MRD,MPP Basic High performance Process Redundant Universal In the ladder display, MPS, MRD and MPP are not displayed. Command Command MPS Command MRD Command MPP Setting Data –– Internal Devices Bit Word R, ZR J Bit \ U Word \G Zn Constants Other –– Function MPS (1) Stores the memory of the operation result (ON or OFF) immediately prior to the MPS instruction. (2) Up to 16 MPS instructions can be used successively.
MPS,MRD,MPP 1. The following shows ladders both using and not using the MPS, MRD, and MPP instructions. Ladder Using the MPS, MRD and MPP Instruction Ladder not Using MPS, MRD, and MPP Instructions X0 X1 X2 X3 X5 Y10 X4 Y11 Y12 X0 X1 X2 X0 X1 X3 X0 X1 X5 1 2 Y10 X4 3 Y11 Y12 4 2. The MPS and MPP instructions must be used the same number of times. Failure to observe this will not correctly display the ladder in the ladder mode of the peripheral device.
MPS,MRD,MPP (2) A program using the MPS and MPP instructions successively.
INV 5.2.3 Operation results inversion (INV) 1 INV Basic High performance Process Redundant Universal 3 Command INV 2 4 Internal Devices Setting Data Bit Word –– R, ZR J Bit \ U Word \G Zn Constants Other –– 5 6 Function Inverts the operation result immediately prior to the INV instruction. 7 Operation Result Immediately Prior to the Operation Result Following the Execution of INV Instruction the INV Instruction OFF ON ON OFF 8 Operation Error 5.
INV 1. The INV instruction operates based on the results of calculation made until the INV instruction is given. Accordingly, use it in the same position as that of the AND instruction. The INV instruction cannot be used at the LD and OR positions. 2. When a ladder block is used, the operation result is inverted within the range of the ladder block. To operate a ladder using the INV instruction in combination with the ANB instruction, pay attention to the range that will be inverted.
MEP,MEF 5.2.4 Operation result conversions (MEP,MEF) 1 MEP,MEF Basic High performance Process Redundant Universal 2 MEP MEF Command 3 Command 4 Internal Devices Setting Data Bit –– Word R, ZR J Bit \ U Word \G Zn Constants Other 5 –– 6 Function MEP (1) If operation results up to the MEP instruction are leading edge (from OFF to ON), goes ON (continuity status).
EGP,EGF 5.2.5 Pulse conversions of edge relay operation results (EGP,EGF) EGP,EGF Basic EGP EGF D Setting Data D Command D Command D Process Redundant Universal : Edge relay number where operation results are stored (bits) Internal Devices Bit High performance Word R, ZR J Bit \ Word U \G Zn Constants Other V –– Function EGP (1) Operation results up to the EGP instruction are stored in memory by the edge relay (V).
EGP,EGF Program Example 1 (1) A program using the EGP instruction in the subroutine program using the EGD instruction [Ladder Mode] [List Mode] Step 2 Instruction Device 3 4 5 6 7 [Operation] END processing (1) (2) (1) (2) (1) (2) (1) (2) (1) 8 (2) ON ON OFF X0 OFF ON Turns OFF as X0 remains ON. ON ON V0 OFF V1 OFF Turns ON at the leading ON edge of X0. Turns OFF as X1 remains ON. Turns ON at the leading edge of X1. D0 2 1 1 D1 1.
OUT 5.3 Output Instructions 5.3.1 Out instruction (excluding timers, counters, and annunciators) (OUT) OUT Basic High performance Process Redundant Universal Bit device number ( D ) Command Y35 OUT Word device bit designation ( D ) Command D0.
OUT Program Example 1 (1) When using bit devices [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 (2) When bit designation has been made for word device [Ladder Mode] 5 [List Mode] Step Instruction Device 6 7 8 b15 b7 b6 b5 b0 D0 5.3 Output Instructions 5.3.
OUT T,OUTH T 5.3.2 Timers (OUT T,OUTH T) OUT T,OUTH T Basic Command OUT T Command Set value Setting in the range from 1 to 32767 is valid. D10 Set value Data register value in the range from 1 to 32767 is valid. T0 Set value Setting in the range from 1 to 32767 is valid. H K50 Command T0 OUTH T (High-speed timer) Command H D10 Set value Data register value in the range from 1 to 32767 is valid. T0 K50 Command Set value Setting in the range from 1 to 32767 is valid.
OUT T,OUTH T (2) The contact responds as follows when the operation result up to the OUT instruction is a change from ON to OFF: Type of Timer Timer Coil Low speed timer Present Value of After Time Up 1 Timer A Contact B Contact A Contact B Contact 0 Non-continuity Continuity Non-continuity Continuity 2 Non-continuity Continuity Continuity Non-continuity 3 OFF High speed timer Prior to Time Up Low speed retentive timer OFF High speed Maintains the present value retentive timer
OUT T,OUTH T Caution (1) When creating a program in which the operation the timer contact triggers the operation of other timer, create the program for the timer that operates later first. In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate. • If the set value is smaller than a scan time. • If "1" is set Example • For timers T0 to T2, the program is created in the order the timer operates later.
OUT T,OUTH T Program Example 1 (1) The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON. [Ladder Mode] [List Mode] *3 Step 2 Instruction Device 3 4 5 *3: The setting value of the low-speed timer indicates its default time limit (100 ms). (2) The following program uses the BCD data at X10 to X1F as the timer's set value. 6 [Ladder Mode] Converts the BCD data at X10 to X1F to BIN and stores the converted value at D10.
OUT C 5.3.3 Counter (OUT C) OUT C Basic Command High performance K50 Set value Setting in the range from 1 to 32767 is valid. D10 Set value Data register value in the range from 1 to 32767 is valid.
OUT C Operation Error 1 (1) There are no operation errors associated with the OUT C instruction. 2 Program Example (1) The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter when X1 goes ON. [Ladder Mode] 3 [List Mode] Step Instruction 4 Device 5 6 (2) The following program sets the value for C10 at 10 when X0 goes ON, and at 20 when X1 goes ON. 7 [Ladder Mode] 8 Stores 10 at D0 when X0 goes ON. Stores 20 at D0 when X1 goes ON. 5.3 Output Instructions 5.3.
OUT F 5.3.4 Annunciator output (OUT F) OUT F Basic High performance Process Redundant Universal Annunciator number Command OUT F F35 D Setting Data D : Number of the annunciator to be turned ON (bits) Internal Devices Bit Word R, ZR J Bit \ Word U \G Zn Constants Other –– (Only F) Function (1) Operation results up to the OUT instruction are output to the designated annunciator. (2) The following responses occur when an annunciator (F) is turned ON. • The "USER"/"ERR." LED goes ON.
OUT F Operation Error 1 (1) There are no operation errors associated with the OUT F instruction. 2 Remark 1. For details of annunciators, refer to the User's Manual (Functions Explanation, Program Fundamentals) for the CPU module used. 2. The number of basic steps for the OUT module F instruction is 2. 3. The table below shows which CPU module features either the LED display device on front of the CPU module or "USER" LED. Type of LED "USER" LED "ERR.
SET 5.3.
SET Operation Error 1 (1) There are no operation errors associated with the SET instruction. 2 Program Example (1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON. [Ladder Mode] [List Mode] Step 3 4 Instruction Device 5 6 (2) The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit value to 0 when X9 goes ON. [Ladder Mode] [List Mode] Step Instruction Device 7 8 Sets b5 of D0 at 1. Sets b5 of D0 at 0. 5.
RST 5.3.
RST Operation Error 1 (1) There are no operation errors associated with the RST instruction. 2 Remark The basic number of steps of the RST instruction is as follows.
RST (2) The following program resets the 100 ms retentive timer and counter. [Ladder Mode] When ST225 is set as retentive timer, it is turned ON when X4 ON time reaches 30 min. Counts the number of times ST225 was turned ON. Resets the coil, contact and present value of ST225 when the contact of ST225 is turned ON. Y55 goes ON at the count-up of C23. Resets C23 to 0 when X5 is turned ON.
SET F,RST F 5.3.
SET F,RST F (3) When the value of SD63 is "16", the annunciator numbers are deleted from SD64 to SD79 by the use of the RST instruction. If the annunciators whose numbers are not registered in SD64 to SD79 are ON, these numbers will be registered. If all annunciator numbers from SD64 to SD79 are turned OFF, the LED display device on the front of the CPU module, or the "USER" LED, will be turned OFF.*2 *2: When using the Basic model QCPU, the "ERR." LED goes OFF.
PLS,PLF 5.3.
PLS,PLF (3) When designating a latch relay (L) for the execution command and turning the power supply OFF to ON with the latch relay ON, the execution command turns OFF to ON at the first scan, executing the PLS instruction and turning ON the designated device. The device turned ON at the first scan after power-ON turns OFF at the next PLS instruction.
PLS,PLF (2) The following program executes the PLF instruction when X9 goes OFF. [Ladder Mode] 1 [List Mode] Step Instruction Device 2 3 [Timing Chart] ON X9 OFF 4 ON M9 OFF 1 scan 5 6 7 8 5.3 Output Instructions 5.3.
FF 5.3.9 Bit device output reverse (FF) FF Basic High performance Process Redundant Universal Command FF FF D Setting Data D : Device number of the device to be reversed (bits) Internal Devices Bit Word R, ZR J \ Bit U Word Zn \G Constants Other DY –– D Function (1) Reverses the output status of the device designated by turned OFF ON.
FF (2) The following program reverses b10 (bit 10) of D10 when X0 goes ON. [Ladder Mode] [List Mode] Step 1 Instruction Device 2 3 [Timing Chart] ON X0 D10 of b10 OFF 4 0 1 0 5 6 7 8 5.3 Output Instructions 5.3.
DELTA(P) 5.3.10 Pulse conversions of direct outputs (DELTA(P)) DELTA(P) Basic High performance Process Redundant Universal Command DELTA DELTA D DELTAP D Command DELTAP D : Bit for which pulse conversion is to be conducted (bits) Internal Devices Setting Data Bit Word J R, ZR Bit \ U Word \G Zn Constants Other DY –– D Function (1) Conducts pulse output of direct access output (DY) designated by D .
DELTA(P) Program Example 1 (1) The following program presets CH1 of the AD61 mounted at slot 0 of the main base unit, when X20 goes ON. [Ladder Mode] Stores preset value (0) at addresses 1 and 2 of the AD61 buffer memory. 2 3 Outputs the preset command. 4 [List Mode] Step 5 Instruction Device 6 7 8 5.3 Output Instructions 5.3.
SFT(P) 5.4 Shift Instructions 5.4.
SFT(P) (2) When word device bit designation is used the 1/0 status of the bit immediately prior to 1 the one designated by D , and turns the prior bit to 0. For example, if D0.5 (bit 5 [b5] of D0) has been designated by the SFT instruction, when the SFT instruction is executed, it will shift the 1/0 status of b4 of D0 to b5, and turn b4 to 0.
SFT(P) Program Example (1) The following program shifts Y57 to Y5B when X8 goes ON. [Ladder Mode] Executes shift for Y57 to Y5B when X8 goes ON. Start programming from the device having a large number. Turns Y57 ON when X7 goes ON.
MC,MCR 5.5 Master Control Instructions 1 5.5.
MC,MCR MC (1) If the execution command of the MC instruction is ON when master control is started, the result of the operation from the MC instruction to the MCR instruction will be exactly as the instruction (ladder) shows. If the execution command of the MC instruction is OFF, the result of the operation from the MC instruction to the MCR instruction will be as shown below: Device Device Status High speed timer Count value goes to 0, coils and contacts all go OFF.
MC,MCR Program Example 1 The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N). Nesting can be performed from N0 to N14. The use of nesting enables the creation of ladders which successively limit the execution condition of the program. 3 A ladder using nesting would appear as shown below: [Ladder as displayed in the GPP ladder mode] A MC N0 M15 NO M15 B 4 A MC N0 M15 B MC N2 M17 C MCR N2 5 Executed when A and B are ON.
MC,MCR Cautions when Using Nesting Architecture (1) Nesting can be used up to 15 times (N0 to N14) When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and from the higher to the lower order with the MCR instruction. If this order is reversed, there will be no nesting architecture, and the CPU module will not be capable of performing correct operations.
FEND 5.6 Termination Instructions 1 5.6.
FEND Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The FEND instruction is executed after the execution of the CALL, FCALL, ECALL, or EFCALL instruction, and before the execution of the RET instruction. (Error code: 4211) • The FEND instruction is executed after the execution of the FOR instruction, and before the execution of the NEXT instruction.
END 5.6.2 End sequence program (END) 1 END Basic High performance Process Redundant Universal 2 3 4 5 END END 6 Setting Data Internal Devices Bit Word J R, ZR Bit –– \ U Word \G Zn Constants Other 7 –– Function 8 (1) Indicates termination of programs, including main routine program, subroutine program, and interrupt programs. 0 Sequence program END (2) The END instruction cannot be used during the execution of the main sequence program.
END (4) The use of the END and FEND instructions is broken down as follows for main routine programs, subroutine programs, and interrupt programs: Main routine program FEND (FEND instruction is necessary.) Subroutine program Main sequence program area Interrupt program END (END instruction is necessary.) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
STOP 5.7 Other instructions 5.7.1 1 Sequence program stop (STOP) 2 STOP Basic High performance Process Redundant Universal 3 4 Command STOP STOP 5 Setting Data Internal Devices Bit Word R, ZR J Bit \ U Word –– Zn \G Constants Other –– 6 7 Function (1) Resets the output (Y) and stops the CPU module operation when the execution command is turned ON. 8 (The same result will take place if the RUN/STOP (key) switch is turned to the STOP setting.
STOP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The STOP instruction was executed before the execution of the RET instruction and after the execution of the CALL/FCALL/ECALL/EFCALL/XCALL instruction. (Error code: 4211) • The STOP instruction was executed before the execution of the NEXT instruction and after the execution of the FOR instruction.
NOP,NOPLF,PAGE n 5.7.2 No operations (NOP,NOPLF,PAGE n) 1 NOP,NOPLF,PAGE n Basic High performance Process Redundant Universal 2 3 In the ladder display, NOP is not displayed. Command NOP NOP 4 NOPLF NOPLF PAGE n PAGE n Setting Data Internal Devices Bit Word R, ZR J Bit –– \ U Word \G Zn Constants 5 Other –– 6 7 Function 8 NOP (1) This is a no operation instruction that has no impact on any operations up to that point. (a) To insert space for sequence program debugging.
NOP,NOPLF,PAGE n PAGE n (1) This is a no operation instruction that has no impact on any operations up to that point. (2) No processing is performed at peripheral devices with this instruction. Operation Error (1) There are no errors associated with the NOP, NOPLF, or PAGE instruction. Program Example NOP (1) Contact closed.... Deletes the AND or ANI instruction.
NOP,NOPLF,PAGE n [Ladder Mode] [List Mode] 1 Before change Step Instruction Device 2 Changing to LD T3 Changing to NOP 3 4 After change Step Instruction Device 5 6 7 NOPLF [Ladder Mode] [List Mode] Step Instruction 8 Device 5.7 Other instructions 5.7.
NOP,NOPLF,PAGE n • Printing the ladder will result in the following: 0 X0 MOV K1 D30 MOV K2 D40 5 NOPLF instruction, inserted as a delimiter of ladder blocks, causes print out page to be changed forcibly. NOPLF X1 6 Y40 8 END • Printing an instruction list with the NOPLF instruction will result in the following: 0 LD X0 1 MOV K1 D30 3 MOV K2 D40 5 NOPLF 6 LD X1 7 OUT Y40 8 END Changes print output page after printing NOPLF.
6 7 BASIC INSTRUCTIONS 7 7 7 7 6 Category Comparison operation instruction Arithmetic operation instruction Processing Details Compares data to data. Adds, subtracts, multiplies, divides, increments, or decrements data with other data. Section Section 6.2 Converts data types. Section 6.3 Data transfer instruction Transmits designated data. Section 6.4 Program branch instruction Program jumps. Section 6.5 Program run control instruction Enables and disables program interrupts. Section 6.
=,<>,>,<=,<,>= 6.1 Comparison Operation Instructions 6.1.1 BIN 16-bit data comparisons (=,<>,>,<=,<,>=) =,<>,>,<=,<,>= Basic High performance indicates an instruction symbol of LD S1 S2 S1 S2 S1 S2 Process Redundant Universal / / / / .
=,<>,>,<=,<,>= Operation Error 1 (1) There are no operation errors associated with the , , , , , or instruction. 2 Program Example (1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical. [Ladder Mode] 3 [List Mode] Step Instruction 4 Device 4 (2) The following program compares BIN value K100 to the data at D3, and establishes continuity if the data in D3 is something other than 100.
D=,D<>,D>,D<=,D<,D>= 6.1.2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) D=,D<>,D>,D<=,D<,D>= Basic High performance indicates an instruction symbol of D / D LD S1 S2 S1 S2 S1 S2 Process Redundant Universal /D /D /D / D .
D=,D<>,D>,D<=,D<,D>= Operation Error 1 (1) There are no operation errors associated with the D , D instruction. ,D ,D ,D or D 2 Program Example 3 (1) The following program compares the data at X0 to X1F with the data at D3 and D4, and turns Y33 ON, if the data at X0 to X1F and the data at D3 and D4 match.
E=,E<>,E>,E<=,E<,E>= 6.1.3 Floating decimal point data comparisons (Single precision) (E=,E<>,E>,E<=,E<,E>=) E=,E<>,E>,E<=,E<,E>= Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of E / E LD S1 S2 S1 S2 S1 S2 /E /E /E .
E=,E<>,E>,E<=,E<,E>= Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is 0. *1 (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *1: There are CPU modules that will not result in an operation error if Section 3.2.4. 0 is specified.
ED=,ED<>,ED>,ED<=,ED<,ED>= 6.1.
ED=,ED<>,ED>,ED<=,ED<,ED>= Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: 0,2 -1022 | value of specified device | < • The value of the designated device is (Error code: 4140) 0.
ED=,ED<>,ED>,ED<=,ED<,ED>= Caution (1) Since the number of digits of the real number that can be input by GX Developer is up to 15 digits, the comparison with the real number whose number of significant digits is 16 or more cannot be made by the instruction shown in this section. When judging match/mismatch with the real number whose significant digits is 16 or more by the instruction in this section, compare it with the approximate values of the real number to be compared and judge by the sizes.
$=,$<>,$>,$<=,$<,$>= 6.1.5 Character string data comparisons ($=,$<>,$>,$<=,$<,$>=) 1 $=,$<>,$>,$<=,$<,$>= Basic indicates an instruction symbol of $ LD S1 S2 S1 S2 High performance /$ Process Redundant Universal /$ / $ /$ / $ .
$=,$<>,$>,$<=,$<,$>= (b) If the character strings are different, the character string with the larger character code will be the larger.
$=,$<>,$>,$<=,$<,$>= Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The code "00H" does not exist within the range of the relevant device, starting from the device number designated by S1 and S2 . 2 (Error code: 4101) (Error code: 4101) 3 The character string data comparison instruction checks the device range while comparing the designated character string data.
$=,$<>,$>,$<=,$<,$>= (3) The following program compares the character string stored following D10 with the character string stored following D100. [Ladder Mode] [List Mode] Step Instruction Device (4) The following program compares the character string stored following D200 with the character string "12345".
BKCMP
,BKCMP
P 6.1.6 BIN block data comparisons (BKCMP
,BKCMP
P) 1 BKCMP
,BKCMP
P Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of / / / / .
BKCMP
,BKCMP
P (4) The results of the comparison operations for the individual instructions are as follows: Instruction Condition Symbols BKCMP= S2 BKCMP<> = S1 BKCMP<= > S1 BKCMP>= Symbols BKCMP= S1 BKCMP<> BKCMP> S2 ON (1) BKCMP<= S2 S1 BKCMP< Instruction S2 S1 BKCMP> Comparison Operation Result < S1 BKCMP< S2 BKCMP>= S2 (5) If all comparison results stored n points from signal) goes ON.
BKCMP
,BKCMP
P (2) The following program compares, when X1C is turned ON, the constant K1000 with the data stored at D10 to D13, and stores the operation result at b4 to b7 in D0.
BKCMP
,BKCMP
P 6.1.7 BIN 32-bit block data comparisons (DBKCMP
,DBKCMP
P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of / / / / / .
BKCMP
,BKCMP
P (2) The comparison operation is executed in 32-bit units. (3) The constant in the device specified by (BIN 32-bit data).
BKCMP
,BKCMP
P Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • A negative value is specified for n. (Error code: 4100) • The range of the n-point devices starting from the device specified by S1 , S2 . or D exceeds the specified device range.
BKCMP
,BKCMP
P When certain bits are specified in a word device, bits other than the certain bits that store the operation result do not change. D10.F Before execution 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 D10.0 0 D10.F 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 D10.
+(P),-(P) 6.2 Arithmetic Operation Instructions 6.2.1 BIN 16-bit addition and subtraction operations (+(P),-(P)) +(P),-(P) Basic When two data are set ( D + S D , - D D S High performance Process Redundant Universal ) indicates an instruction symbol of +/ .
+(P),-(P) – (1) Subtracts 16-bit BIN data designated by D from 16-bit BIN data designated by stores the result of the subtraction at the device designated by D b15 S b0 5678 (BIN) (2) Values for S and D b15 D S 1 and . 2 D b0 1234 (BIN) can be designated between b15 b0 4444 (BIN) 3 32768 and 32767 (BIN, 16 bits). (3) The judgment of whether data is positive or negative is made by the most significant bit (b15).
+(P),-(P) When three data are set ( S1 + S2 D , S1 - S2 D ) indicates an instruction symbol of +/ .
+(P),-(P) – (1) Subtracts 16-bit BIN data designated by S1 from 16-bit BIN data designated by stores the result of the subtraction at the device designated by S1 b15 5678 (BIN) (2) Values for S1 , S2 D 1 and . 2 D S2 b0 D S2 b15 b0 b15 1234 (BIN) and can be designated between b0 4444 (BIN) D 32768 and 32767 (BIN, 16 bits). (3) The judgment of whether data is positive or negative is made by the most significant bit (b15).
D+(P),D-(P) 6.2.2 BIN 32-bit addition and subtraction operations (D+(P),D-(P)) D+(P),D-(P) Basic When two data are set (( D +1, D )+( +1, S S ) ( D +1, D ), ( D High performance +1, D )-( Process Redundant Universal S +1, ) ( S D +1, D )) indicates an instruction symbol of D+/D .
D+(P),D-(P) D(1) Subtracts 32-bit BIN data designated by D from 32-bit BIN data designated by stores the result of the subtraction at the device designated by D D +1 b31 b16 b15 b0 567890 (BIN) (2) The values for (BIN 32 bits). S and D S +1 D +1 S b31 b16 b15 b0 123456 (BIN) D S 1 and . 2 D b31 b16 b15 b0 444434 (BIN) can be designated at between 2147483648 and 2147483647 (3) Judgment of whether the data is positive or negative is made on the basis of the most significant bit (b31).
D+(P),D-(P) When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D )) indicates an instruction symbol of D+/ D .
D+(P),D-(P) D(1) Subtracts 32-bit BIN data designated by from 32-bit BIN data designated by S1 stores the result of the subtraction at the device designated by S1 +1 S1 S2 b31 b16 b15 b0 567890 (BIN) (2) The values for (BIN 32 bits). S1 , S2 and D +1 D +1 S2 b31 b16 b15 b0 123456 (BIN) D S2 1 and .
*(P),/(P) 6.2.3 BIN 16-bit multiplication and division operations (*(P),/(P)) *(P),/(P) Basic High performance Process Redundant Universal indicates an instruction symbol of * , / .
*(P),/(P) / (1) Divides BIN 16-bit data designated by and BIN 16-bit data designated by S1 the result in the device designated by D S1 S2 b0 5678 (BIN) , and stores D b0 b15 1234 (BIN) 2 Remainder D 1 b15 b0 b15 b0 742 (BIN) 4 (BIN) (2) If a word device has been used, the result of the division operation is stored as 32 bits, and both the quotient and remainder are stored; if a bit device has been used, 16 bits are used and only the quotient is stored. Quotient: Stored at the lower 16 bits.
D*(P),D/(P) 6.2.4 BIN 32-bit multiplication and division operations (D*(P),D/(P)) D*(P),D/(P) Basic High performance Process Redundant Universal indicates an instruction symbol of D * D/ .
D*(P),D/(P) D/ (1) Divides BIN 32-bit data designated by the result in the device designated by S1 S1 S2 b31 b16 b15 b0 567890 (BIN) and BIN 32-bit data designated by S1 D S2 , and stores . D S2 b31 b16 b15 b0 123456 (BIN) D b31 b16 b15 4 (BIN) D 2 D b0 b31 b16 b15 b0 74066 (BIN) (2) With a word device, the division operation result is stored in 64 bits and both the quotient and remainder are stored. With a bit device, only the quotient is stored as the operation result in 32 bits.
B+(P),B-(P) 6.2.5 BCD 4-digit addition and subtraction operations (B+(P),B-(P)) B+(P),B-(P) B+(P), B-(P) High performance Basic When two data are set ( D + S D , D - D S Process Redundant Universal ) indicates an instruction symbol of B+/B .
B+(P), B-(P) (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. 0 0 0 1 0 0 1 0 3 9 9 9 8 2 Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The S or D BCD data is outside the 0 to 9999 range.
B+(P), B-(P) When three data are set ( S1 + S2 D , S1 - S2 ) D indicates an instruction symbol of B+/B- .
B+(P), B-(P) (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. 0 0 0 1 0 0 1 0 3 9 9 9 8 2 Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The S1 , S2 D or BCD data is outside the 0 to 9999 range.
DB+(P),DB-(P) 6.2.6 BCD 8-digit addition and subtraction operations (DB+(P),DB-(P)) DB+(P),DB-(P) High performance Basic When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, Process Redundant Universal )-( D S +1, S ) ( D +1, )) D indicates an instruction symbol of DB+/DB- . Command DB+, DB- S D S D Command DB+P.
DB+(P),DB-(P) (2) 0 to 99999999 (BCD 8 digits) can be assigned to S and D . (3) The following will result if an underflow is generated by the subtraction operation: The carry flag in this case does not go ON. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 9 9 9 9 9 9 9 9 1 2 Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The S or D BCD data is outside the 0 to 99999999 range.
DB+(P),DB-(P) When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, indicates an instruction symbol of DB+/ DB D )) .
DB+(P),DB-(P) DB(1) Subtracts the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by and stores the result of the subtraction at the device designated by S1 +1 S1 (Upper 4 digits) (Lower 4 digits) 5 6 7 8 9 1 2 3 S2 +1 D +1 S2 (Upper 4 digits) (Lower 4 digits) S2 , . D 2 D (Upper 4 digits) (Lower 4 digits) 0 1 2 3 4 5 6 7 5 5 5 5 4 5 5 6 3 Digits exceeding the designated number of digits are assumed to be 0.
B*(P),B/(P) 6.2.7 BCD 4-digit multiplication and division operations (B*(P),B/(P)) B*(P),B/(P) Basic High performance Process Redundant Universal indicates an instruction symbol of B * ,B/ .
B*(P),B/(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The or S1 S2 BCD data is outside the 0 to 9999 range. • Attempt to divide (Error code: 4100) by 0. S2 (Error code: 4100) 2 3 Program Example (1) The following program multiplies, when X20 is turned ON, the BCD data at X0 to XF by the BCD data at D8 and stores the operation result at D0 to D1.
DB*(P),DB/(P) 6.2.8 BCD 8-digit multiplication and division operations (DB*(P),DB/(P)) DB*(P),DB/(P) Basic High performance Process Redundant Universal indicates an instruction symbol of DB * ,DB/ .
DB*(P),DB/(P) (2) 64 bits are used for the result of the division operation, and stored as quotient and remainder. 1 Quotient (BCD 8 digits) :Stored at the lower 32 bits. Remainder (BCD 8 digits) :Stored at the upper 32 bits. (3) If D has been designated as a bit device, the remainder of the operation will not be stored. Operation Error 3 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
E+(P),E-(P) 6.2.9 Addition and subtraction of floating decimal point data (Single precision) (E+(P),E-(P)) E+(P),E-(P) Ver. High performance Basic Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D )) indicates an instruction symbol of E+/E- .
E+(P),E-(P) (2) Values which can be designated at 0, 2-126 S and D and which can be stored, are as follows: | Designated value (stored value) | < 2128 1 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
E+(P),E-(P) When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D D indicates an instruction symbol of E+/E-.
E+(P),E-(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range: 0, 2-126 | Contents of designated device | < 2128 (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) • The value of the specified device is 0.
ED+(P),ED-(P) 6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P)) ED+(P),ED-(P) Basic When two data are set (( ( +3, D D +2, D +1, D )-( D S +3, +3, D S +2, +2, D S +1, +1, Process Redundant Universal )+( S +3, S +2, S +1, S ) ( ) ( D +3, D +2, D +1, D S High performance D D +3, D +2, D +1, D ), )) indicates an instruction symbol of ED+/ED-.
ED+(P),ED-(P) ED(1) Subtracts a 64-bit floating decimal point type real number designated by floating decimal point type real number designated by designated by D and a 64-bit 1 , and stores the result at a device .
ED+(P),ED-(P) When three data are set(( S1 +3, S1 +2, S1 +1, S1 )+( S2 +3, S2 +2, S2 +1, S2 ) ( ( S1 +3, S1 +2, S1 +1, S1 )-( S2 +3, S2 +2, S2 +1, S2 ) ( D +3, +2, D D +1, D D +3, D +2, D +1, D ), )) indicates an instruction symbol of ED+/ED-.
ED+(P),ED-(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range: (Error code: 4140) 0, 2-1022 | Contents of designated device | < 21024 • The value of the specified device is 0.
E*(P),E/(P) 6.2.11 Multiplication and division of floating decimal point data (Single precision) (E*(P),E/(P)) E*(P),E/(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of E* , E/ .
E*(P),E/(P) (2) Values which can be designated at 0, 2-126 S1 , S2 and D and which can be stored, are as follows: 1 | Designated value (stored value) | < 2128 Operation Error 2 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
ED*(P),ED/(P) 6.2.12 Multiplication and division of floating decimal point data (Double precision) (ED*(P),ED/(P)) ED*(P),ED/(P) Basic High performance Process Redundant Universal indicates an instruction symbol of ED*, ED/.
ED*(P),ED/(P) ED/ (1) Divides the 64-bit floating decimal point real number designated by S1 by the 64-bit floating decimal point real number designated by S2 and stores the operation result at the device designated by D .
ED*(P),ED/(P) (2) The following program divides the 64-bit floating decimal point real numbers at D10 to D13 by the 64-bit floating decimal point real numbers at D20 to D23, and stores the result at D30 to D33. [Ladder Mode] [List Mode] Step Instruction [Operation] D13 D12 D11 D10 52171.39 6-58 D23 D22 D21 D20 9.73521 D33 D32 D31 D30 5359.
BK+(P),BK-(P) 6.2.13 Block addition and subtraction (BK+(P),BK-(P)) 1 BK+(P),BK-(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of BK+, BK- .
BK+(P),BK-(P) (4) The following will happen when an underflow or overflow is generated in an operation result: The carry flag in this case does not go ON. K32767 +K2 (7FFFH) (0002H) K 32767 (8001H) K 32767 +K 2 (8001H) (FFFEH) K32767 (7FFFH) BK(1) Subtracts n points of BIN data from the device designated by from the device designated by onward.
BK+(P),BK-(P) Program Example 1 (1) The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the data stored at R0 to R3 and stores the operation result into the area starting from D200.
DBK+(P),DBK-(P) 6.2.14 BIN 32-bit data block addition and subtraction operations (DBK+(P),DBK-(P)) DBK+(P),DBK-(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of DBK+, DBK- .
DBK+(P),DBK-(P) When a constant is specified for S1 1, 3, 5, S1 n 1, S1 S1 S1 b31 b0 -30000 (BIN) 40000 (BIN) 2 -50000 (BIN) n 4 S1 S1 S1 S2 1, S2 S2 b31 b0 50000 (BIN) n 2 60000 (BIN) D D D D D D 1, 3, 5, D n 1, D b31 b0 20000 (BIN) 90000 (BIN) 2 0 (BIN) n 4 S2 2 n 2 110000 (BIN) 3 (2) Block addition is executed in 32-bit units. (3) The constant in the device specified by (BIN 32-bit data).
DBK+(P),DBK-(P) (6) The following will happen if an overflow occurs in an operation result: The carry flag in this case is not turned on. K 2147483647 K2147483647 K 2 (7FFFFFFFH) (00000002H ) ( 80000001H ) K2147483647 K 2147483647 K2 (80000001H) ( FFFFFFFEH ) ( 7FFFFFFFH ) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • A negative value is specified for n.
$+(P) 6.2.
$+(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The entire character string linked from the device number designated by D to the final device number of the relevant device cannot be stored. (Error code: 4101) • The storage device numbers for the character strings designated by • The character string of and S D exceeds 16383 characters. S and D overlap.
$+(P) When three data are set ( S1 + S2 D ) 1 Command $+ $+ S1 S2 D $+P S1 S2 D 2 Command $+P Setting Data 3 S1 : Data for linking or head number of the devices where the data for linking is stored (character string) S2 : Data to be linked or head number of the devices where the data to be linked is stored (character string) D : Head number of the devices where the linking result will be stored (character string) Internal Devices Bit Word R, ZR J Bit \ Word U Zn \G Constants
$+(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The entire character string linked from the device number designated by D to the final device number of the relevant device cannot be stored.
INC(P),DEC(P) 6.2.16 Incrementing and decrementing 16-bit BIN data (INC(P),DEC(P)) 1 INC(P),DEC(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of INC/DEC. 4 Command INC, DEC D 4 Command P INCP, DECP D Setting Data : Head number of devices for INC (+1)/DEC ( Internal Devices Bit Word J R, ZR 6 1) operation (BIN 16 bits) \ Bit D U Word Zn \G Constants Other 7 –– D 8 Function INC D (16-bit data).
INC(P),DEC(P) Program Example (1) The following program outputs the present value at the counter C0 to C20 to the area Y30 to Y3F in BCD, every time X8 is turned ON. (When present value is less than 9999) [Ladder Mode] Outputs the present value of C (D+Z1) to Y30 to Y3F in BCD. Executes Z1 + 1. Sets Z1 at "0" when Z1=21 or X7 (reset input) is ON. [List Mode] Step Instruction Device (2) The following is a down counter program. [Ladder Mode] Transfers 100 to D8 when X7 goes ON.
DINC(P),DDEC(P) 6.2.17 Incrementing and decrementing 32-bit BIN data (DINC(P),DDEC(P)) 1 DINC(P),DDEC(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of DINC/DDEC. 4 Command DINC, DDEC D 4 Command P DINCP, DDECP D Setting Data 6 : Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits) Internal Devices Bit D J R, ZR Word \ Bit U Word Zn \G Constants Other 7 –– D 8 Function DINC D +1 D (32-bit data).
DINC(P),DDEC(P) Program Example (1) The following program adds 1 to the data at D0 and D1 when X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device (2) The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4. [Ladder Mode] [List Mode] Step Instruction Device (3) The following program subtracts 1 from the data at D0 and D1 when X0 goes ON.
BCD(P),DBCD(P) 6.3 Data conversion instructions 6.3.1 1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD(P),DBCD(P)) 2 BCD(P),DBCD(P) BCD(P), DBCD(P) Basic High performance Process Redundant Universal 3 4 indicates an instruction symbol of BCD/DBCD.
BCD(P), DBCD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data of S is other than 0 to 9999 at BCD instruction. • The data of S or S (Error code: 4100) +1 is other than 0 to 99999999 at DBCD instruction. (Error code: 4100) Program Example (1) The following program outputs the present value of C4 from Y20 to Y2F to the BCD display device.
BIN(P),DBIN(P) 6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN(P),DBIN(P)) 1 BIN(P),DBIN(P) High performance Basic Process Redundant Universal 2 3 indicates an instruction symbol of BIN/DBIN.
BIN(P),DBIN(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • When values other than 0 to 9 are designated to any digits of S (Error code: 4100) When the QCPU is used, the error above can be suppressed by turning ON SM722. However, the instruction is not executed regardless of whether SM722 is turned ON or OFF if the designated value is out of the available range.
BIN(P),DBIN(P) (2) The following program converts the BCD data at X10 to X37 to BIN when X8 is ON, and stores it at D0 and D1.
FLT(P),DFLT(P) 6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (Single precision) (FLT(P),DFLT(P)) FLT(P),DFLT(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of FLT/DFLT.
FLT(P),DFLT(P) (3) Due to the fact that 32-bit floating decimal point type real numbers are processed by simple 32-bit processing, the number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal. 1 For this reason, if the integer exceeds the range of 16777216 to 16777215 (24-bit BIN value), errors can be generated in the conversion value.
FLT(P),DFLT(P) Program Example (1) The following program converts the BIN 16-bit data at D20 to a 32-bit floating decimal point type real number and stores the result at D0 and D1. [Ladder Mode] [List Mode] Step Instruction Device [Operation] D20 Integer conversion D1 15923 D0 15923 BIN value 32-bit floating-point real number (2) The following program converts the BIN 32-bit data at D20 and D21 to a 32-bit floating decimal point type real number, and stores the result at D0 and D1.
FLTD(P),DFLTD(P) 6.3.4 Conversion from BIN 16 and 32-bit data to floating decimal point (Double precision) (FLTD(P),DFLTD(P)) 1 FLTD(P),DFLTD(P) High performance Basic Process Redundant Universal 2 3 indicates an instruction symbol of FLTD/DFLTD.
FLTD(P),DFLTD(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The result exceeds the following range (Operation results in an overflow): 21024 | Operation result | (Error code: 4141) Program Example (1) The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point type real number and stores the result at D0 to D3.
INT(P),DINT(P) 6.3.5 Conversion from floating decimal point data to BIN16- and 32-bit data (Single precision) (INT(P),DINT(P)) 1 INT(P),DINT(P) Ver. High performance Basic Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of INT/DINT.
INT(P),DINT(P) (3) The integer value stored at D +1 and D is stored as BIN 32 bits. (4) After conversion, the first digit after the decimal point of the real number is rounded off. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
INT(P),DINT(P) (2) The following program converts the 32-bit floating decimal point type real number at D20 and D21 to BIN 32-bit data and stores the result at D0 and D1. [Ladder Mode] [List Mode] Step Instruction 1 Device 2 [Operation] D20 D21 -574968.321 Integer conversion 32-bit floating-point real number D1 D0 -574968 4 BIN value 32-bit floating-point real number D20 D21 2147483649.22 3 Integer conversion 4 An operation error occurs since "setting data > 2147483647." 6 7 8 6.
INTD(P),DINTD(P) 6.3.6 Conversion from floating decimal point data to BIN16- and 32-bit data (Double precision) (INTD(P),DINTD(P)) INTD(P),DINTD(P) High performance Basic Process Redundant Universal indicates an instruction symbol of INTD/DINTD.
INTD(P),DINTD(P) (2) The range of 64-bit floating decimal point type real numbers that can be designated at S +3, S +2, S +1 or S is from (3) The integer value stored at D 2147483648 to 2147483647. +1 and D 1 is stored as BIN 32 bits. (4) The converted data is the value rounded 64-bit floating-point real number to the first digit after the decimal point.
DBL(P) 6.3.
WORD(P) 6.3.
GRY(P),DGRY(P) 6.3.9 Conversion from BIN 16 and 32-bit data to Gray code (GRY(P),DGRY(P)) GRY(P),DGRY(P) Basic High performance Process Redundant Universal indicates an instruction symbol of GRY, DGRY.
GRY(P),DGRY(P) Operation Error 1 (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data at S is a negative number. (Error code: 4100) Program Example 3 (1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200.
GBIN(P),DGBIN(P) 6.3.10 Conversion of Gray code to BIN 16 and 32-bit data (GBIN(P),DGBIN(P)) GBIN(P),DGBIN(P) Basic High performance Process Redundant Universal indicates an instruction symbol of GBIN/DGBIN.
GBIN(P),DGBIN(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Data at S • Data at S when the GBIN instruction was issued is outside the 0 to 32767 range. (Error code: 4100) when the DGBIN instruction was issued is outside the 0 to 2147483647 range. (Error code: 4100) (1) The following program converts the Gray code data at D100 when X10 is ON to BIN data, and stores the result at D200.
NEG(P),DNEG(P) 6.3.11 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG(P),DNEG(P)) NEG(P),DNEG(P) High performance Basic Process Redundant Universal indicates an instruction symbol of NEG/DNEG.
NEG(P),DNEG(P) DNEG (1) Reverses the sign of the 32-bit device designated by by D D and stores at the device designated 1 . 2 32 bit b31 1 1 Before execution D 1 Sign conversion - 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 b0 0 0 b31 0 0 After execution D 1 b0 0 0 0 0 0 0 0 1 0 1 1 -218460 3 4 218460 4 (2) Used when reversing positive and negative signs.
ENEG(P) 6.3.12 Floating-point sign invertion (Single precision) (ENEG(P)) ENEG(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
EDNEG(P) 6.3.
BKBCD(P) 6.3.
BKBCD(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device n points from a device designated by relevant device. • The data n points from the device designated by • The S and D S , D or exceeds the (Error code: 4101) is outside the 0 to 9999 range. (Error code: 4100) S devices overlap.
BKBIN(P) 6.3.
BKBIN(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The n-bit range from the • The data n points at the S S , D , or device exceeds the range of that device. (Error code: 4101) device is outside the 0 to 9999 range. (Error code: 4100) • The S and D devices overlap.
ECON(P) 6.3.
ECON(P) Program Example 1 (1) The program which converts 32-bit floating-point real number of the devices, D10 to D11, into 64-bit floating-point real number when X0 turns ON, and outputs the conversion result to the devices, D0 to D3. [Ladder Mode] 2 [List Mode] Step Instruction Device 3 4 4 6 7 8 6.3 Data conversion instructions 6.3.
EDCON(P) 6.3.
EDCON(P) Program Example 1 (1) The program which converts 64-bit floating-point real number of the devices, D10 to D13, into 32-bit floating-point real number when X0 turns ON, and outputs the conversion result to the devices, D0 to D1. [Ladder Mode] 2 [List Mode] Step Instruction Device 3 4 4 6 7 8 6.3 Data conversion instructions 6.3.
MOV(P),DMOV(P) 6.4 Data Transfer Instructions 6.4.1 16-bit and 32-bit data transfers (MOV(P),DMOV(P)) MOV(P),DMOV(P) Basic High performance Process Redundant Universal indicates an instruction symbol of MOV/DMOV.
MOV(P),DMOV(P) Program Example 1 (1) The following program stores input data from X0 to XB at D8. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 (2) The following program stores the constant K155 at D8 when X8 goes ON. [Ladder Mode] 4 [List Mode] Instruction Step Device 4 009BH 6 b8b7 b15 b0 D8 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 (3) The following program stores the data from D0 and D1 at D7 and D8.
EMOV(P) 6.4.2 Floating-point data transfer (Single precision) (EMOV(P)) EMOV(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
EMOV(P) Program Example 1 (1) The following program stores the real numbers at D10 and D11 at D0 and D1. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 [Operation] D11 D10 36.475 D1 4 D0 36.475 (2) The following program stores the real number [Ladder Mode] 4 1.23 at D10 and D11 when X8 is ON. [List Mode] Step Instruction 6 Device 7 [Operation] D11 1.23 D10 8 1.23 6.4 Data Transfer Instructions 6.4.
EDMOV(P) 6.4.
EDMOV(P) Program Example 1 (1) The following program stores the 64-bit floating decimal point type real number at D10 to D13 at D0 to D3. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 [Operation] D13 D12 D11 D10 36.475 D3 D2 D1 D0 36.475 (2) The following program stores the real number [Ladder Mode] 4 1.23 at D10 to D13 when X8 is ON. 6 [List Mode] Step Instruction Device 7 [Operation] 8 D13 D12 D11 D10 6.4 Data Transfer Instructions 6.4.
$MOV(P) 6.4.
$MOV(P) (3) If the "00H" code is being stored at lower bytes of higher bytes and the lower bytes of S S +1 S +2 b15 b8 b7 b0 42 H (B) 41 H (A) 44 H (D) 43 H (C) 45 H (E) 00 H D D D +1 D +2 Upper byte is not transferred. S +n, "00H" will be stored at both the +n. 1 b15 b8 b7 b0 42 H (B) 41 H (A) 44 H (D) 43 H (C) 00 H 00 H 2 At the upper byte position, "00H" is automatically stored.
CML(P),DCML(P) 6.4.5 16-bit and 32-bit negation transfers (CML(P),DCML(P)) CML(P),DCML(P) High performance Basic Process Redundant Universal indicates an instruction symbol of CML, DCML.
CML(P),DCML(P) Program Example 1 (1) The following program inverts the data from X0 to X7, and transfers result to D0. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 [Operation] 4 If "Number of bits of S < Number of bits of D " X7 X0 11010000 These bits are all regarded as 0. 4 b0 b15 b8 b7 D0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 6 (2) The following program inverts the data at M16 to M23, and transfers the result to Y40 to Y47.
CML(P),DCML(P) (4) The following program inverts the data at X0 to X1F, and transfers results to D0 and D1. [Ladder Mode] [List Mode] Device Instruction Step [Operation] If "Number of bits of S < Number of bits of D " X1B These bits are all regarded as 0. X8 X7 0100 b31 b28 b27 X0 011100101100 b24 b8 b7 D0, 1 1 1 1 1 1 0 1 1 b0 100011010011 (5) The following program inverts the data at M16 to M35, and transfers it to Y40 to Y63.
BMOV(P) 6.4.
BMOV(P) Example Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000 (source) to R10 (block No.1 of the destination). • ZR transfer range (30000) to (30000+10000-1) • R transfer range (10+(1 32768)) to (10+(1 (30000) to (39999) 32768)+10000-1) (32778) to (42777) Therefore, the range 32778 to 39999 overlaps and the data is not correctly transferred. Source of transfer Destination of transfer ZR0 R0 Overlapped Block No.
BMOV(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device range of n points from or S D exceeds the corresponding device range. (Error code: 4101) 2 3 Program Example (1) The following program outputs the lower 4 bits of data at D66 to D69 to Y30 to Y3F in 4-point units.
FMOV(P) 6.4.
FMOV(P) (4) Selection whether to check a device range Whether to check a device range during execution of the FMOV instruction can be selected with the device range check inhibit flag (SM237) (only when the conditions for subset processing are established). While SM237 is ON, whether D to D + (n) - 1 is within the device range or not is not checked. For details of SM237, refer to Appendix 3 SPECIAL RELAY LIST.
DFMOV(P) 6.4.8 Identical 32-bit data block transfers (DFMOV(P)) DFMOV(P) Ver. Basic High performance Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
DFMOV(P) (3) If D specifies data of a device with digit specification, the amount of data stored in the device specified by If K5Y0 is specified by object. If both and S specified by D D 1 will be transferred. D D , the lower 20 bits of the word device specified by will be the S 2 specify data of a device with digit specification, the amount of data will be transferred regardless of the number of digits.
XCH(P),DXCH(P) 6.4.9 16-bit and 32-bit data exchanges (XCH(P),DXCH(P)) XCH(P),DXCH(P) Basic High performance Process Redundant Universal indicates an instruction symbol of XCH, DXCH.
XCH(P),DXCH(P) Operation Error 1 (1) There are no errors associated with the XCH (P) and DXCH (P) instruction. 2 Program Example (1) The following program exchanges the present value of T0 with the contents of D0 when X8 goes ON. [Ladder Mode] 3 [List Mode] Instruction Step 4 Device 4 (2) The following program exchanges the contents of D0 with the data from M16 to M31 when X10 goes ON.
BXCH(P) 6.4.
BXCH(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device of n points from a device designated by relevant device. • The D1 and D2 D1 , D2 devices overlap. or exceeds the (Error code: 4101) (Error code: 4101) Program Example 3 4 (1) The following program exchanges 16-bit data for 3 points from D200 for 16-bit data for 3 points from R0 when X1C goes ON.
SWAP(P) 6.4.11 Upper and lower byte exchanges (SWAP(P)) SWAP(P) Basic High performance Process Redundant Universal Command SWAP SWAP D SWAPP D Command SWAPP D : Head number of the devices where the data is stored (BIN 16 bits) Internal Devices Setting Data Bit R, ZR Word J \ Bit Word U \G Zn Constants Other –– D Function (1) Exchanges the higher and lower 8 bits of the device designated by b15 D b8 b7 b4 b3 .
CJ,SCJ,JMP 6.5 Program Branch Instructions 6.5.
CJ,SCJ,JMP JMP (1) Unconditionally executes program of designated pointer number within the same program file. Note the following points when using the jump instruction. 1. After the timer coil has gone ON, accurate measurements cannot be made if there is an attempt to jump the timer of a coil that has been turned ON using the CJ, SCJ or JMP instructions. 2. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump to the OUT instruction. 3.
CJ,SCJ,JMP Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The pointer number designated does not come prior to the END instruction. (Error code: 4210) • A pointer number which is not in use as a label in the same program has been designated. (Error code: 4210) • A common pointer has been designated. 2 3 (Error code: 4210) 4 Program Example (1) The following program jumps to P3 when X9 goes ON.
GOEND 6.5.2 Jump to END (GOEND) GOEND Basic High performance Process Redundant Universal Command GOEND GOEND Setting Data Internal Devices Bit Word R, ZR J Bit \ U Word –– \G Zn Constants Other –– Function (1) Jumps to the FEND or END instruction in the same program file. Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
DI,EI,IMASK 6.6 Program Execution Control Instructions 1 6.6.
DI,EI,IMASK IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 8 points from the device designated by S . • 1(ON)......Interrupt program execution enabled • 0(OFF) ....
DI,EI,IMASK Operation Error 1 (1) There are no operation errors associated with the DI, EI or IMASK instruction. 2 Program Example (1) The following program is designed to enable the execution of only the interrupt programs having the interrupt pointer numbers I1 and I3 while X0 is ON. [Ladder Mode] 3 [List Mode] Step Instruction 4 Device 4 6 7 8 6.6 Program Execution Control Instructions 6.6.
DI,EI,IMASK When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU is used DI DI Sequence program IMASK IMASK S EI EI : Head number of the devices where the interrupt mask data is stored (BIN 16 bits) S Setting Data S Internal Devices Bit Word J R, ZR Bit –– \ Word U Zn \G Constants Other –– Function DI (1) Disables the execution of an interrupt program until the EI instruction has been executed, even if a start cause for the interrupt program occurs.
DI,EI,IMASK IMASK (1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit pattern of 16 points from the device designated by S 1 . • 1(ON)...... Interrupt program execution enabled 2 • 0(OFF)....
DI,EI,IMASK Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified by S exceeds the range of the corresponding device. (For the Universal model QCPU only.) (Error code: 4101) Program Example (1) The following program creates an execution enabled state for the interrupt program marked by the interrupt pointer number when X0 is ON.
IRET 6.6.2 Recovery from interrupt programs (IRET) 1 IRET Basic High performance Process Redundant Universal 2 3 I ** IRET 4 IRET Setting Data –– Internal Devices Bit Word R, ZR J Bit \ U Word \G Zn Constants Other 4 –– 6 Function 7 (1) Indicates the completion of interrupt program processing. (2) Returns to sequence program processing following the execution of the IRET instruction.
IRET Program Example (1) The following program adds 1 to D0 if M0 is ON when the number 3 interrupt is generated.
RFS(P) 6.7 I/O Refresh Instructions 1 6.7.
RFS(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range n points from the device designated by S exceeds the proximate I/O range. (Error code: 4101) Program Example (1) The following program refreshes X100 to X11F and Y200 to Y23F when M0 goes ON.
UDCNT1 6.8 Other Convenient Instructions 6.8.
UDCNT1 • The counter designated at D is a ring counter. If it is counting up when the present value is 32767, the present value will become 32768. Further, if it is counting down when the present value is 32768, the present value will become 32767.
UDCNT1 Program Example 1 (1) This program uses C0 (Up/Down counter) to count the number of times X0 goes from OFF to ON after X20 has gone ON. [Ladder Mode] 2 [List Mode] Instruction Step Device 3 4 [Operation] X20 4 X0 X1 Up Down Up 6 C0 present value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0- 1- 2- 3- 2- 1 0 1 1 C0 contact 7 8 6.8 Other Convenient Instructions 6.8.
UDCNT2 6.8.
UDCNT2 • The counter designated at D is a ring counter. If it is counting up when the present value is 32767, the present value will become 32768. Further, if it is counting down when the present value is 32768, the present value will become 32767.
UDCNT2 Program Example (1) The following program performs a count operation as instructed by C0 (count up or down) on the status of X0 and X1 after X20 has gone ON.
TTMR 6.8.
TTMR Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified by D exceeds the range of the corresponding device. (For the Universal model QCPU only.) (Error code: 4101) Program Example (1) The following program stores the amount of time that X0 is ON at D0.
STMR 6.8.4 Special function timer (STMR) 1 STMR High performance Basic Process Redundant Universal 2 3 Command STMR STMR n S D 4 S : Timer number (word) 4 n : Value to set (BIN 16 bits).
STMR (3) The timer contact goes ON at the leading edge of the command for the STMR instruction, and after the trailing edge is reached, the timer coil goes OFF at the trailing edge of the STMR instruction command. The timer contact is used by the CPU module system, and cannot be used by the user.
STMR Program Example 1 (1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20 is ON. (Uses 100 ms timer) [Ladder Mode] 2 [List Mode] Step Instruction 3 Device 4 4 [Timing Chart] 6 X20 M1, Y0 7 M2, Y1 M3 1 sec 8 1 sec 6.8 Other Convenient Instructions 6.8.
ROTC 6.8.
ROTC (6) D +2 is the 0 point detection output signal that goes ON when item number 0 has arrived at the No. 0 station. When the device designated by D +2 goes ON while the ROTC instruction is being executed, S +0 is cleared. It is best to perform this clear operation first, then to begin shortest direction control with the ROTC instruction. (7) The data from D +3 to D +7 consists of output signals needed to control the table's operation.
ROTC Program Example (1) The following program deposits the item at section D2 on a 10-division rotary table at the station at section D1, and the two sections ahead and behind this determine the rotation direction and control speed of the motor when the table is being rotated at low speed. [Ladder Mode] [List Mode] Device Instruction Step Station No. 0 0 point detection X002 8 9 0 7 Part X000 6 1 Detection switch 2 Forward rotation 3 Station No.
RAMP 6.8.
RAMP (2) If the scan is performed for the number of moves specified by n3, the complete device specified by D2 +0 is turned ON. The ON/OFF status of the completion device and the contents of D1 +0 are determined by the ON/OFF status of the device designated by • When D2 D2 +1 is OFF, +0 will go OFF at the next scan, and the RAMP instruction will begin a new move operation from the value currently at • When D2 +1. +1 is ON, D2 D2 +0. +0 will remain ON, and the contents of D1 +0 will not change.
RAMP Program Example 1 (1) The following program changes the contents of D0 from 10 to 100 in a total of 6 scans, and saves the contents of D0 when the move has been completed. [Ladder Mode] [List Mode] Instruction Step 2 Device 3 4 [Timing Chart] 4 ON X0 D0 D1 OFF 10 25 40 55 70 85 100 0 1 2 3 4 5 6 1scan 1scan 1scan 1scan 1scan 6 1scan ON M0 7 OFF ON M1 OFF 8 6.8 Other Convenient Instructions 6.8.
SPD 6.8.
SPD 1. With the SPD instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted must have longer ON and OFF times than the interrupt interval of the CPU module.
PLSY 6.8.
PLSY 1. With the PLSY instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be output must have longer ON and OFF times than the interrupt interval of the CPU module.
PWM 6.8.
PWM 1. With the PWM instruction, the argument device data is registered in the work area of the CPU module and counting operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the execution command OFF, or turning the STOP/RUN switch STOP RUN.
MTR 6.8.
MTR Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device other than the input (X) was specified at S • The device other than the output (Y) was specified at . D1 (Error code: 4101) . (Error code: 4101) Program Example (1) The following program fetches, when X0 is turned ON, the 16 points X10, and stores the matrix into the area starting from M0.
MEMO 6-168
7 7 APPLICATION INSTRUCTIONS 7 7 7 7 7 Category Logical operation instructions Processing Details Logical operations such as logical sum, logical product, etc. Reference Section 7.1 Rotation of designated data Section 7.2 Shift instruction Shift of designated data Section 7.3 Bit processing instructions Sets and resets bit data; bit extraction Section 7.
7.1 Logical operation instructions (1) The logical operation instructions perform logical sum, logical product or other logical operations in 1-bit units.
WAND(P),DAND(P) 7.1.1 Logical products with 16-bit and 32-bit data (WAND(P),DAND(P)) 1 WAND(P),DAND(P) Basic When two data are set ( D D S ,( +1, D D ) ( S +1, High performance S ) Process Redundant Universal ( D +1, D 2 3 )) indicates an instruction symbol of WAND/DAND.
WAND(P),DAND(P) DAND (1) Conducts a logical product operation on each bit of the 32-bit data for the device designated by S1 and the 32-bit data for the device designated by S2 , and stores the results at the device designated by D .
WAND(P),DAND(P) (2) The following program performs a logical product operation on the data at D99 and D100, and the 24-bit data between X30 and X47 when X8 is ON, and stores the results at D99 and D100. [Ladder Mode] [List Mode] Step Instruction 1 Device 2 3 [Operation] b31 b30b29 b28 b27 b26 b25b24 b23 b22 D100, D99 1 1 1 1 1 1 1 1 1 1 X47 X30 0 0 0 0 0 0 0 AND X47X46 0 1 1 b3 b2 b1 b0 1 1 1 1 4 X33X32X31X30 0 1 0 1 Regarded as 0s.
WAND(P),DAND(P) When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D )) indicates an instruction symbol of WAND/DAND.
WAND(P),DAND(P) as "0" in the operation. (See Program Example (3)) 1 Operation Error (1) There are no operation errors associated with the WAND(P) or DAND(P) instruction. 2 Program Example (1) The following program performs a logical product operation on the data from X10 to X1B and the data at D33 when XA is ON, and stores the results at D40.
WAND(P),DAND(P) (3) The following program masks the digit in the hundred-thousands place of the 8-digit BCD value at D10 and D11 (sixth digit from the end) to 0 when XA is ON, and outputs the results to from Y10 to Y2B.
BKAND(P) 7.1.
BKAND(P) (2) The constant designated by S1 S2 can be between -32768 and 32767 (BIN 16-bit data).
WOR(P),DOR(P) 7.1.3 Logical sums of 16-bit and 32-bit data (WOR(P),DOR(P)) 1 WOR(P),DOR(P) Basic When two data are set ( D S D ,( +1, D D ) ( S +1, High performance S ) Process Redundant Universal ( D +1, D )) 3 indicates an instruction symbol of WOR/DOR.
WOR(P),DOR(P) DOR (1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by D and the 32-bit data of the device designated by designated by D , and stores the results at the device .
WOR(P),DOR(P) (2) The following program performs a logical sum operation on the 32-bit data from X0 to X1F, and on the hexadecimal value FF00FF00H when XB is turned ON, and stores the results at D66 and D67.
WOR(P),DOR(P) When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D )) indicates an instruction symbol of WOR/DOR.
WOR(P),DOR(P) DOR (1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by S1 and the 32-bit data of the device designated by designated by D 1 0 1 b16 b15 0 1 1 0 0 1 OR b31 0 0 0 1 1 1 b16 b15 0 0 0 b31 0 0 1 1 b0 0 0 1 3 S2 0 D +1 D 1 2 S1 S2 + 1 S2 , and stores the results at the device .
WOR(P),DOR(P) (2) The following program performs a logical sum operation on the 32-bit data at D0 and D1, and the 24-bit data from X20 to X37, and stores the results at D23 and D24 when M8 is ON. [Ladder Mode] [List Mode] Step Instruction [Operation] S +1 D1, D0 b31 1 1 1 S b28 b27 1 0 0 0 b24 b23 b22b21 0 1 1 0 b3 b2 b1 b0 0 1 1 1 OR X37 to X20 0 0 0 0 0 0 0 0 X37X36X35 1 0 0 X23X22X21X20 1 0 0 1 Regarded as 0s.
BKOR(P) 7.1.
BKOR(P) (2) The constant designated by S1 S2 can be between 32768 and 32767 (BIN 16-bit data).
WXOR(P),DXOR(P) 7.1.5 16-bit and 32-bit exclusive OR operations (WXOR(P),DXOR(P)) 1 WXOR(P),DXOR(P) Basic When two data are set ( D S D ,( D +1, D ) ( S High performance +1, S ) Process Redundant Universal 2 ( 3 D +1, D )) indicates an instruction symbol of WXOR/DXOR.
WXOR(P),DXOR(P) DXOR (1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated by D and the 32-bit data of the device designated by designated by D , and stores the results at the device .
WXOR(P),DXOR(P) (2) The following program compares the bit pattern of the 32-bit data from X20 to X3F with the bit pattern of the data at D9 and D10 when X6 is ON, and stores the number of differing bits at D16.
WXOR(P),DXOR(P) When three data are set ( S1 S2 D ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D )) indicates an instruction symbol of WXOR/DXOR.
WXOR(P),DXOR(P) DXOR (1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated by S1 and the 32-bit data of the device designated by designated by D b31 1 1 , and stores the results at the device .
WXOR(P),DXOR(P) (2) The following program conducts an exclusive OR operation on the data at D20 and D21, and the data at D30 and D31 when X10 is turned ON, and stores the results at D40 and D41.
BKXOR(P) 7.1.
BKXOR(P) (2) The constant designated by b15 S1 can be between S2 b8b7 32768 and 32767 (BIN 16-bit data).
WXNR(P),DXNR(P) 7.1.7 16-bit and 32-bit data exclusive NOR operations (WXNR(P),DXNR(P)) 1 WXNR(P),DXNR(P) Basic When two data are set ( S D D ,( +1, D D ) ( S +1, High performance S ) Process Redundant Universal ( D +1, D 2 3 )) 4 indicates an instruction symbol of WXNR/DXNR.
WXNR(P),DXNR(P) DXNR (1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by the 32-bit data of the device designated by designated by D S D and , and stores the results at the device .
WXNR(P),DXNR(P) (2) The following program compares the bit patterns of the 32-bit data located from X20 to X3F with the bit patterns of the data at D16 and D17 when X6 is ON, and stores the number of identical bit patterns at D18.
WXNR(P),DXNR(P) When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, )) D indicates an instruction symbol of WXNR/DXNR.
WXNR(P),DXNR(P) DXNR (1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by the 32-bit data of the device designated by designated by D and , and stores the results at the device S2 1 1 2 S1 0 b16 b15 0 1 1 1 1 0 0 b0 1 1 3 XNR S2 + 1 S2 b31 0 1 D b31 1 0 1 .
WXNR(P),DXNR(P) (2) The following program performs an exclusive NOR operation on the 32-bit data at D20 and D21 and the data at D10 and D11 when X10 is turned ON, and stores the result to D40 and D41.
BKXNR(P) 7.1.
BKXNR(P) (2) The constant designated by S1 S2 can be between 32768 and 32767 (BIN 16-bit data).
ROR(P),RCR(P) 7.2 Rotation instruction 1 7.2.1 Right rotation of 16-bit data (ROR(P),RCR(P)) 2 ROR(P),RCR(P) Basic High performance Process Redundant Universal 3 4 indicates an instruction symbol of ROR/RCR.
ROR(P),RCR(P) (2) When a bit device is designated for specified by digit specification. D , a rotation is performed within the device range The number of bits by which a rotation is carried out is the remainder of n/(specified number of bits). For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12 1 is "3", and the data is rotated 3 bits. (3) Specify any of 0 to 15 as n. If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
ROR(P),RCR(P) Operation Error 1 (1) There are no operation errors associated with the ROR(P) or RCR(P) instructions. 2 Program Example (1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the right when XC is turned ON.
ROL(P),RCL(P) 7.2.2 Left rotation of 16-bit data (ROL(P),RCL(P)) ROL(P),RCL(P) Basic High performance Process Redundant Universal indicates an instruction symbol of ROL/RCL.
ROL(P),RCL(P) (2) When a bit device is designated for specified by digit specification. D , a rotation is performed within the device range The number of bits by which a rotation is executed is the remainder of n/(specified number of bits). For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12 1 is "3", and the data is rotated 3 bits. (3) Specify any of 0 to 15 as n. 18, the data is rotated 2 bits to the left since the remainder of 18/16 1 is "2".
ROL(P),RCL(P) Operation Error (1) There are no operation errors associated with the ROL(P) or RCL(P) instructions. Program Example (1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the left when XC is turned ON.
DROR(P),DRCR(P) 7.2.3 Right rotation of 32-bit data (DROR(P),DRCR(P)) 1 DROR(P),DRCR(P) Basic High performance Process Redundant Universal indicates an instruction symbol of DROR/DRCR.
DROR(P),DRCR(P) DRCR (1) Rotates 32-bit data, including carry flag, at device designated by D n bits to the right. The carry flag goes ON or OFF depending on its status prior to the execution of the DRCR instruction. D +1 b31 b30 b29 b28 b27 D b5 b4 b3 b2 b1 b0 b18 b17 b16 b15b14 Carry flag (SM700) n-bit rotation (2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
DROR(P),DRCR(P) (2) The following program rotates the contents of D0 and D1, including the carry flag, 4 bits to the right when XC is ON.
DROL(P),DRCL(P) 7.2.4 Left rotation of 32-bit data (DROL(P),DRCL(P)) DROL(P),DRCL(P) Basic High performance Process Redundant Universal indicates an instruction symbol of DROL/DRCL.
DROL(P),DRCL(P) (2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification. The number of bits by which a rotation is executed is the remainder of n /(specified number of bits). For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24 1 is "7", and the data is rotated 7 bits. (3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n/32 is used for rotation.
SFR(P),SFL(P) 7.3 Shift instruction 7.3.1 n-bit shift to right or left of 16-bit data (SFR(P),SFL(P)) SFR(P),SFL(P) Basic High performance Process Redundant Universal indicates an instruction symbol of SFR/SFL.
SFR(P),SFL(P) The number of bits by which a shift is executed is the remainder of n/(specified number of bits). For example, when n 15 and (specified number of bits) 1 is "7", and the data is shifted 7 bits. 8 bits, the remainder of 15/8 (3) Specify any of 0 to 15 as n. If the value specified as n is 16 or greater, the remainder of n/16 is used for a shift to the right. For example, when n 18, the data is shifted 2 bits to the right since the remainder of 18/16 1 is 2.
SFR(P),SFL(P) Program Example (1) The following program shifts the data of D0 to the right by the number of bits designated by D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 D0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 D100 3 Carry flag (SM700) 0 b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 D0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Filled with 0s.
BSFR(P),BSFL(P) 7.3.2 1-bit shift to right or left of n-bit data (BSFR(P),BSFL(P)) 1 BSFR(P),BSFL(P) Basic High performance Process Redundant Universal indicates an instruction symbol of BSFR/BSFL.
BSFR(P),BSFL(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device n points from a device designated by relevant device. D , or exceeds the (Error code: 4101) Program Example (1) The following program shifts the data at M668 to M676 to the right when X8F is turned ON.
SFTBR(P),SFTBL(P) 7.3.3 n-bit shift to right or left of n-bit data (SFTBR(P),SFTBL(P)) 1 SFTBR(P),SFTBL(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. 2 QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. 3 indicates an instruction symbol of SFTBR/SFTBL.
SFTBR(P),SFTBL(P) SFTBL(P) (1) This instruction shifts the n1 bits data in the devices starting from the device specified by to the left by n2 bits. D n1=10, n2=4 n2 n1 8 D 1 Carry flag (SM700) 1 1 8 D 1 7 D 1 6 D 1 5 D 0 7 D D 1 6 0 1 D 1 4 D 3 D 1 5 D 4 D 3 D 0 2 D 0 2 0 1 D 1 1 1 D D 0 D 0 Filled with 0s (2) n1 and n2 are specified under the condition that n1 is larger than n2.
SFTBR(P),SFTBL(P) Program Example 1 (1) The following program shifts the data of Y10 to Y17 (8 bits) specified by bits (n2), when M0 is turned on. [Ladder Mode] to the right by 2 D 2 [List Mode] Instruction Step Device 3 [Operation] 4 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 1 0 1 1 1 0 0 1 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 0 0 1 0 1 1 1 0 6 Carry flag (SM700) 0 (2) The following program shifts the data of Y21 to Y2C (12 bits) specified by bits (n2), when M0 is turned on.
DSFR(P),DSFL(P) 7.3.4 1-word shift to right or left of n-word data (DSFR(P),DSFL(P)) DSFR(P),DSFL(P) Basic High performance Process Redundant Universal indicates an instruction symbol of DSFR/DSFL.
DSFR(P),DSFL(P) Operation Error 1 (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range of the device n points from a device designated by relevant device. D , or exceeds the (Error code: 4101) 2 3 Program Example (1) The following program shifts the contents of D683 to D689 to the right when XB is turned ON.
SFTWR(P),SFTWL(P) 7.3.5 n-bit shift to right or left of n-word data (SFTWR(P),SFTWL(P)) SFTWR(P),SFTWL(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of SFTWR/SFTWL.
SFTWR(P),SFTWL(P) SFTWL(P) (1) This instruction shifts the n1 words data in the devices starting from the device specified by D 1 to the left by n2 words. n1=9, n2=4 2 n2 n1 D 8 D 7 D D 10H 1FFH 8 7 D 3AH 6 0H 1F H D 30 H 5 D 7FFH 6 5 D 0H D 4 3AH D FFH 3 D D 1F H 4 3 D 2 30 H D 0H D 1 D 0H 2 0H D FFH 3 D 4 1 0H 0H Filled with 0H 6 (2) The n2 words in the devices starting from the lowest device are filled with 0s.
SFTWR(P),SFTWL(P) (2) The following program shifts the 12 words (n1) data in the devices starting from D21 specified by D to the left by 5 words (n2), when M0 is turned on.
BSET(P),BRST(P) 7.4 Bit processing instructions 1 7.4.1 Bit set and reset for word devices (BSET(P),BRST(P)) 2 BSET(P),BRST(P) High performance Basic Process Redundant Universal indicates an instruction symbol of BSET/BRST.
BSET(P),BRST(P) Operation Error (1) There are no operation errors associated with the BSET(P) or BRST(P) instructions. Program Example (1) The following program resets the 8th bit of D8 (b8) to 0 when XB is OFF, and sets the 3rd bit of D8 (b3) to 1 when XB is ON. [Ladder Mode] Resets b8 of D8. Sets b3 of D8. [List Mode] Step Instruction Device [Operation] b15 b8 b3 b0 Before execution D8 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 When XB turns OFF. After execution When XB turns ON.
TEST(P),DTEST(P) 7.4.2 Bit tests (TEST(P),DTEST(P)) 1 High performance Basic Process Redundant Universal 2 TEST(P),DTEST(P) 3 indicates an instruction symbol of TEST/DTEST.
TEST(P),DTEST(P) (3) The position designated by S2 indicates the position of an individual bit in a 2-word data block (0 to 31). When 32 or more is designated at S2 , the target is the bit data at the position indicated by the remainder of n / 32. For example, when n 34, the target is the data at b2 since the remainder of 34 / 32 1 is "2". S2 bit (When S2 =21) b31 b21 b16 b15 S1 +1 b0 D S1 Operation Error (1) There are no operation errors associated with the TEST(P) or DTEST(P) instructions.
TEST(P),DTEST(P) (2) The following program turns Y40 ON or OFF, depending on the status of the 19th bit of the 2-word data (W0 and W1). [Ladder Mode] [List Mode] Step Instruction 1 Device 2 3 [Operation] b31 b19 b16 b15 b0 10 1 10 0 10 10 1 100 00 10 1 10 1 1 10 1 1 10 110 4 Turns Y40 OFF since b19 is "0." b31 b19 b16 b15 b0 0 110 110 1110 1 10 0 110 10 110 000 10 1 10 1 Turns Y40 ON since b19 is "1.
BKRST(P) 7.4.3 Batch reset of bit devices (BKRST(P)) BKRST(P) Basic High performance Process Redundant Universal Command BKRST BKRST D n BKRSTP D n Command BKRSTP D n Setting Data : Head number of the devices to be reset (bits) : Number of the devices to be reset (BIN 16 bits) Internal Devices Bit Word R, ZR J Bit \ Word U Zn \G Constants K, H Other –– D –– n –– Function (1) Resets bit device n-points from the bit device designated by Device D .
BKRST(P) Program Example 1 (1) The following program turns OFF devices from M0 to M7 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 [Operation] M9M8M7 M4 M3 M0 1 1100 11100 4 M9 M8M7 M4M3 M0 1100000000 Not changed (2) The following program sets data from 2nd bit (b2) of D10 to 1st bit (b1) of D11 to 0 when X20 is turned ON.
SER(P),DSER(P) 7.5 Data processing instructions 7.5.
SER(P),DSER(P) DSER (1) Searches n points from the device designated by S2 in 32-bit units (2 units.) regarding 32-bit data of the device designated by S1 +1 and n points in 16-bit S1 as a keyword. Then, the number of matches with the keyword is stored at the device designated by first matched device number (in the relative number from designated by Search data D D +1, and the ) is stored at the device 2 . 3 Head number to be searched 5678901 S1 +1.
SER(P),DSER(P) Program Example (1) The following program searches D100 to D105 for the contents of D0 when X20 is ON, and stores the search results at W0 and W1.
SUM(P),DSUM(P) 7.5.2 16-bit and 32-bit data checks (SUM(P),DSUM(P)) 1 SUM(P),DSUM(P) Basic High performance Process Redundant Universal indicates an instruction symbol of SUM/DSUM.
SUM(P),DSUM(P) Operation Error (1) There are no operation errors associated with the SUM(P) or DSUM(P) instructions. Program Example (1) The following program stores the number of bits which are ON from X8 to X17 into D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] X8 X17 0 0 10 10 1 100 00 0 1 11 Stores the total number of bits where 1 is set at D0.
DECO(P) 7.5.
DECO(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of n is not in the 0 to 8 range. • The range 2n bits from D (Error code: 4100) exceeds the range of the relevant device. (Error code: 4101) Program Example (1) The following program decodes the 3 bits from X0 and stores the results at M10 when X20 is ON.
ENCO(P) 7.5.
ENCO(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of n is not in the 0 to 8 range. • The range 2n bits from (Error code: 4100) exceeds the range of the relevant device. S (Error code: 4101) • All data 2n bits from is "0". S (Error code: 4100) Program Example (1) The following program encodes the 3 bits from M10 when X20 is ON, and stores the results at D8.
SEG(P) 7.5.
SEG(P) 7-segment decode display S Hexadecimal D Configuration of 7 Segments Bit Pattern B7 B6 B5 B4 B3 B2 B1 B0 0 0000 0 0 1 1 1 1 1 1 1 0001 0 0 0 0 0 1 1 0 2 0010 0 1 0 1 1 0 1 1 3 0011 0 1 0 0 1 1 1 1 4 0100 0 1 1 0 0 1 1 0 5 0101 0 1 1 0 1 1 0 1 6 0110 0 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 7 0111 8 1000 B0 B5 B1 B6 B4 9 Display Data B2 100
DIS(P) 7.5.
DIS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range n-points from D exceeds the relevant device. • The value of n is outside the 0 to 4 range. (Error code: 4101) (Error code: 4100) Program Example (1) The following program dissociates the 16-bit data from D0 into 4-bit groups, and stores from D10 to D13 when X0 is ON.
UNI(P) 7.5.
UNI(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The range n-points from S exceeds the relevant device. • The value of n is outside the 0 to 4 range. (Error code: 4101) (Error code: 4100) Program Example (1) The following program links the lower 4 bits of D0 to D2 when X0 is ON, and stores them at D10.
NDIS(P),NUNI(P) 7.5.8 Dissociation or linking of random data (NDIS(P),NUNI(P)) 1 NDIS(P),NUNI(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of NDIS/NUNI.
NDIS(P),NUNI(P) (2) The number of dissociated bits designated at bits. (3) Bits from the device number designated at processed as dissociated bits. S2 S2 can be designated within a range of 1 to 16 to the device number where "0" is stored are (4) Do not overlap the device range for data to be dissociated( S1 to end range of S1 ) with the device range which stores the dissociated data ( D to end range of D ). If overlapped, the correct operation result may not be obtained.
NDIS(P),NUNI(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. 1 • The number of bits to be dissociated or linked as specified by S2 , or the device use range specified by S1 or D exceeds the final device number of their respective devices. (Error code: 4101) 2 • The number of bits for dissociation or linking specified by range of from 1 to 16 bits.
NDIS(P),NUNI(P) (2) The following program links the lower 4 bits of data from D10, the lower 3 bits of data from D11, and the lower 6 bits of data from D12, and stores at D0. [Ladder Mode] [List Mode] Step Instruction [Operation] b3 b0 D10 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 4 bits b2 b0 D11 0 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1 3 bits b5 b0 D12 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 6 bits The data in these bits is ignored. 7-84 D0 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 b12 b7b6 b4b3 b0 Filled with 0s.
WTOB(P),BTOW(P) 7.5.9 Data dissociation and linking in byte units (WTOB(P),BTOW(P)) 1 WTOB(P),BTOW(P) High performance Basic 2 Process Redundant Universal 3 indicates an instruction symbol of WTOB/BTOW.
WTOB(P),BTOW(P) (2) Setting the number of bytes with n automatically determines the range of the 16-bit data designated by and the range of the devices to store the byte data designated by S . D (3) No processing will be conducted when the number of bytes designated by n is "0". (4) The "00H" code will automatically be stored at the upper 8 bits of the byte storage device designated by b15 .
WTOB(P),BTOW(P) (4) The upper 8 bits of the byte storage device designated by bits are used. S (5) Linking is correctly processed even when the device range ( to be linked is stored overlaps with the device range ( D to D are ignored, and the lower 8 S to S +(n-1)) where the data n +( 2 -1)) where the linked data will be stored.
WTOB(P),BTOW(P) (2) The following program links the lower 8 bits of data from D20 through D25 and stores the result at D10 to D12 when X0 is turned ON. [Ladder Mode] [List Mode] Instruction Step Device [Operation] b8 b7 b15 D20 D21 D22 6 bytes D23 D24 D25 00H 31H 36H 44H 48H 49H Upper byte is ignored.
MAX(P),DMAX(P) 7.5.10 Maximum value search for 16- and 32-bit data (MAX(P),DMAX(P)) 1 MAX(P),DMAX(P) High performance Basic Process Redundant Universal 2 3 indicates an instruction symbol of MAX/DMAX.
MAX(P),DMAX(P) DMAX (1) Searches in the n points of 32-bit BIN data, from the device designated by S , for the maximum value and stores the searched maximum value at the device designated by and D Starts the search from the device designated by number of points counted from D D +1.
MAX(P),DMAX(P) (2) The following program searches for the maximum value from the32-bit data at D0 to D7, and stores it at D100 to D103 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 2 3 [Operation] D1, D0 D3, D2 D5, D4 D7, D6 3786213 (BIN) -3235 (BIN) 8744740 (BIN) 7141821 (BIN) 1 D101, D100 D102 D103 8744740 3 1 4 6 6 7 8 7.5 Data processing instructions 7.5.
MIN(P),DMIN(P) 7.5.11 Minimum value search for 16- and 32-bit data (MIN(P),DMIN(P)) MIN(P),DMIN(P) Basic High performance Process Redundant Universal indicates an instruction symbol of MIN/DMIN.
MIN(P),DMIN(P) DMIN (1) Searches in the n points of 32-bit BIN data, from the device designated by S minimum value and stores searched minimum value at the devices designated by D D and +1.
MIN(P),DMIN(P) (2) The following program, when X20 is turned ON, searches for the minimum value from the 32-bit data contained from D0 to D7, and stores it from D100 to D103.
SORT,DSORT 7.5.12 BIN 16 and 32 bits data sort operations (SORT,DSORT) 1 SORT,DSORT Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of SORT/DSORT.
SORT,DSORT (2) Several scans are required for sorts performed by the SORT instruction. The number of scans executed until completion is the value obtained by dividing the maximum number of times executed until the completion of the sort by the number of data blocks compared at one execution designated by S2 . (Decimal fractions are rounded up.)When the value of S2 is increased, the number of scans until completion of the sort is reduced, but the amount of time per scan is lengthened.
SORT,DSORT (2) Several scans are required for sorts performed by the DSORT instruction. The number of scans executed until completion is the value obtained by dividing the maximum number of times executed until the completion of the sort by the number of data blocks compared at one execution designated by S2 . (Decimal fractions are rounded up.)When the value of S2 is increased, the number of scans until completion of the sort is reduced, but the amount of time per scan is lengthened.
SORT,DSORT Program Example (1) The following program sorts the BIN 16-bit data in 10 points from D0 in the ascending/ descending order when X10 is turned ON. [Ladder Mode] [List Mode] Instruction Step Device [Operation] Data after sort Data before sort D0 D1 D2 D3 100 -1 12345 -999 X0 OFF D0 D1 D2 D3 X0 D0 D1 ON D2 D3 -999 -1 100 12345 12345 100 -1 -999 (2) The following program sorts the BIN 32-bit data in 20 points from D0 in ascending/ descending order when X10 is turned ON.
WSUM(P) 7.5.
WSUM(P) Program Example (1) The following program adds the 16-bit BIN data from D10 to D14, and stores it in D100 and D101 when X1C is turned ON.
DWSUM(P) 7.5.
DWSUM(P) Program Example (1) The following program adds the 32-bit BIN data at D100 to D107, and stores the result at D10 and D13 when X20 is turned ON.
MEAN(P),DMEAN(P) 7.5.15 Calculation of averages for 16-bit or 32-bit data (MEAN(P),DMEAN(P)) 1 MEAN(P),DMEAN(P) Ver. High performance Basic Process Redundant Universal • QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. • QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of MEAN/DMEAN.
MEAN(P),DMEAN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The value specified by n is other than 0 to 32767. (Error code: 4100) • The range of the n-point devices starting from the device specified by S range of the devices specified by D .
FOR,NEXT 7.6 Structure creation instructions 1 7.6.
FOR,NEXT Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • An END, FEND or GOEND instruction was executed before the execution of a NEXT instruction and after the execution of a FOR instruction. (Error code: 4200) • A NEXT instruction is executed prior to the execution of a FOR instruction. (Error code: 4201) • A STOP instruction has been inserted within the FOR to NEXT loop.
FOR,NEXT Remark 1. To force an end to the repetitious execution of the FOR to NEXT loop during the execution of the loop, insert a BREAK instruction. See 7.6.2 for details concerning the use of the BREAK instruction. 2. Use the EGP/EGF instruction to perform the pulse operation of an index-modified program between the FOR and NEXT instructions. Refer to 5.2.5 for details of the EGP/EGF instruction. The program samples are shown below: 1 2 3 4 6 6 3.
BREAK(P) 7.6.2 Forced end of FOR to NEXT instruction loop (BREAK(P)) BREAK(P) Basic High performance Process Redundant Universal Command BREAK BREAK D Pn BREAKP D Pn Command BREAKP D : Number of the device where the remaining number of loops will be stored (BIN 16 bits) Pn : Number of the pointer (device name (pointer)) where the program is branched at the forced end of a loop.
BREAK(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The BREAK instruction is used in a case other than with the FOR to NEXT instruction loop. (Error code: 4203) • The jump destination for the pointer designated by Pn does not exist. (Error code: 4210) • The pointer of another program file is designated for Pn.
CALL(P) 7.6.
CALL(P) (2) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with S1 to S5 corresponding to the function device. The contents to the devices specified by to S5 are as indicated below. S1 1 2 3 4 (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. 6 (b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding devices.
CALL(P) (6) The device used in the argument of the CALL (P) instruction should not be used in a subroutine program. If used, it will not be possible to obtain accurate calculations. (Refer to the following program example.) (7) When the device, either timer or counter, is used in the argument of the CALL(P) instruction, only the current value is transmitted/received.
CALL(P) Correct operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is used in the subroutine program.
CALL(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified for the argument cannot be secured for the data size. (Error code: 4101) • Following the execution of the CALL (P) instruction, an END, FEND, GOEND, or STOP instruction is executed before the execution of the RET instruction. (Error code: 4211) • An RET instruction is executed prior to the execution of the CALL (P) instruction.
RET 7.6.4 Return from subroutine programs (RET) 1 RET Basic High performance Process Redundant Universal 2 3 RET RET 4 Setting Data Internal Devices Bit Word R, ZR –– J Bit \ U Word Zn \G Constants Other 6 –– 6 Function (1) Indicates end of subroutine program (2) When the RET instruction is executed, returns to the step following the CALL (P), FCALL (P), ECALL (P), EFCALL (P) or XCALL instruction which called the subroutine program.
FCALL(P) 7.6.
FCALL(P) (b) The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction ...... SET instruction RST instruction SFT instruction ...... Basic instructions Application instructions PLS instruction Pulse generation ...... instruction ( P) Present value of low speed/high speed timers ...... Present value of retentive timer ......
FCALL(P) (4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with S1 to S5 corresponding to the function device. The contents to the devices specified by to S5 are as indicated below. S1 (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. (b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding devices.
FCALL(P) (6) Up to 16 nesting levels are possible with the FCALL(P) instruction. However, this 16 levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions. CALL P0 FCALL P0 P0 CALL FEND 1 P10 P10 CALL 2 P20 P20 FCALL P10 FCALL P20 RET RET 3 RET 4 END Operation Error 6 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
ECALL(P) 7.6.
ECALL(P) (2) Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file name. (3) It is not necessary to designate the extension (.QPG) with the file name. 1 (Only .QPG files will be acted on.) (4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with S1 to S1 to are as indicated below. S5 2 S5 .
ECALL(P) (5) From S1 to S5 can be used by the ECALL instruction. (6) The device used in the argument of the ECALL instruction should not be used in a subroutine program. If used, it will not be possible to obtain accurate calculations. (Refer to the following program example.) Incorrect operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is used in the subroutine program.
ECALL(P) Correct operation example The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is used in the subroutine program.
ECALL(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified for the argument cannot be secured for the data size. (Error code: 4101) • Following the execution of the ECALL (P) instruction, an END, FEND, GOEND, or STOP instruction is executed before the execution of the RET instruction. (Error code: 4211) • An RET instruction is executed prior to the execution of the ECALL(P) instruction.
EFCALL(P) 7.6.
EFCALL(P) (b) The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of the ON/OFF status of the individual contacts: OUT instruction ...... SET instruction RST instruction SFT instruction ...... Basic instructions Application instructions PLS instruction Pulse generation ...... instruction ( P) Present value of low speed/high speed timers ...... Present value of retentive timer ......
EFCALL(P) (4) Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file name. (5) It is not necessary to designate the extension (.QPG) with the file name. (Only .QPG files will be acted on.) (6) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function device with S1 to S5 .
EFCALL(P) (7) S1 to S5 can be used with the EFCALL (P) instruction. (8) The number of function devices used by subroutine programs must be identical to the number of arguments used by the EFCALL (P) instruction. Further, the function devices should be identical to the types of arguments used by the EFCALL (P) instruction. (9) Up to 16 levels of nesting can be used with the EFCALL (P) instruction.
XCALL 7.6.8 Subroutine program call (XCALL) 1 XCALL Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
XCALL (2) Operation of XCALL instruction varies according to the CPU module type. The following program example shows the operation of XCALL instruction for each CPU module. [Program example] Subroutine program (P1) call by XCALL instruction P1 subroutine program [ON/OFF timing of X0] (1) Turning X0 ON (OFF ON) (2) During X0 is ON *2 (3) Turning X0 OFF (ON OFF) ON X0 OFF *2: Time during X0 is ON(2)) does not include the time when turning X0 ON (1)). Component • Process CPU (serial No.
XCALL (3) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with S1 to S5 corresponding to the function device. The contents to the devices specified by to S5 are as indicated below. S1 1 2 3 4 (a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD. (b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding devices.
XCALL (7) Up to 16 nesting levels can be used with the XCALL instruction. However, this 16 levels is the total number of levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions. P0 XCALL P0 X0 XCALL P10 X10 FEND P20 XCALL P20 X20 RET RET RET END (8) The device used for the argument of the XCALL instruction must not be used in a subroutine program. If used, it will not be possible to perform correct calculations. (Refer to the following program example.
XCALL Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified for the argument cannot be secured for the data size. (Error code: 4101) 2 • Following the execution of the XCALL(P) instruction, the END, FEND, GOEND or STOP instruction is executed before the execution of the RET instruction.
COM 7.6.9 Refresh instruction (COM) Basic COM High performance Process Redundant Universal Refer to Section 7.6.10 for the COM instruction of the following CPU modules. • Basic model QCPU of serial No. 04122 or later • High Performance model QCPU of serial No. 04012 or later • Process CPU of serial No.
COM (3) At the point of the execution of the COM instruction, the CPU module temporarily stops the processing of the sequence program, and performs the same operation as ordinary data processing as well as auto refresh of intelligent function modules (including link refreshes) at the END processing. However, the low speed cyclic refresh of MELSECNET/10 or MELSECNET/H is not performed.
COM (6) If the scan time from the linked station is longer than the sequence program scan time at the host station, designating the COM instruction at the host station will not increase the speed of data communications.
COM 7.6.10 Select Refresh Instruction (COM) 1 COM Refer to Section 7.6.9. for the COM instruction of the following CPU modules. • Basic model QCPU of serial No. 04121 or lower • High Performance model QCPU of serial No. 04011 or lower • Process CPU of serial No. 07031 or lower Ver. Basic Ver. High performance 2 Ver. Process Redundant Universal 3 The first 5 digits of the serial No. are "04122" or higher. The first 5 digits of the serial No. are "04012" or higher.
COM (3) When selecting refresh items (a) Select refresh items by SD778, and set SM775 to ON. The following table shows the refresh items that can be designated by turning SM775 ON/OFF and with SD778.
COM (4) Upon the execution of the COM instruction, the CPU module suspends the processing of the sequence program, and refreshes the designated refresh item. Execution of COM instruction 0 END Refreshes the designated refresh items 1 Execution of COM instruction 0 END 2 0 3 Refreshes the designated refresh items (5) The COM instruction can be used in a sequence program any number of times.
COM 1. The COM instruction cannot be used in low speed execution type programs, fixed scan execution type programs or interrupt programs. 2. For the redundant CPU, there are restrictions on use of the COM instruction. Refer to the manual below for details.
CCOM 7.6.11 Select Refresh Instruction (CCOM) 1 CCOM Ver. Basic High performance Process Redundant Universal 2 QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
CCOM (3) When refresh items are selected (a) Specify refresh items for SD778, and set SM775 to on. The following table shows the refresh items that can be specified by turning SM775 on or off and in SD778.
CCOM (4) On the execution of the CCOM (P) instruction, the CPU module suspends the processing of the sequence program, and refreshes the specified refresh item. Execution of CCOM(P) instruction END 0 Refresh specified in refresh items Execution of CCOM(P) instruction END 0 1 2 0 Refresh specified in refresh items 3 (5) The CCOM(P) instruction can be used in a sequence program any number of times.
IX,IXEND 7.6.
IX,IXEND (2) Index modification for device numbers is accomplished in the manner as below: By setting a modification value to each of the devices, the set modification values are added to the all device numbers of the devices used in the ladder between the IX and IXEND instructions. The program is executed using the index modified device numbers.
IX,IXEND (8) Whether the program will be expanded or a user needs to create the program is depending on your GPP function software package. (a) When a user needs to create the program (When GX Developer is used) The index register should be added to the index modification ladder established with the IX and IXEND instructions.
IX,IXEND Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The IX and IXEND instructions are not used together. (Error code: 4231) • An END, FEND, GOEND, or STOP instruction is executed prior to the execution of the IXEND instruction, but after the execution of the IX instruction.
IXDEV,IXSET 7.6.
IXDEV,IXSET (6) If two offsets for two identical types of device have been set in the offset designation area, the last value set will be valid. (7) The IXDEV and IXSET instructions should be treated as a pair. (8) Any value from 0 to 32767 is valid for ZR. (The offset value will be the remainder of the quotient of the designated device number divided by 32768.) (9) The dummy contacts in the offset specifying part are valid for only LD and AND located within the range of the IXDEV-IXSET instructions.
IXDEV,IXSET Program Example (1) The following program changes the modification values for input (X), output (Y), data register (D) and pointer (P). When using a basic model QCPU, the devices R, U/G, J, ZR and P cannot be used. [Ladder Mode] [List Mode] Device Instruction Step Index modification ladder * Index modification table T D0 4 0 C X 5 Y 3 M 0 L 0 B 0 V 0 8 D 0 W 0 D15 0 0 *4: Refer to 7.6.12 for index modification using the IX to IXEND instructions.
FIFW(P) 7.7 Data Table Operation Instructions 1 7.7.
FIFW(P) Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data table range exceeds the relevant device range when the FIFW instruction is executed. (Error code: 4101) Program Example (1) The following program stores the data at D0 to the data table following R0 when X10 is turned ON.
FIFR(P) 7.7.
FIFR(P) Program Example (1) The following program stores the R1 data from the table R0 to R7 at D0 when X10 is turned ON.
FPOP(P) 7.7.
FPOP(P) Program Example (1) The following program stores the data stored last in the data table R0 to R7 at D0 when X10 is turned ON. [Ladder Mode] [List Mode] Device Instruction Step [Operation] R0 R1 R2 R3 R4 R5 R6 R7 Data table 5 -123 1400 1234 5432 3000 0 0 R0 R1 R2 R3 R4 R5 R6 R7 Data table 4 -123 1400 1234 5432 0 0 0 D0 3000 Stores 0.
FDEL(P),FINS(P) 7.7.4 Deleting and inserting data from and in data tables (FDEL(P),FINS(P)) 1 FDEL(P),FINS(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of FDEL/FINS.
FDEL(P),FINS(P) FINS (1) Inserts the 16-bit data designated by S at the nth block of the data table designated by D . After the execution of the FINS instruction, the data in the table following the inserted block is all dropped one position. Data table 3 5432 1234 123 0 0 D D +1 D +2 D +3 D +4 D +5 Number of stored data blocks D D +1 D +2 D +3 D +4 D +4 Data table 4 5432 4444 1234 123 0 0 Data table range 0 If n=2, data is inserted to D +2.
FDEL(P),FINS(P) Program Example 1 (1) The following program deletes the second data from the table R0 to R7 and stores the deleted data at D0 when X10 is turned ON.
FROM(P),DFRO(P) 7.8 Buffer memory access instruction 7.8.1 Reading 1-/2-word data from the intelligent function module (FROM(P),DFRO(P)) FROM(P),DFRO(P) Basic High performance Process Redundant Universal indicates an instruction symbol of FROM/DFRO.
FROM(P),DFRO(P) DFRO (1) Reads the data in (n3 2) words from the buffer memory address designated by n2 of the the intelligent function module designated by n1, and stores the data into the area starting from the device designated by D . Intelligent function module buffer memory n2 n2+1 1 2 CPU module Device designated by D (n3 2) words 3 (n3 2) points 4 6 Data read from intelligent function modules is also possible with the use of an intelligent function module device.
FROM(P),DFRO(P) Program Example (1) The following program reads the digital value of CH1 of the A68AD mounted at I/O numbers 040 to 05F into D0 when X0 is turned ON. (Reads 1 word of data from address 10 of the buffer memory.) [Ladder Mode] [List Mode] Instruction Step Device (2) The following program reads the X-axis present value of the AD71 mounted at the I/O numbers 040 to 05F into D0 and D1, when X0 is turned ON. (Reads data in 2 words from the address 602 and 603 of the buffer memory.
TO(P),DTO(P) 7.8.2 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) 1 TO(P),DTO(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of TO/DTO.
TO(P),DTO(P) DTO Writes the data stored in n3 2 points starting from the device designated by S into the area starting from buffer memory address designated by n2 of the intelligent function module designated by n1. Device designated by S Intelligent function module buffer memory 0 CPU module n2 n2+1 (n3 x 2) points When a constant is designated to S (n3 x 2) words , writes the same data (value designated to of n3 2 points starting from the specified buffer memory.
TO(P),DTO(P) Program Example 1 (1) The following program sets the CH1 and CH2 of the Q68ADV mounted at the I/O numbers 040 to 04F to the "A/D conversion" mode, when X0 is turned ON. (Writes 3 into the buffer memory address 0.) [Ladder Mode] 2 [List Mode] Instruction Step Device 3 4 (2) The following program sets the X-axis current value of the AD71 mounted at I/O numbers 040 to 05F to 0 when X0 is turned ON. (Writes 0 to addresses 41, 42 of the buffer memory.
PR 7.9 Display instructions 7.9.
PR (b) If SM701 is OFF, everything from the device designated by the target of the operation.
PR Operation Error (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • There is no 00H code within the range of the device specified by S when SM701 is OFF. (Error code: 4101) Program Example (1) The following program converts the string "ABCDEFGHIJKLMNOP" to ASCII code when X0 is turned ON and stores it from D0 to D7, and then outputs the ASCII code at D0 to D7 to Y14 to Y1D when X3 is turned ON.
PRC 7.9.
PRC [Timing Chart] A B C n O Preprocessing 41H 42H 43H 4EH 4FH (several scans) 30 ms Y30 to Y37 ON OFF PRC ON Y38 OFF (Strobe signal) 10 10 10 ms ms ms ON Y39 OFF 30ms x 16 = 480 ms (Flag indicating strobe signal is being output) ON SM721 (File access in progress flag) OFF SM720 (File access completion flag) OFF PRC instruction cannot be executed again. ON None of instructions can be executed. Instructions other than PRC instruction (SP.FREAD, SP.
PRC 1. For device comments used with the PRC instruction, use comment files stored in the memory card Standard Rom. Comment files stored in the program memory cannot be used. 2. The comment file used by the PRC instruction is set at the "PLC File Setting" option in the PLC parameter dialog box. If no comment file has been set for use by the PLC file setting, it will not be possible to output device comments with the PRC instruction. 3. Do not execute the PRC instruction during an interrupt program.
LEDR 7.9.3 Error display and annunciator reset instruction (LEDR) LEDR Basic High performance Process Redundant Universal Command LEDR LEDR Setting Data Internal Devices Bit Word R, ZR J Bit \ U Word –– \G Zn Constants Other –– Function Resets the self-diagnosis error display so that annunciator display or operation can be continued. With one execution of this instruction, either error display or annunciator is reset.
LEDR (2) Operations when an annunciator (F) is ON. (a) When the CPU module has no LED display The following operations will be conducted when the LEDR instruction is executed: 1) "USER" LED flickers, and is turned OFF 2) The annunciators (F) stored in SD62 and SD64 are reset, and the F numbers for SD65 to SD79 are moved up. 3) The data newly stored at SD64 is transmitted to SD62. 4) The data at SD63 is decremented by 1. However, if SD63 is 0, it remains 0.
LEDR Remark 1. The defaults for the error item numbers set in special registers SD207 to SD209 and order of priority are given in the table below: Priority Factor number (Hexadecimal) Meaning AC DOWN 1 1 SINGLE PS.DOWN SINGLE PS.ERROR 2 3 4 2 3 4 Remarks Power supply cut Redundant base unit power supply voltage drop Redundant power supply module fault UNIT VERIFY ERR. I/O module verify error FUSE BREAK OFF Blown fuse SP.
CHKST,CHK 7.10 Debugging and failure diagnosis instructions 1 7.10.
CHKST,CHK (b) The contact instruction prior to the CHK instruction does not control the execution of the CHK instruction, but rather sets the check conditions.
CHKST,CHK (2) Depending on the designated contact, the CHK instruction undergoes processing identical to that shown for the ladder below: TO 1 CHKST X X CHK Coil No. 1 (Detection by both advance and retraction end sensors during advance operation of the conveyor) X X +1 Y SET SM80 Coil No. 2 MOV Failure No. 1 SD80 (Detection by both advance and retraction end sensors during retract operation of the conveyor) X X +1 Y SET SM80 Coil No. 3 MOV Failure No.
CHKST,CHK (7) Place LD and AND instructions prior to the CHK instruction to establish a check condition. Check conditions cannot be set using other contact instructions. If a check condition has been set with LDI or ANI, the processing for the check condition they specify will not be conducted. However, contact numbers during failure detection can also be allocated to the LDI and ANI instructions. Does not execute check X5 X7 X9 XA X1A X1C CHK Contact No.
CHKCIR,CHKEND 7.10.2 Changing check format of CHK instruction (CHKCIR,CHKEND) 1 CHKCIR,CHKEND Basic High performance Process Redundant Universal When the GX Developer is used (High Performance model QCPU/Process CPU/ Redundant CPU) 2 3 4 Command CHKST Refer to Section 7.10.1. CHKST X X X X CHK 6 CHK SM400 CHKCIR 6 CHKCIR Fn Fn Ladder pattern to be checked 7 Max.
CHKCIR,CHKEND (a) The device numbers indicated at check conditions (X2 and X8 in the figure below) will assume index modification values for the individual device numbers (with the exception of annunciators (F)) described in the ladder patterns. Example X10 in the in the figure below would be as follows: When corresponding to check condition X2 Processing performed by...X12 When corresponding to check condition X8 Processing performed by...
CHKCIR,CHKEND (b) Failure checks check the ON/OFF status of OUT F various check conditions. by using the ladder pattern in the 1 In all check conditions, SM80 will be turned ON if even one of the OUT F is ON in a ladder pattern. Further, the error numbers (contact numbers and coil numbers) corresponding to the OUT F (c) The instructions that can be used in ladder patterns are as follows: Contacts ... LD, LDI, AND, ANI, OR, ORI, ANB, ORB, MPS, MPP,MRD, and comparative operation instructions 3 4 Coil .
CHKCIR,CHKEND (4) The CHKCIR and CHKEND instructions can be written at any step in the program desired. It can be used in up to two locations in all program files being executed. However, the CHKCIR and CHKEND instructions cannot be used in more than 1 location in a single program file. (5) The CHKCIR and CHKEND instructions cannot be used in low speed execution type programs.
BINDA(P),DBINDA(P) 7.11 Character string processing instructions 1 7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII (BINDA(P),DBINDA(P)) 2 BINDA(P),DBINDA(P) Basic High performance 3 Process Redundant Universal 4 indicates an instruction symbol of BINDA/DBINDA.
BINDA(P),DBINDA(P) (3) The operation results stored at are as follows: D (a) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it is negative. (b) The sign "20H" will be stored for the leading zeros of effective digits. (Zero suppression is conducted.) 00325 Number of significant digits 20H is set (c) The storage of data at devices specified by D +3 differs depending on the ON/OFF status of SM701 (output number of characters conversion signal).
BINDA(P),DBINDA(P) Operation Error 1 (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The device specified by D exceeds the range of the corresponding device. (For the Universal model QCPU only.) (Error code: 4101) 2 3 Program Example (1) The following example program uses the PR instruction to output the 16-bit BIN data W0 value by decimal to Y40 to Y48 as ASCII.
BINHA(P),DBINHA(P) 7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII (BINHA(P),DBINHA(P)) BINHA(P),DBINHA(P) Basic High performance Process Redundant Universal indicates an instruction symbol of BINHA/DBINHA.
BINHA(P),DBINHA(P) DBINHA 1 (1) Converts the individual digit numbers of hexadecimal notation of the BIN 32-bit data designated by S into ASCII codes, and stores the results into the area starting from the device designated by D .
BINHA(P),DBINHA(P) Program Example (1) The following program uses the PR instruction to output the hexadecimal value of the 16-bit BIN data at W0 in ASCII code to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction Device [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.
BCDDA(P),DBCDDA(P) 7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data (BCDDA(P),DBCDDA(P)) 1 BCDDA(P),DBCDDA(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of BCDDA/DBCDDA.
BCDDA(P),DBCDDA(P) (4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF status of SM701 (number of characters to output select signal). When SM701 is OFF......Stores "0" When SM701 is ON .......Does not change DBCDDA (1) Converts the individual digit numbers of hexadecimal notation of the BCD 8-digit data designated by S into ASCII codes, and stores the results into the area starting from the device designated by D .
BCDDA(P),DBCDDA(P) Program Example 1 (1) The following program uses the PR instruction to convert BCD 4-digit data (the value at W0) to decimal, and outputs it in ASCII format to Y40 to Y48. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 6 [Operation] Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON. Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.
DABIN(P),DDABIN(P) 7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data (DABIN(P),DDABIN(P)) DABIN(P),DDABIN(P) High performance Basic Process Redundant Universal indicates an instruction symbol of DABIN/DDABIN.
DABIN(P),DDABIN(P) DDABIN 1 (1) Converts decimal ASCII data stored into the area starting from the device number designated by S into BIN 32-bit data, and stores it in the device number designated by b15 S S S S S S b8b7 +1 ASCII code for ten-millions place +2 ASCII code for hundred-thousands place +3 ASCII code for thousands place +4 ASCII code for tens place +5 (Ignored) b0 2 ASCII code for hundred-millions place ASCII code for hundreds place +1 +2 +3 +4 +5 (1) (3) (5) (3) (1) D b16b15 Up
DABIN(P),DDABIN(P) Program Example (1) The following program converts the decimal, 5-digit ASCII data and sign set at D20 through D22 to BIN values, and stores the result at D0.
HABIN(P),DHABIN(P) 7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data (HABIN(P),DHABIN(P)) 1 HABIN(P),DHABIN(P) Basic High performance 2 Process Redundant Universal 3 indicates an instruction symbol of HABIN/DHABIN.
HABIN(P),DHABIN(P) DHABIN (1) Converts hexadecimal ASCII data stored in the area starting from the device number designated by S into BIN 32-bit data, and stores it in the device number designated by b15 b8b7 b0 ASCII code for the 7th digit ASCII code for the 8th digit S S +1 ASCII code for the 5th digit ASCII code for the 6th digit S +2 ASCII code for the 3rd digit ASCII code for the 4th digit S +3 ASCII code for the 1st digit ASCII code for the 2nd digit b8b7 b15 S S +1 S +2 S +3 D 43H 38H 37H 31H
HABIN(P),DHABIN(P) Program Example 1 (1) The following program converts the hexadecimal, 4-digit ASCII data set at D20 and D21 to BIN data, and stores the result at D0.
DABCD(P),DDABCD(P) 7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data (DABCD(P),DDABCD(P)) DABCD(P),DDABCD(P) High performance Basic Process Redundant Universal indicates an instruction symbol of DABCD/DDABCD.
DABCD(P),DDABCD(P) DDABCD (1) Converts decimal ASCII data stored in the area starting from the device designated by 8-digit BCD data, and stores it into the area starting from the device designated by b15 S S +1 S +2 S +3 b8b7 D S to .
DABCD(P),DDABCD(P) Program Example (1) The following program converts the decimal ASCII data set from D20 to D22 to BCD 4-digit data, and outputs the results to Y40 to Y4F. [Ladder Mode] Outputs the converted BCD value to a display device.
COMRD(P) 7.11.
COMRD(P) (2) If no comment has been registered for the device specified by S despite the fact that the comment range setting is made, all of the characters for the comment are processed as "20H" (space). (3) The device number plus 1 where the final character of D is stored differs depending on the ON/OFF status of SM701 (number of characters to output select signal).
COMRD(P) Program Example 1 (1) The following program stores the comments set at D100 into the area starting from W0 as ASCII when X1C is turned ON.
LEN(P) 7.11.
LEN(P) Operation Error 1 (1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • There is no "00H" set within the relevant device range following the device number designated by S . 2 (Error code: 4101) 3 Program Example (1) The following program outputs the length of the character string from D0 to Y40 to Y4F as BCD 4-digit values. 4 [Ladder Mode] 6 Outputs the length of character string to a display device.
STR(P),DSTR(P) 7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR(P),DSTR(P)) STR(P),DSTR(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger. indicates an instruction symbol of STR/DSTR.
STR(P),DSTR(P) (2) The total number of digits that can be designated by (3) The number of digits that can be designated by 0 to 5. S1 S1 is from 2 to 8. +1 as a part of the decimal fraction is from However, the number of digits following the decimal point must be smaller than or equal to the total number of digits minus 3. (4) BIN data in the range between 32768 and 32767 can be designated at S2 1 2 .
STR(P),DSTR(P) DSTR (1) Adds a decimal point to the BIN 32-bit data designated by S1 D . Total number of digits b15 S1 +1 Number of digits in decimal fraction D D +1 .
STR(P),DSTR(P) (c) If the total number of digits following the decimal fraction is greater than the number of BIN data digits, a zero will be added automatically and the number converted by shifting to the right, so that it would become "0. Total number of digits Number of digits in decimal fraction BIN data ". 13 10 1 2 0 .
STR(P),DSTR(P) Program Example (1) The following program converts the BIN 16-bit data stored at D10 when X0 is turned ON in accordance with the digit designation of D0 and D1, and stores the result from D20 to D23. [Ladder Mode] Sets the data. Sets the total number of digits. Sets the number of digits in decimal fraction. [List Mode] Step Instruction Device [Operation] 7-210 D10 12672 D0 D1 7 1 b15 D20 D21 D22 D23 31H (1) 36H (6) 2E H (.) 00H b8b7 20H (space) 32H (2) 37H (7) 32H (2) b0 1267.
STR(P),DSTR(P) (2) The following program converts the BIN 32-bit data stored at D10 and D11 when X0 is turned ON in accordance with the digit designation of D0 and D1, and stores the result at from D20 to D26. 1 [Ladder Mode] 2 Sets the data. Sets the total number of digits. 3 Sets the number of digits in decimal fraction. 4 6 [List Mode] Step Instruction Device 6 7 [Operation] D10 D11 D10 12345678 D0 D1 12 9 30 H (0) 30 H (0) 32 H (2) 34 H (4) 36 H (6) 38 H (8) b8b7 20 H (space) 2EH (.
VAL(P),DVAL(P) 7.11.10 Conversion from character string to BIN 16-bit or 32-bit data (VAL(P),DVAL(P)) VAL(P),DVAL(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger (Correspording GX Seveloper :Version 8.00 A or later). indicates an instruction symbol of VAL/DVAL.
VAL(P),DVAL(P) For example, if the character string " 123.45" is designated for the area starting from the operation result would be stored at D1 and D2 b15 b8 b7 b0 31H (1) 33H (3) 34H (4) 00H 2DH 32 H 2EH 35 H ( ) (2) (.) (5) , in the following manner: D1 +1 (2) The total number of characters that can be designated as a character string at to 8. (3) From 0 to 5 characters from the character string designated at fraction part. S 2 12345 D2 1 2 3 .
VAL(P),DVAL(P) DVAL (1) Converts the character string stored in the area starting from the device designated by BIN 32-bit data, and stores the digits numbers and BIN data in D1 and D2 S to . For conversions from character strings to BIN, all data from the device number designated by S to the device number where "00H" is stored will be processed as character strings.
VAL(P),DVAL(P) (8) In cases where the character string designated by S contains "20H" (space) or "30H" (0) between the sign and the first numerical value other than "0", these "20H" and "30H" are ignored in the conversion into a BIN value. 6543 . 21 Total number of digits Number of digits in decimal fraction BIN data 12 2 1 2 6 5 4 3 2 1 Ignored 0 .
VAL(P),DVAL(P) Program Example (1) The following program reads the character string data stored from D20 to D22 as an integer, converts it to a BIN value, and stores it at D0 when X0 is ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] b15 D20 D21 D22 D23 b8b7 31H (1) 2E H (.
ESTR(P) 7.11.11 Conversion from floating decimal point to character string data (ESTR(P)) 1 ESTR(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
ESTR(P) b15 S2 Decimal point format S2 +1 Total number of digits S2 +2 Number of digits in decimal fraction D +1 ASCII code for the ASCII code for the (total number of digits -3) (total number of digits -2) th digit th digit D +2 ASCII code for the ASCII code for (total number of digits -5) decimal point (.) (2E H) th digit Sign S1 D +3 D +4 32-bit floating-point real number 7-218 b0 D .
ESTR(P) For example, in a case where there are 8 digits in total, with 3 digits in the decimal fraction part, and the value designated is starting from S2 S2 +1 S2 +2 D 1.23456, the operation result would be stored in the area in the following manner: 0 8 3 1 . 2 3 5 Sign D D +1 D +2 D +3 D +4 b15 20H (space) b8 b7 2 b0 2DH(-) 31H (1) 32H (2) 35H (5) 20H (space) 2EH (.) 33H (3) 3 00H Automatically stored at the end of character sting S1 +1 S1 -1.
ESTR(P) 4) If the total number of digits, excluding the sign, the decimal point and the decimal fraction part, is greater than the integer part of the 32-bit floating point type real number data, "20H (space)" will be stored between the sign and the integer part. S2 S2 +1 S2 +2 0 8 2 Total number of digits - S1+1 1 . 2 3 S1 Number of digits in decimal fraction -1 . 2 3 4 5 6 Filled with 20H (space) codes 5) The value "00H" is automatically stored at the end of the converted character string.
ESTR(P) (a) The total number of digits that can be designated by When the number of decimal fraction digits is "0" S2 +1 is as shown below: 1 .................... Number of digits (max.: 24) 2 When the number of decimal fraction digits is other than "0" .................... Number of digits (max.: 24) (Number of decimal fraction digits + 7) (b) The number of digits of dicimal fraction part that can be designated by S2 +2 is from 0 to 7.
ESTR(P) 5) The ASCII code "2CH" (+) will be stored as the sign for the exponent portion of the value if the exponent is positive in value, and the code "2DH" ( ) will be stored if the exponent is a negative value. 6) The exponent portion is fixed at 2 digits. If the exponent portion is only 1 digit, the ASCII code "30H" (0) will be stored between the sign and the exponent portion of the number. S2 S2 +1 Total number of digits (12) 1 12 4 S2 +2 Fixed to 2 digits 1 . 2 3 4 6 E+ 0 1 - S1 +1 -1 2 .
ESTR(P) Program Example 1 (1) The following program converts the 32-bit floating point type real number data which had been stored at R0 and R1 in accordance with the conversion designation that is being stored at R10 to R12, and stores the result following D0 when X0 goes ON. [Ladder Mode] [List Mode] Step Instruction 2 3 Device 4 [Operation] R10 R11 R12 0 7 3 Conversion format Total number of digits Number of digits in decimal fraction R0 R1 0 .
EVAL(P) 7.11.12 Conversion from character string to floating decimal point data (EVAL(P)) EVAL(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
EVAL(P) (b) When using exponent format S S +1 S +2 S +3 S +4 S +5 S +6 b15 20H (space) 2EH (.) 32H (2) 31H (1) 2BH (+) 30H (0) b8b7 1 b0 2DH (-) 31H (1) 33H (3) 30H (0) 45H (E) 31H (1) D +1 D 2 -1. 320 1E + 10 32-bit floating-point real number 00H 1 3 1 .
EVAL(P) (6) In a case where the ASCII code "20H (space)" or "30H" (0) exists between numbers not including the initial zero in a character string specified by S , it will be ignored when the conversion is done. S S S S S b15 20H (space) +1 31H (1) 32H (2) +2 31H (1) +3 +4 - b8b7 b0 2DH (-) 30H (0) 2EH (.) 33H (3) D +1 D -1 . 2 3 1 32-bit floating-point real number 00 0 1 .
EVAL(P) Program Example 1 (1) The following program converts the character string stored in the area starting from R0 to a 32-bit floating decimal point type real number, and stores the result at D0 and D1 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 3 4 [Operation] b15 R0 20H (space) R1 31H (1) R2 32H (2) R3 34H (4) 32H (2) R4 00H R5 b8b7 b0 2DH (-) 30H (0) 2EH (.) 33H (3) 35H (5) 31H (1) 6 D1 D0 -1 . 234 5 2 6 0 1 .
ASC(P) 7.11.
ASC(P) (2) The use of n to set the number of characters causes the BIN data range designated by and the character string storage device range designated by D S 1 to be set automatically. (3) Processing will be performed accurately even if the device range where BIN data to be converted is being stored overlaps with the device range where the converted ASCII data will be stored.
HEX(P) 7.11.
HEX(P) (3) Accurate processing will be conducted even in cases where the range of devices where the ASCII code to be converted is being stored overlaps with the range of devices that will store the converted BIN data.
RIGHT(P),LEFT(P) 7.11.15 Extracting character string data from the right or left (RIGHT(P),LEFT(P)) RIGHT(P),LEFT(P) Basic High performance Process Redundant Universal indicates an instruction symbol of RIGHT/LEFT.
RIGHT(P),LEFT(P) (2) The NULL code (00H) indicating the end of the character string is automatically appended at the end of the character string. Refer to 3.2.5 for the format of the character string data. (3) If the number of characters designated by n is "0", the NULL code (00H) will be stored at D .
RIGHT(P),LEFT(P) Program Example (1) The following program stores 4 characters of data from the rightmost of the character string stored in the area starting from R0, and stores it into the area starting from D0 when X0 is turned ON.
MIDR(P),MIDW(P) 7.11.16 Random selection from and replacement in character strings (MIDR(P),MIDW(P)) 1 MIDR(P),MIDW(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol MIDR/MIDW.
MIDR(P),MIDW(P) (2) The NULL code (00H) indicating the end of the character string is automatically added to the end of the character string. Refer to 3.2.5 for the format of the character string data. (3) No processing will be conducted if the number of characters designated by (4) If the number of characters designated by character designated by b15 S1 S1 +1 S1 +2 S1 +3 S1 +4 S1 +5 S b0 41 H (A) 43 H (C) 45 H (E) 47 H (G) 49 H (I) 4B H (K) +1 is "0".
MIDR(P),MIDW(P) (4) If the number of characters designated by character string data designated by D S2 +1 exceeds the final character from the , data will be stored up to the final character.
MIDR(P),MIDW(P) • The S2 +1 value exceeds the number of characters for • The S2 + 0 value is 0. S1 . (Error code: 4101) (Error code: 4101) • "00H" does not exist in the specified devices that follow the device specified for S1 . (Error code: 4101) Program Example (1) The following program stores the 3rd character through the 6th character from the left of the character string stored in the area starting from D10 at devices starting from D0 when X0 is turned ON.
INSTR(P) 7.11.
INSTR(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of n exceeds the number of characters for S2 . (Error code: 4100) • 00H (NULL) does not exist within the corresponding device range after the device designated by S1 , S2 . (Error code: 4100) • The value of n is negative number or “0”.
STRINS(P) 7.11.18 Insertion of character string (STRINS(P)) 1 STRINS(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. 2 QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
STRINS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The number of characters in the devices specified by ( S + D S , D , or the devices specified by ) after the insertion exceeds 16383 characters. (Error code: 4100) • The value specified by n is not within the specified range.
STRDEL(P) 7.11.19 Deletion of character string (STRDEL(P)) 1 STRDEL(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. 2 QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
STRDEL(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The number of characters in the devices specified by D • The value specified by n1 is not within the range. (1 n1 exceeds 16383. (Error code: 4100) 16383) (Error code: 4100) • The value specified by n1 exceeds the number of characters in the devices specified by D .
EMOD(P) 7.11.
EMOD(P) S1 S1 +1 0 . 03542768 S2 4 S1 +1 S1 1 . 5 4 3 2 1E + 2 S2 3 D D D D D +1 +2 +3 +4 D D D D D +1 +2 +3 +4 1 3542770H 1 4 1 1543210H 1 1 (2) The 7th digit of the significant digits being stored at 6-digit number. S1 +1 S1 D D D D D 1 .
EMOD(P) Program Example 1 (1) The following program breaks down the 32-bit floating decimal point type real number data stored at D0 and D1 into BCD according to the decimal fraction digits as designated by R10, and stores the results into the area starting from D100 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 3 4 [Operation] D1 D0 0.987654 R10 3 2 D100 D101 D102 D103 D104 1 6 9876540H 1 4 6 7 8 7.11 Character string processing instructions 7.11.
EREXP(P) 7.11.
EREXP(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The format designated by S1 was neither 0 nor 1. (Error code: 4100) • A value other than 0 to 9 exists in the each digit of • The format designation made by S1 S1 + 1 and S1 + 2. (Error code: 4100) + 3 is something other than 0 or 1. 2 3 (Error code: 4100) • The exponent data designated by S1 +4 is outside the range of from 0 to 38.
SIN(P) 7.12 Special function instructions 7.12.1 SIN operation on floating-point data (Single precision) (SIN(P)) SIN(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
SIN(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is 0. *2 (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *2: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.
SIND(P) 7.12.
SIND(P) Program Example 1 (1) The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores the results at D0 to D3 as 64-bit floating decimal point type real numbers. 2 [Ladder Mode] 3 Inputs an angle used for SIN operation ( 1 ). Converts the input angle into a 64-bit floating-point real number ( 2 ). 4 Converts the converted angle into a radian value ( 3 ). Executes SIN operation using the converted radian value ( 4 ).
COS(P) 7.12.3 COS operation on floating-point data (Single precision) (COS(P)) COS(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
COS(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is 0. *2 (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *2: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.
COSD(P) 7.12.
COSD(P) Program Example 1 (1) The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and stores results as 64-bit floating decimal point type real numbers at D0 to D3. 2 [Ladder Mode] 3 Inputs an angle used for COS operation ( 1 ). Converts the input angle into a 64-bit floating-point real number ( 2 ). 4 Converts the converted angle into a radian value ( 3 ). Executes COS operation using the converted radian value ( 4 ).
TAN(P) 7.12.5 TAN operation on floating-point data (Single precision) (TAN(P)) TAN(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
TAN(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Operation results are outside the range shown below: 2-126 2 2128 0, |operation result| (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) 3 • The value of the specified device is 0.
TAND(P) 7.12.
TAND(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: 0,2-1022 | value of specified device | < 21024 (Error code: 4140) • The value of the designated device is (Error code: 4140) 0.
ASIN(P) 7.12.
ASIN(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by S is outside the range of from 1.0 to 1.0.
ASIN(P) Program Example (1) The following program seeks the inverse sine of the 32-bit floating decimal point real number at D0 and D1, and outputs the angle to the 4 BCD digits at Y40 to Y4F.
ASIND(P) 7.12.
ASIND(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: 0,2 -1022 | value of specified device | < 2 • The value of the designated device is (Error code: 4140) 1024 0. (Error code: 4140) • The value specified by S is within the double-precision floating-point range and outside the range of -1.0 to 1.0.
ACOS(P) 7.12.
ACOS(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by S is outside the range of from 1.0 to 1.0.
ACOSD(P) 7.12.
ACOSD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is not in the following range: 0,2 -1022 | value of specified device | < 2 • The value of the designated device is (Error code: 4140) 1024 0. (Error code: 4140) • The value specified by S is within the double-precision floating-point range and outside the range of -1.0 to 1.0.
ATAN(P) 7.12.
ATAN(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range(For the Universal model QCPU only): (Error code: 4140) 0, 2-126 | Contents of designated device | < 2128 • The value of the specified device is 0.
ATAND(P) 7.12.
ATAND(P) Program Example (1) The following program seeks the inverse tangent of the 64-bit floating decimal point real number at D0 to D3, and outputs the angle to the 4 BCD digits at Y40 to Y4F. [Ladder Mode] Calculates an angle (radian value) by TAN operation ( 1 ). Converts the radian value into an angle ( 2 ). Converts the angle in 64-bit floating-point real number into an integer ( 3 ). Outputs the integer-converted angle to a display device ( 4 ).
RAD(P) 7.12.13 Conversion from floating-point angle to radian (Single precision) (RAD(P)) 1 RAD(P) Ver. High performance Basic Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
RAD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The contents of the designated device or the result of the addition are not "0", or not within the following range(For the Universal model QCPU only): (Error code: 4140) 0, 2-126 | Contents of designated device | < 2128 • The value of the specified device is 0.
RADD(P) 7.12.
RADD(P) Program Example (1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 64-bit floating decimal point type real number at D20 to D23. [Ladder Mode] Inputs an angle to be converted into a radian value ( 1 ). Converts the input angle into a 64-bit floating-point real number ( 2 ). Converts the converted angle into a radian value ( 3 ).
DEG(P) 7.12.15 Conversion from floating-point radian to angle (Single precision) (DEG(P)) 1 DEG(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
DEG(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value of the specified device is 0. *2 (For the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU) (Error code: 4100) *2: There are CPU modules that will not result in an operation error if 0 is specified. For details, refer to 3.2.4.
DEGD(P) 7.12.
DEGD(P) Program Example (1) The following program converts the radian value set with 64-bit floating decimal point type real number at D20 to D23 to angles, and stores the result as a BCD value at Y40 to Y4F. [Ladder Mode] Converts a radian value into an angle ( 1 ). Converts the angle in 64-bit floating-point real number into an integer ( 2 ). Outputs the converted integer to a display device ( 3 ). [List Mode] Step Instruction Device [Operations involved when the values at D20 to D23 are 1.
POW(P) 7.12.17 Exponentiation operation on floating-point data (Single precision) (POW(P)) 1 POW(P) Ver. Basic High performance Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
POW(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The values specified by 0, 2-126 S1 or S2 are out of the ranges shown below. | Specified value (Storage value) | < • The value of S1 or S2 is 0. (Error code: 4140) • The values in the operation result is within the range shown below.
POWD(P) 7.12.18 Exponentiation operation on floating-point data (Single precision) (POWD(P)) 1 POWD(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
POWD(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The values specified by -1022 S1 or S2 are out of the range shown below. | Set values (Storage values) | < 2 0, 2 • The value of S1 or S2 is (Error code: 4140) 1024 0. (Error code: 4140) • The values resulted from the operation is within the range shown below.
SQR(P) 7.12.19 Square root operation for floating-point data (Single precision) (SQR(P)) 1 SQR(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
SQR(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by S is a negative number. (Error code: 4100) • The contents of the designated device or the result of the addition are not "0", or not within the following range(For the Universal model QCPU only): (Error code: 4140) 0, 2-126 | Contents of designated device | < 2128 • The value of the specified device is 0.
SQRD(P) 7.12.
SQRD(P) Program Example (1) The following program seeks the square root of the value set by the 4 BCD digits from X20 to X2F, and stores the result as a 64-bit floating decimal point type real number at D0 to D3. [Ladder Mode] Inputs data used for square root operation ( 1 ). Converts the input data into a 64-bit floating-point real number ( 2 ). Executes square root operation ( 3 ).
EXP(P) 7.12.21 Exponent operation on floating-point data (Single precision) (EXP(P)) 1 EXP(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
EXP(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Operation results are outside the range shown below: (Error code: 4100) 2-126 | operation result | 2128 (For a High Performance model QCPU) 2-126 | operation result | 2128 (For a Basic model QCPU/Process CPU/Redundant CPU) • The value of the specified device is 0.
EXP(P) Program Example 1 (1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X27, and stores the results as a 32-bit floating decimal point real number at D0 and D1. 2 [Ladder Mode] 3 Inputs the data used for exponent operation ( 1 ). 4 Checks the range of the value for operation. *4 6 Converts the input data into a 32-bit floating-point real number ( 2 ). Executes exponent operation ( 3 ).
EXPD(P) 7.12.
EXPD(P) Program Example 1 (1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X31, and stores the results as a 64-bit floating decimal point real number at D0 to D3. 2 [Ladder Mode] 3 Inputs data used for exponent operation ( 1 ). Checks the range of the value used for operation. *1 Converts the input data into a 64-bit floating-point real number ( 2 ). Executes exponent operation ( 3 ).
LOG(P) 7.12.23 Natural logarithm operation on floating-point data (Single precision) (LOG(P)) LOG(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
LOG(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The value designated by S is negative. (Error code: 4100) • The value designated by S is 0.
LOGD(P) 7.12.
LOGD(P) Program Example 1 (1) The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 to D33. [Ladder Mode] Sets data used for natural logarithm operation ( 1 ). 3 Converts the operation data into a 64-bit floating-point real number ( 2 ). Executes natural logarithm operation ( 3 ).
LOG10(P) 7.12.25 Common logarithm operation on floating-point data (Single precision) (LOG10(P)) LOG10(P) Ver. Basic High performance Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
LOG10(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The value specified by S is negative. (Error code: 4100) • The value specified by S is 0. (Error code: 4100) • The value of the specified device is not in the following range. -126 (Error code: 4140) 128 | value of specified device | < 2 0,2 • The value specified by S is 0.
LOG10D(P) 7.12.26 Common logarithm operation on floating-point data (Double precision) (LOG10D(P)) LOG10D(P) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later.
LOG10D(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The value specified by S is negative. (Error code: 4100) • The value specified by S is 0. (Error code: 4100) • The value of the specified device is not in the following range: -1022 0,2 (Error code: 4140) 1024 | value of specified device | < 2 • The value of the specified device is 0.
RND(P),SRND(P) 7.12.27 Random number generation and series updates (RND(P),SRND(P)) RND(P),SRND(P) Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
RND(P),SRND(P) Operation Error 1 (1) There are no operation errors associated with the RND(P) or SRND(P) instructions. 2 Program Example 3 (1) The following program stores random number at D100 when X10 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device 4 (2) The following program updates a random number series according to the contents of D0 when X10 is turned ON. [Ladder Mode] [List Mode] Step 6 6 Instruction Device 7 8 7.12 Special function instructions 7.12.
BSQR(P),BDSQR(P) 7.12.
BSQR(P),BDSQR(P) BDSQR (1) Calculates the square root of the values designated by the device designated by S and . D D ( +1 and stores the results at S S +1 S ) 1 D +1 2 Integer part . Decimal fraction part 2-word data (2) BCD value of a maximum of 8 digits (0 to 99999999) can be designated by (3) The operation results of 0 and 9999. and D D S and S +1. 3 +1 are stored as their respective BCD values of between 4 (4) Operation results are rounded off from the fifth decimal place.
BSQR(P),BDSQR(P) (2) The following program calculates the square root of BCD value 74625813 and outputs the integer part of the result to the 4 BCD digits at Y50 to Y5F, and the decimal fraction part to the 4 BCD digits from Y40 to Y4F.
BSIN(P) 7.12.
BSIN(P) Program Example (1) The program example below calculates the SIN of 3-digit BCD data designated by X20 to X2B, and outputs a 1-digit BCD part to the integer part from Y50 to Y53, and a 4-digit BCD fraction part from Y40 to Y4F. Y60 is turned ON if the results of the operation are negative. (If a value has been set at X20 to X2F that is greater than 360, it will be adjusted to be in the range from 0 to 360.
BCOS(P) 7.12.
BCOS(P) Program Example (1) The following program calculates the cosine of the data designated by the 3 BCD digits from X20 to X2B and outputs the integer part of the result to 1 BCD digit from Y50 to Y53, and the decimal fraction part of the result to the 4 BCD digits from Y40 to Y4F. Y60 is turned ON if the results of the operation are negative.
BTAN(P) 7.12.
BTAN(P) Program Example (1) The following program calculates the tangent of the data stored in the 3 BCD digits from X20 to X2B, and stores the integer part of the results in the 4 BCD digits from Y50 to Y53, and the decimal fraction part in the 4 BCD digits from Y40 to Y4F. Y60 is turned ON if the results of the operation are negative.
BASIN(P) 7.12.
BASIN(P) Program Example (1) The following program performs a SIN-1 operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
BACOS(P) 7.12.
BACOS(P) Program Example (1) The following program performs a COS-1 operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
BATAN(P) 7.12.
BATAN(P) Program Example (1) The following program performs a TAN-1 operation on the sign (positive when X0 is OFF, and negative when X0 is ON), the BCD 4-digit integer part from X20 to X2F and the BCD 4-digit decimal fraction part from X30 to X3F, and outputs the calculated angle in 4 BCD digits from Y40 to Y4F.
LIMIT(P),DLIMIT(P) 7.13 Data Control Instructions 1 7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data (LIMIT(P),DLIMIT(P)) 2 LIMIT(P),DLIMIT(P) Basic High performance Process Redundant Universal 3 4 indicates an instruction symbol of LIMIT/DLIMIT.
LIMIT(P),DLIMIT(P) (3) When control based only on upper limit values is performed, the lower limit value designated at S1 is set at " 32678". (4) When control based only on lower limit values is performed, the upper limit value designated at S2 is set at "32767".
LIMIT(P),DLIMIT(P) Program Example 1 (1) The following program conducts limit controls from 500 to 5000 on the data set as BCD values from X20 to X2F, and stores the result at D1 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 6 [Operation] • D1 becomes 500 if D0 Example 500. D0 400 D1 500 • D1 becomes the value of D0 when 500 Example 6 5000. D0 1300 D1 1300 • D1 becomes 5000 when 5000 Example D0 7 D0.
BAND(P),DBAND(P) 7.13.2 BIN 16-bit and 32-bit dead band controls (BAND(P),DBAND(P)) BAND(P),DBAND(P) Basic High performance Process Redundant Universal indicates an instruction symbol of BAND/DBAND.
BAND(P),DBAND(P) (3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results exceed the range of from 32768 to 32767, the following will take place: Dead band lower limit value When : Input value Output value S3 .................10 S1 ............................................
BAND(P),DBAND(P) Program Example (1) The following program performs the dead band control by applying the lower and upper limits of 0 and 1000 for the data set in BCD at X20 to X2F and stores the result of control at D1 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction Device [Operation] • "0" is stored at D1 if 0 D0 1000. Example D0 500 D1 0 • The value of (D0) Example 1000 is stored at D1 if 1000 D0.
ZONE(P),DZONE(P) 7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE(P),DZONE(P)) 1 ZONE(P),DZONE(P) Basic High performance Process Redundant Universal 2 3 indicates an instruction symbol of ZONE/DZONE.
ZONE(P),DZONE(P) (2) The values that can be designated by 32767. S1 , S2 , and S3 are in the range of from 32768 to (3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results exceed the range of 32768 to 32767, the following will take place: Negative bias value When : Input value Output value S3 S1 .............................. 100 ............................................
ZONE(P),DZONE(P) Program Example 1 (1) The following program performs zone control by applying negative and positive bias values of 100 to 100 for the data set at D0 and stores the result of control at D1 when X0 is turned ON. [Ladder Mode] 2 [List Mode] Step Instruction 3 Device 4 [Operation] • The value (D0) + ( 100) is stored at D1 if D0 Example D0 200 D1 • The value 0 is stored at D1 if D0 300 6 0. • The value of (D0) + 100 is stored at D1 if 0 Example 6 0. D0.
(SCL(P),DSCL(P)) 7.13.4 Scaling (Point-by-point coordinate data) (SCL(P),DSCL(P)) (SCL(P),DSCL(P)) Ver. High performance Basic Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of SCL/DSCL. Command SCL.DSCL S1 S2 D S1 S2 D Command SCLP.
(SCL(P),DSCL(P)) (5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output. 1 (6) Specify the number of coordinate points of scaling conversion data from 1 to 32767. DSCL(P) (1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified by S2 with the input value specified S1 , and then stores the operation result into the devices specified by D .
(SCL(P),DSCL(P)) (1) There are two searching methods that depend on whether SM750 is on or off. SM750 Searching method Range of number of searches OFF Sequential search 1 Number of times 32767 ON Binary search 1 Number of times 15 (2) When the scaling conversion data are set in ascending order, the searching methods change from one to the other depending on the SM750 status. Therefore, the processing speed also changes. The number of searches determines the processing speed.
(SCL(P),DSCL(P)) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The X coordinates of the scaling conversion data positioned before the point specified by S1 are not set in ascending order. (However, this error is not detected when SM750 is on.) (Error code: 4100) • The input value specified by S1 is out of the range of the scaling conversion data set.
SCL2,DSCL2 7.13.5 Scaling (Point-by-point coordinate data) (SCL2(P),DSCL2(P)) SCL2,DSCL2 Ver. Basic High performance Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of SCL/DSCL. Command SCL.DSCL S1 S2 D S1 S2 D Command SCLP.
SCL2,DSCL2 (4) Set the input value devices). S1 within the range of the scaling conversion data (within the range of S2 (5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output. DSCL2(P) (1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified by S2 with the input value specified S1 S2 3 and up.
SCL2,DSCL2 Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. • The X coordinates are not set in ascending order. • The input value specified by S1 (Error code: 4100) is out of the range of the scaling conversion data set. (Error code: 4100) • The number of X and Y coordinates of the device specified by 1 to 32767. • The number of X and Y coordinates of the device specified by range.
RSET(P) 7.14 File register switching instructions 1 7.14.
RSET(P) Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The block number designated by S does not exist. (Error code: 4100) • There is no file register for the specified block No. (Error code: 4101) Program Example (1) The following program compares R0 of block No. 0 and block No. 1. [Ladder Mode] Designates block No. 0 Executes reading R0 of block No.0 Designates block No.
QDRSET(P) 7.14.2 Setting files for file register use (QDRSET(P)) 1 QDRSET(P) Basic High performance Process Redundant Universal 2 3 Command QDRSET QDRSET S QDRSETP S 4 Command QDRSETP 6 S Setting Data : Character string data of the drive No.
QDRSET(P) (2) Drive number can be designated from 1 to 4. (The drive number cannot be designated as drive 0 (program memory/internal memory).) Note that available drives vary depending on the CPU module used. Refer to the manual of the CPU module and check the drives that can be specified. (3) It is not necessary to designate the extension (.QDR) with the file name. (4) A file name setting can be deleted by designating the NULL character (00H) for the file name.
QDRSET(P) Program Example 1 (1) The following program compares R0 of ABC in block No. 1 and R0 of DEF in block No. 1. [Ladder Mode] 2 3 4 6 6 [List Mode] Step Instruction 7 Device 8 7.14 File register switching instructions 7.14.2 Setting files for file register use (QDRSET(P)) [Operation] Block No. 0 R0 R1 R2 R3 R4 R5 -3216 5001 128 -7981 9610 0 Block No.
QCDSET(P) 7.14.3 File setting for comments (QCDSET(P)) QCDSET(P) Basic High performance Process Redundant Universal Command QCDSET QCDSET S QCDSETP S Command QCDSETP S Setting Data : Character string data of the drive No.
QCDSET(P) (4) A file name setting can be deleted by designating the NULL character (00H) for the file name. (5) File names designated with this instruction will be given priority even if a drive number and file name have been designated in the parameters. (6) This instruction cannot be executed while SM721 is ON for the Universal model QCPU. No operation if executed.
DATERD(P) 7.15 Clock instructions 7.15.
DATERD(P) Program Example 1 (1) The following program outputs the following clock data as BCD values: Year .......... Y70 to Y7F Month ....... Y68 to Y6F Day ........... Y60 to Y67 Hour.......... Y58 to Y5F Minute....... Y50 to Y57 Second ..... Y48 to Y4F Week ........ Y44 to Y47 2 3 4 [Ladder Mode] 6 Outputs "Year" Outputs "Month" 6 Outputs "Day" Outputs "Hour" 7 Outputs "Minute" Outputs "Second " 8 Outputs "Day of week" Step Instruction 7.15 Clock instructions 7.15.
DATEWR(P) 7.15.2 Writing clock data (DATEWR(P)) DATEWR(P) Basic High performance Process Redundant Universal Command DATEWR DATEWR S DATEWRP S Command DATEWRP : Head number of the devices where clock data to be written into the clock device is stored (BIN 16 bits) S Setting Data S Internal Devices Bit R, ZR Word J \ Bit Word U Zn \G –– Constants Other –– Function (1) Writes clock data stored in the device number designated by the clock element of the CPU module.
DATEWR(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Individual items of data have been set outside the setting range. 2 (Error code: 4100) • The device specified by S exceeds the range of the corresponding device. (For the Universal model QCPU only.
DATE+(P) 7.15.
DATE+(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data set by S1 and S2 is outside the setting range. (Error code: 4100) • The device specified by S1 or S2 or D exceeds the range of the corresponding device. (For the Universal model QCPU only.
DATE-(P) 7.15.
DATE-(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The data set by S1 and S2 is outside the setting range. (Error code: 4100) • The device specified by S1 or S2 or D exceeds the range of the corresponding device. (For the Universal model QCPU only.
SECOND(P) 7.15.
SECOND(P) Program Example 1 (1) The following program converts the clock time data read from the clock element into second when X20 is turned ON, and stores the result at D100 and D101. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 6 [Operation] • Time data read operation triggered by DATERDP instruction.
HOUR(P) 7.15.
HOUR(P) Program Example 1 (1) The following program converts the seconds stored at D0 and D1 into an hour, minute, second format, and stores the result at devices starting from D100 when X20 is turned ON. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 [Operation] • Conversion to hour minute, and second format by the HOURP instruction (when the value 40000 seconds has been designated by D1 and D0). D1,D0 40000 D100 D101 D102 11 6 40 4 6 6 7 8 7.15 Clock instructions 7.15.
(DT=,DT<>,DT>,DT<=,DT<,DT>=) 7.15.7 Date comparison (DT=,DT<>,DT>,DT<=,DT<,DT>=) (DT=,DT<>,DT>,DT<=,DT<,DT>=) Ver. Basic High performance Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. indicates an instruction symbol of DT=/DT<>/DT<=/DT>/DT>=.
(DT=,DT<>,DT>,DT<=,DT<,DT>=) When either S1 or S2 corresponds to any of the following in comparing given or current date data with given date data, the operation error (error code: 4101) or a malfunction may occurs. • The range of the devices to be used for the index modification is specified over the range of the device specified by • File registers are specified by S1 or S1 or S2 without a register set.
(DT=,DT<>,DT>,DT<=,DT<,DT>=) (c) The following table shows processing details of bits to be compared.
(DT=,DT<>,DT>,DT<=,DT<,DT>=) (a) The following figure shows the comparison example of dates. A 2006/1/1 B 1 C 2007/1/1 2008/1/1 2009/1/1 (2006/9/22) (2007/6/23) (2008/8/8) The following table shows the conductive states resulting from performing the comparison operation of the dates A, B, and C shown above. Even if the objects to be compared are under the same condition, the comparison operation results vary depending on the objects selected.
(DT=,DT<>,DT>,DT<=,DT<,DT>=) Operation Error (1) Any operation errors do not occur in DT=,DT<>,DT>,DT<=,DT<,DT>= instruction. Program Example (1) The following program compares the data stored in D0 with the data (year, month, and day) stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the data stored in D10.
(TM=,TM<>,TM>,TM<=,TM<,TM>=) 7.15.8 Clock comparison (TM=,TM<>,TM>,TM<=,TM<,TM>=) 1 (TM=,TM<>,TM>,TM<=,TM<,TM>=) Ver. Basic High performance Process Redundant Universal QnU(D)(H)CPU: The serial number (first five digits) is "10102" or later. 2 QnUDE(H)CPU: The serial number (first five digits) is "10102" or later. (TM=,TM<>,TM>,TM<=,TM<,TM>=) 3 indicates an instruction symbol of DT LD /DT /DT /DT S1 S2 n S1 S2 n S1 S2 n /DT /DT .
(TM=,TM<>,TM>,TM<=,TM<,TM>=) (b) Comparison of current time data • This instruction treats the clock data specified by S1 and the current time data as a normally open contact, and compares the data in accordance with the value of n. • This instruction treats the clock data specified by data.
(TM=,TM<>,TM>,TM<=,TM<,TM>=) (c) The following table shows processing details of bits to be compared.
(TM=,TM<>,TM>,TM<=,TM<,TM>=) (a) The following figure shows the comparison example of time. A 0 Midnight 6:00 4:50:55 B C 18:00 0 Midnight N00n 22:47:05 14:08:58 The following table shows the conductive states resulting from performing the comparison operation of the dates A, B, and C shown above. Even if the objects to be compared are under the same condition, the comparison operation results vary depending on the objects selected.
(TM=,TM<>,TM>,TM<=,TM<,TM>=) Program Example 1 (1) The following program compares the data stored in D0 with the data (hour, minute, and second) stored in D10, and makes Y33 be conductive status when the data stored in D0 meet the data stored in D10.
S(P).DATERD 7.16 Expansion Clock Instructions 7.16.1 Reading expansion clock data (S(P).DATERD) S(P).DATERD Ver. Basic High performance Ver. Ver. Process Redundant Universal The first 5 digits of the serial No. are "07032" or higher. Command S.DATERD S.DATERD D SP.DATERD D Command SP.
S(P).DATERD Program Example 1 (1) The following program outputs the following clock data as BCD values: Year .................... Y70 to Y7F Month ................. Y68 to Y6F Day ..................... Y60 to Y67 Hour.................... Y58 to Y5F Minute................. Y50 to Y57 Second ............... Y48 to Y4F Week .................. Y44 to Y47 Millisecond..........
S(P).DATERD Caution (1) This instruction reads clock data and stores those to a specified device even if a wrong clock data is set to the CPU module. (example: Feb. 30th) When setting clock data with the DATEWR instruction or GX Developer, make sure to set a correct data. (2) Time error of reading a clock data of millisecond is a maximum of 2ms. (Difference between the data memorized by clock element inside of the CPU module and the data read by this function.
S(P).DATE+ 7.16.2 Expansion clock data addition operation (S(P).DATE+) 1 S(P).DATE+ Ver. Basic Ver. High performance Ver. Process Redundant Universal The first 5 digits of the serial No. are "07032" or higher. 2 3 Command S.DATE+ S.DATE+ S1 S2 D SP.DATE+ S1 S2 D 4 Command SP.
S(P).DATE+ (2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the sum to make the final operation result. For example, when the time 20:20:20:500 is added to 14:20:30:875, the result is not 34:40:51:375, but 10:40:51:375.
S(P).DATE+ Program Example 1 (1) The following program adds 1 hour to the clock data read from the clock element, and stores the results into the area starting from D100 when X20 is turned ON. [Ladder Mode] Reads out the clock element data to D0 or later. 2 3 Sets the time to D10 or later. 4 6 6 [List Mode] Step Instruction 7 Device 8 7.16 Expansion Clock Instructions 7.16.2 Expansion clock data addition operation (S(P).DATE+) [Operation] • Time data read operation by the SP.
S(P).DATE- 7.16.3 Expansion clock data subtraction operation (S(P).DATE-) S(P).DATE- Ver. Basic Ver. High performance Ver. Process Redundant Universal The first 5 digits of the serial No. are "07032" or higher. Command S.DATE- S.DATE- S1 S2 D SP.DATE- S1 S2 D Command SP.
S(P).DATE- (2) If the subtraction results in a negative number, 24 will be added to the result to make a final operation result. For example, when the clock time 10:42:12:500 is subtracted from 4:50:32:875, the result is not 6:8:20:375, but 18:8:20:375.
S(P).DATE- Program Example (1) The following program subtracts the time data stored in the area starting from D10 from the clock data read from the clock element when X1C is turned ON, and stores the result into the area starting from D100. [Ladder Mode] Reads out the clock element data to D0 or later. Sets the time to D10 or later. [List Mode] Step Instruction Device [Operation] • Time data read operation by the SP.
7.17 Program control instructions 1 (1) Processing when the execution type is converted with the program control instruction is as follows. Executed Instruction 3 Execution type before change PSCAN Scan execution type PSTOP No change-remains POFF Stand-by type that. No change-remains stand-by type Low speed execution type execution is Low speed execution type from the next scan after Becomes scan execution type. stopped, becomes scan execution type from the next scan.
(2) As program execution type conversions by PSCAN and PSTOP instructions occur at the END processing, such conversions are impossible during program execution. When different execution types have been set for the same program in the same scan, the execution type will be that specified by the execution switching command that was executed last.
PSTOP(P) 7.17.
POFF(P) 7.17.
POFF(P) Remark 1. Non-execution processing is identical to the processing that is conducted when the condition contacts for the individual coil instructions are in the OFF state.
PSCAN(P) 7.17.
PSCAN(P) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The program with the file name specified by S does not exist. 2 (Error code: 2410) • The file name storage destination device of device. S exceeds the range of the corresponding (Error code: 4101) • The specified file name is the SFC program, and the SFC program for the other file name has been already started.
PLOW(P) 7.17.
PLOW(P) Program Example 1 (1) The following program sets the program with file name ABC as low-speed execution type when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 6 6 7 8 7.17 Program control instructions 7.17.
PCHK 7.17.
PCHK Remark Non-execution indicates that the program execution type is a stand-by type. Execution indicates that the program execution type is a scan execution type (including during output OFF (during non-execution processing)), low speed execution type or fixed scan execution type. 1 2 3 The PCHK instruction is in conduction when the program of the specified file name (target program) is in execution, and the instruction is in non-conduction when the program is in non-execution.
WDT(P) 7.18 Other instructions 7.18.1 Resetting watchdog timer (WDT(P)) WDT(P) Basic High performance Process Redundant Universal Command WDT WDT Command WDTP WDTP Setting Data Internal Devices Bit Word J R, ZR Bit \ U Word –– \G Zn Constants Other –– Function (1) Resets watchdog timer during the execution of a sequence program. (2) Used in cases where the scan time exceeds the value set for the watchdog timer due to prevailing conditions.
WDT(P) Operation Error 1 (1) There are no operation errors associated with the WDT(P) instruction. 2 Program Example (1) The following program has a watchdog timer setting of 200 ms, when due to the execution conditions program execution requires 300 ms from step 0 to the END (FEND) instruction. 4 [When WDT instruction is used] Program where scan time is 300 ms. Program where scan time is 150 ms. 6 WDT END 3 Program where scan time is 150 ms. 6 END 7 8 7.18 Other instructions 7.18.
DUTY 7.18.2 Timing pulse generation (DUTY) DUTY Basic High performance Process Redundant Universal Command DUTY DUTY n1 n2 D n1 : Number of scans for ON (BIN 16 bits) n2 : Number of scans for OFF (BIN 16 bits) : User timing clock (SM420 to SM424, SM430 to M434) (bits) D Setting Data Internal Devices Bit Word J R, ZR \ Bit U Word \G Constants K, H Zn n1 –– n2 D Other –– *1 –– –– *1: Only SM420 to SM424, SM430 to SM434 can be used.
DUTY Program Example 1 (1) The following program turns SM420 ON for 1 scan, and OFF for 3 scans if X0 is ON. [Ladder Mode] [List Mode] Step 2 Instruction Device 3 4 [Operation] ON X0 OFF 6 ON SM420 OFF 1 scan 3 scans 6 7 8 7.18 Other instructions 7.18.
TIMCHK 7.18.3 Time check instruction (TIMCHK) TIMCHK Ver. Basic High performance Process Redundant Universal Basic model QCPU: The upper five digits of the serial No. are "04122" or larger.
ZRRDB(P) 7.18.
ZRRDB(P) (a) If the value of n has been designated as 23560, the data at the lower 8 bits of ZR11780 will be read. n 23560 Read destination b0 b15 b8 b7 designation ZR11780 43H 21H b8 b7 b15 D 00H b0 21H Data is stored (b) If the value of n has been designated as 43257, the data at the upper 8 bits of ZR21628 will be read.
ZRWRB(P) 7.18.
ZRWRB(P) If n 12340 is specified, the data will be written to the lower 8 bits of ZR11170. n Write destination b0 b15 b8 b7 designation 43H 21H ZR11170 12340 b15 b8 b7 43H S b15 b8 b7 b0 54H Ignored b0 54H If n 43257 is specified, the data will be written to the upper 8 bits of ZR21628.
ADRSET(P) 7.18.
KEY 7.18.
KEY (2) Numerical input to input (X) designated by S S undergoes bit development at S through +7 and is input as the ASCII code corresponding to the numbers. ASCII code which can be input is from 30H (0) to 39H (9), and from 41H (A) to 46H (F). (1 H) (3 H) b7 b4 b3 b0 "1"(31 H)= 0 0 1 1 0 0 0 1 Input module 2 S S +1 S +2 S +3 S +4 S +5 S +6 S +7 (3) After ASCII code is input to S to designated numbers internally.
KEY (7) Fetching of the input data is completed when any of the inputs shown below has been made. At the completion, the bit device designated by D2 is turned ON.
KEY Program Example 1 (1) The following program fetches data of the 5 or fewer digits from the numerical key pad connected to X20 to X28, and stores it to the area starting from D0 when X0 is turned ON. [Ladder Mode] 2 3 Clears the previous input data Sets the number of digits to be input 4 6 Resets the data input completion fag 6 [List Mode] Step Instruction 7 Device 8 7.18 Other instructions 7.18.
ZPUSH(P),ZPOP(P) 7.18.8 Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) ZPUSH(P),ZPOP(P) Basic High performance Process Redundant Universal indicates an instruction symbol of ZPUSH/ZPOP.
ZPUSH(P),ZPOP(P) • When using a High Performance model QCPU/Process CPU/Redundant CPU D +0 Number of saves +1 Z0 +2 Z1 1 1st nesting (18 words for the 1st nesting) +16 +17 +18 +19 +20 2 Z15 Reserved by the system (2 words) Z0 Z1 3 2nd nesting • When Universal model QCPU is used 4 D +0 Number of saves +1 Z0 +2 Z1 6 1st nesting (22 words for the 1st nesting) +20 +21 +22 +23 +24 Z19 6 Reserved by the system (2 words) Z0 Z1 2nd nesting 7 ZPOP (1) Recovers the contents saved in the area starting
UNIRD(P) 7.18.
UNIRD(P) The details of the module information are described as follows: Bit 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Individual module information Bit Item b0 b1 Number of I/O points b2 b4 Module type b5 b7 000: 16 points 001: 32 points 010: 48 points 011: 64 points 100: 128 points 101: 256 points 110: 512 points 111: 1024 points 3 000: Input module b3 b6 2 Meaning 001: Output module 4 010: I/O mixed module 011: Intelligent function module External supply power s
UNIRD(P) Program Example (1) The following program stores the module information at I/O numbers 10H to 20H into the devices starting from D0 when X10 is turned ON.
UNIRD(P) (b) 32-point module for A series 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 D0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 For an A series module, all of these bits turn 0 because information is not stored. 2 A series module 3 Module is installed b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 All of these bits turn 0 because information is stored to "D0.
7.18.10 Reading module model name(TYPERD(P)) Ver. High performance Basic Process Redundant Universal Universal model QCPU: The serial number (first five digits) is "11043" or later. Command TYPERD TYPERD n D TYPERDP n D Command TYPERDP .
(2) Specify the start I/O number of a module whose model name is to be read by "n" as follows: • Specify the value obtained by dividing the start I/O number of the target module by 16. 1 Power CPU supply module QX10 QX10 QX10 module 2 QX10 Q68 ADV QY41 P QY10 QY10 3E00H 0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Start I/O number configured in the I/O assignment setting 3 Specify the start I/O number by K3 or H3.
(3) D +0 and D +1 to D +9 store the execution result of the instruction and module model name, respectively. A value stored in D is as follows: (a) When the model name has been written to the target module (example: QJ71GP21-SX) b15 to b8 b7 b0 0 D +0 D +1 Nine words are used. to 4AH (J) Stores 0. Indicates that the model name that has been written to the target module is stored.
[Character string indicating the number of points] • 16 points:_16 1 • 32 points:_32 • 48 points:_48 2 • 64 points:_64 • 128 points:_128 3 • 256 points:_256 • 512 points:_512 • 1024 points:_1024 4 (c) Others • The specified slot is empty or the target module is during online module change. • The specified value (n) is not the start I/O number. • The specified value (n) is within the allowable setting range, but cannot be set in the I/O assignment setting screen of the PLC parameter dialog box.
Program Example (1) The following program stores the model name of a module having the start I/O number 0020H in the area starting from the device specified by [Ladder Mode] Step 7-410 D when X0 is turned on.
TRACE,TRACER 7.18.11 Trace Set/Reset (TRACE,TRACER) 1 TRACE,TRACER Basic High performance Process Redundant Universal 2 3 Command TRACE TRACE 4 Command TRACER TRACER 6 Setting Data Internal Devices Bit Word R, ZR J Bit \ U Word –– Zn \G Constants Other 6 –– Function The sampling trace function collects the specified device data of a CPU module consecutively at the specified timing.
TRACE,TRACER TRACE (1) The TRACE instruction turns ON SM803, executes sampling by the number of times set for "After trigger number of times" in the Trace condition settings, latches the data and stops sampling trace. (2) The sampling is stopped if SM801 is turned OFF during the trace execution. (3) After the TRACE instruction is executed and the trace is completed, SM805 is turned ON. (4) Once the TRACE instruction is executed, the second and the subsequent TRACE instructions are ignored.
SP.FWRITE 7.18.12 Writing Data to Designated File (SP.FWRITE) 1 SP.FWRITE High performance Basic Process Redundant Universal 2 3 Command SP.FWRITE U0 SP.
SP.FWRITE Setting Meaning Data Setting Range Set by Data Type When binary write is specified at D0 , always set 0. When CSV format write is specified at D0 , No. of D0 +6 columns set the number of columns where data will be designation 0 D0 0H to FFFFH written. : No columns. Regarded as User (0 to 65535) one row. Other than 0 : Set to the specified number of columns. D0 +7 Data type 0: Word specification 1: Byte 0,1 User Head number of the devices storing a file name.
SP.FWRITE Caution (1) At 1 S0 (drive designation), only the ATA card drive (2) can be set. Note that when the Flash card is loaded, the SP.FWRITE instruction cannot be used to perform writing. The SRAM card, standard RAM or standard ROM drive cannot be set. 2 3 (2) For CSV setting, the data written are decimal values. Example Character "A" (41H) "65" is written. Handling range: -32768 to 32767 (3) For binary write, the word-specified file position setting range is 00000000H to 7FFFFFFFH and FFFFFFFFH.
SP.FWRITE Function (1) The designated number of data is written to the designated file. Set the execution/completion type in the control data to designate whether to write binary data without any conversion or to convert binary data into CSV format data before writing it. (The writing target is the ATA card only.) (2) The execution completion bit device ( D1 ) is automatically turned ON at the END processing after the completion of the instruction is detected.
SP.FWRITE (4) When writing binary data (a) If the extension of the target file is omitted, ".BIN" is used as an extension. (b) When the designated file does not exist, a new file is created and the data is added/ saved from the beginning of the file. The attributes of this new file are set using the archive attributes. (c) When the size of the data exceeds that of the existing area in the file during the writing, the excess data is added/saved.
SP.FWRITE (e) When the designated number of columns is "0", the data is stored as single-row data in CSV format file. Example When data is written after CSV format conversion and the designated No. of columns is "0": SP.FWRITE U0 K2 D10 D20 D99 M0 * Designation in word units D10 H0100 Execution/completion type D11 - D12 K0 D13 - Not used Number of written result data (In normal completion, it is the same number as the number of data to be written.
SP.FWRITE (f) When data is written after CSV format conversion and the designated number of columns is other than "0", the data is stored as table data with designated number of columns in a CSV format file. Example When data is written after CSV format conversion and the designated No. of columns is other than "0": 1 2 3 SP.
SP.FWRITE (g) When data is added by the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU of which the first 5 digits of the serial number are 01112 or higher: [Specify the file to which data will be written.] (If a file exists, delete it and create a new file again.
SP.FWRITE Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • Drive specified by drive designation device card. • Values specified in control data range. S0 contains the medium other than the ATA (Error code: 4100) 2 and the subsequent devices are out of the setting (Error code: 4100) 3 • Value designated by "No.
SP.FWRITE Program Example (1) When X10 is turned ON, the following program adds four bytes of binary data (00H, 01H, 02H, and 03H) to file "ABCD.BIN" in the memory card inserted to drive 2. • Assume that 8 points from D0 are reserved for the control data devices. [Ladder Mode] Sets the execution/completion type Sets the file position Sets the file name Sets the number of request write data Sets the data to be written.
SP.FWRITE (2) When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the memory card inserted to drive 1, and writes four bytes of data (00H, 01H, 02H, and 03H) as two-column table data in CSV format. 1 • The written file is displayed as follows: [Ladder Mode] 2 Sets the execution/completion type Sets the designation of the number of columns 3 Sets the file name 4 Sets the number of request write data Sets the data to be written.
SP.FREAD 7.18.13 Reading Data from Designated File (SP.FREAD) SP.FREAD High performance Basic Process Redundant Universal Command SP.FREAD SP.FREAD Setting Data Internal Devices Bit R, RZ Word J Bit \ Word U D0 S0 U0 S1 Zn \G D1 Constants K, H –– S0 D2 $ Other –– –– D0 –– –– –– –– –– S1 –– –– –– –– –– D1 –– –– –– –– –– D2 *1 *1 –– –– –– *1: Local devices and the devices designated for individual programs cannot be used.
SP.FREAD Setting Meaning Data Setting Range Set by Data Type Designate the file position to start reading when binary data reading is designated by D0 . 00000000H: Starting at the beginning of the file 00000001H to FFFFFFFEH :From the designated position The unit for the value is determined by word/byte unit designation.
SP.FREAD Setting Meaning Data Setting Range Set by Setting Range Set by Data Type Bit device that turned ON at the completion of the processing. ( D2 +1 is also turned ON at error completion.) Device D2 D2 D2 +1 Item Contents/Setting Data Completion signal Indicates the completion of the processing. ON: Completed OFF: Not completed Error completion signal Indicates whether the processing is normally completed or abnormally completed.
SP.FREAD (3) Be sure to use word units to designate the number of request read data ( D0 +2), file position ( D0 +4 and D0 +5), and read data device size ( D1 ). The following shows how the individual device data is read in binary data reading operation.
SP.FREAD (e) When the designated number of columns is 0, the data is read by ignoring the rows in CSV format file. Example When data is read after CSV format conversion and the designated No. of columns is 0: Data created by EXCEL Measured value Main / sub item Length Temperature Data saved in the CSV format Main / sub item , , Measured value CR LF Length , 1 , 3 CR LF Temperature , -21 , CR LF Data to be read into devices SP.
SP.FREAD If the number of columns varies in each row, the data is also read by ignoring the rows. 1 Such file cannot be created using EXCEL. This happens when CSV file is modified by a user. 2 Example If the number of columns varies in each row when the data is read: 3 Main / sub item , , Measured value , Excess CR LF Length CR LF Temperature , -21 , CR LF 4 6 Data to be read into devices SP.
SP.FREAD (f) When data is read after CSV format conversion and the designated number of columns is other than 0, the data is read as the table with designated number of columns in CSV format file. The elements outside of the designated columns are ignored. Example When data is read after CSV format conversion and the designated No.
SP.FREAD If the number of columns varies in each row, the elements outside of the designated columns are ignored and "0" is added to the places where elements do not exist. 1 Example 2 If the number of columns varies in each row when the data is read: Main / sub item , , Measured value , Excess CR LF Length CR LF Temperature , -21 , CR LF Elements outside the designated number of columns are ignored. 3 4 Data to be read into devices SP.
SP.FREAD (g) With the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU whose first 5 digits of the serial number are "01112" or later, it is possible to divide read operation into multiple times. [Specify the row desired to start read.
SP.FREAD (h) When data is read after CSV format conversion, the numerical values that are out of range or the elements other than numerical values in the object CSV format file are converted into 0H.
SP.FREAD Program Example (1) The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in the memory card inserted to drive 2 when X10 is turned ON. • Assume that 8 points from (D0) are reserved for the control data devices. • Assume that 100 bytes from D20 are reserved for the reading devices.
SP.FREAD (2) The following program reads file "ABCD.CSV" in the PC card inserted to slot 0 as two-column table data in CSV format when X10 is turned ON. 1 • Assume that 8 points from (D0) are reserved for the control data devices. • Assume that 100 bytes from D20 are reserved for the reading devices. 2 • Assume that the target CSV format file contains numerical values only.
SP.DEVST 7.18.14 Writing Data to Standard ROM (SP.DEVST) SP.DEVST High performance Basic Process Redundant Universal Command SP.DEVST SP.
SP.DEVST (4) SM721 turns ON during execution of this instruction. When SM721 has already turned ON, this instruction can not be executed. (If executed, no processing is performed.) (5) When an error is detected at execution of this instruction, the completion device ( error completion device ( D +1) and SM721 do not turn ON. D +0), Operation Error 1 2 3 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
(S(P).DEVLD) 7.18.15 Read Data from Standard ROM (S(P).DEVLD) (S(P).DEVLD) Basic High performance Process Redundant Universal Command S.DEVLD S.DEVLD n1 D n2 SP.DEVLD n1 D n2 Command SP.
(S(P).DEVLD) Operation Error 1 (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The address specified at n1 is out of the standard ROM range. (Error code: 4100) • The number of n2 points from the address specified at n1 is out of the standard ROM range. (Error code: 4100) • The range for the number of n2 points from the device device.
PLOADP 7.18.16 Load Program from Memory Card (PLOADP) PLOADP High performance Basic Process Redundant Universal Command PLOADP PLOADP S S D : Drive No.
PLOADP (b) When there are multiple open program Nos., the program designated by the PLOADP instruction is added to the lowest number among them to be added. (The open program Nos. are made when programs are deleted by the PUNLOADP instruction.) When programs No. 2 and 4 are open, the new program is added as program No. 2. Program No. 1 2 3 4 5 Program name MAIN1 Empty MAIN3 Empty MAIN5 Adds "MAIN6" by the PLOADP instruction. Program No.
PLOADP (10) The "PLOADP instruction" and "Write during RUN" processing cannot be executed simultaneously. (a) When a write during RUN request is given during processing of the PLOADP instruction, write during RUN is delayed. Write during RUN is started after the processing of the PLOADP instruction is completed. (b) When the PLOADP instruction is executed during write during RUN, the processing of the PLOADP instruction is delayed.
PUNLOADP 7.18.
PUNLOADP (6) When the Programmable Controller is powered OFF, then ON or the CPU module is reset after execution of the PUNLOADP instruction, the following operation is performed. (a) When boot setting has been made in the PLC parameter dialog box, the program where the boot setting has been made is transferred to the program memory.
PSWAPP 7.18.18 Load + Unload (PSWAPP) 1 PSWAPP Basic High performance Process Redundant Universal 2 3 Command PSWAPP PSWAPP S1 S2 D 4 S1 : Character string data of the file name of the program to be unloaded, or head number of the devices storing the character string data (BIN 16 bits) S2 : Drive No.
PSWAPP (3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.) • Drive 1: Memory card (RAM) • Drive 2: Memory card (ROM) • Drive 4: Standard ROM (4) An extension (.QPG) need not be specified for the file name. (5) The bit device specified by D is turned ON during the END processing of the scan where this instruction is completed. The bit device is turned OFF at the next END processing. (6) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
PSWAPP Operation Error (1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. • The drive No. or the file name designated by S1 or S2 does not exist. (Error code: 2410) • The drive No. designated by S1 is invalid. (Error code: 4100) • There is not enough memory to load the specified program in drive 0. 1 2 3 (Error code: 2413) • The program designated by S1 is not in standby status or is being executed.
RBMOV(P) 7.18.
RBMOV(P) Example Transfer ranges of ZR and R overlap when transferring 10000 points of data from ZR30000 (source) to R10 (block No.1 of the destination). • ZR transfer range (30000) to (30000+10000-1) (30000) to (39999) 2 • R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1) (32778) to (42777) Therefore, the range 32778 to 39999 overlaps. Source of transfer ZR0 1 3 Destination of transfer R0 Overlapped 4 Block No. 0 ZR30000 R32767 R10 ZR39999 R10009 6 Block No.
RBMOV(P) Program Example (1) The following program outputs the lower four bits of data in R66 to R69 to Y30 through Y3F in units of 4 points.
RBMOV(P) The RBMOV (P) instruction is useful to batch transfer a large quantity of file register data with the QnHCPU/QnPHCPU/QnPRHCPU. For the QnUCPU, the processing speed of the RBMOV instruction is equivalent to that of the BMOV instruction.
RBMOV(P) (2)Transfer from file registers to file registers CPU QnHCPU Instruction RBMOV QnPHCPU QnPRHCPU BMOV RBMOV QnCPU BMOV RBMOV 1 word Target memory where file register is stored Min. 1000 words Max. Min. 10000 words Max. Min. Max. Standard RAM 20.0 µs 91.0 µs 775.0 µs SRAM card 22.5 µs 545.0 µs 5300.0 µs Standard RAM 7.5 µs 77.0 µs 720.0 µs SRAM card 8.5 µs 692.0 µs 7050.0 µs Standard RAM 45.5 µs 215.0 µs 1850.0 µs SRAM card 50.0 µs 870.0 µs 8350.
I INDEX I Index-1
[Symbols] - (BIN 16-bit subtraction operations).................... 6-22 $+ (Linking character strings) ...................... 6-65,6-67 $=, $<>, $>, $<=, $<, $>= (Character string data comparisons) ....................................................... 6-11 $MOV (Character string transfers) .................... 6-112 * (BIN 16-bit multiplication operations) ................ 6-30 + (BIN 16-bit addition operations)........................ 6-22 / (BIN 16-bit division operations) .........................
BCD 4-digit multiplication and division operations (B*, B/) ........................................................................ 6-42 BCD 4-digit square roots (BSQR)...................... 7-306 BCD 8-digit addition and subtraction operations (DB+, DB-) ..................................................................... 6-38 BCD 8-digit multiplication and division operations (DB*, DB/)............................................................ 6-44 BCD 8-digit square roots (BDSQR) ...................
CML (16-bit negation transfers) ......................... 6-114 COM (Refresh instruction) ............. 7-134,7-137,7-141 Common logarithm operation on floating-point data (Double precision) (LOG10D(P)) ....................... 7-302 Common logarithm operation on floating-point data (Single precision) (LOG10(P)) ........................... 7-300 Comparison operation instruction table ............... 2-10 Comparison operation instructions ........................ 6-2 Comparisons (BIN 16-bit data) ............
Conversion from hexadecimal BIN to ASCII (ASC) ........................................................................... 7-228 Conversion of Gray code to BIN 16-bit (GBIN).... 6-92 Conversion of Gray code to BIN 32-bit (DGBIN) ............................................................................. 6-92 Conversion to BIN BCD 4-digit to BIN 16-bit (BIN) ........................ 6-75 BCD 8-digit to BIN 32-bit (DBIN)......................
DI (Interrupt disable) .......................................... 6-133 Digit designation .................................................... 3-4 Digit designation of bit devices .............................. 3-4 DINC (Incrementing 32-bit BIN)........................... 6-71 DINT (Floating decimal point data to BIN 32-bit (Single precision)) ............................................................ 6-83 DINTD (Floating decimal point data to BIN 32-bit (Double precision)) ...............................
Expansion clock data subtraction operation (S.DATE-) ........................................................................... 7-366 EXPD (Exponent operation on floating-point data (Double precision)) ............................................ 7-294 Exponent operation on floating-point data (Double precision) (EXPD).............................................. 7-294 Exponent operation on floating-point data (Single precision) (EXP) ................................................
[J] JMP (Pointer branch)......................................... 6-129 Jump to END (GOEND)..................................... 6-132 [K] KEY (Numerical key input from keyboard)......... 7-396 [L] Ladder block parallel connections (ORB) ............ 5-10 Ladder block series connections (ANB) .............. 5-10 LD ($=, $<>, $>, $<=, $<, $>=) (Character string data comparisons) ....................................................... 6-11 LD (=, <>, >, <=, <, >=) (BIN 16-bit data comparisons) ...............
[O] Operation errors .................................................. 3-27 Operation results inversion (INV) ........................ 5-15 Operation results pop (MPP) ............................... 5-12 Operation results push (MPS) ............................. 5-12 Operation results read (MRD) ............................. 5-12 Operation start (LD, LDI) ....................................... 5-2 OR ($=, $<>, $>, $<=, $<, $>=) (Character string data comparisons) .........................................
RADD (Conversion from floating-point angle to radian (Double precision)) ............................................ 7-277 RAMP (Ramp signal) ......................................... 6-157 Ramp signal (RAMP) ......................................... 6-157 Random number generation (RND/SRND)........ 7-304 Random selection from and replacement in character strings (MIDR) ................................................... 7-235 Random selection replacement in character strings (MIDW) .......................
SIND (SIN operation on floating-point data (Double precision)).......................................................... 7-252 Single precision to Double precision conversion (ECON).............................................................. 6-102 SORT (BIN 16-bit data sort) ................................ 7-95 SP.CONTSW (System switching instruction) ...... 11-2 SP.DEVST (Writing data to standard ROM)...... 7-436 SP.FREAD (Reading data from designated file) ..............................................
S.TO................................................................... 9-4 TO ...................................................................... 9-7 WSUM (Calculation of totals for 16-bit data) ....... 7-99 WTOB (Data dissociation in byte units) ............... 7-85 WXNR (16-bit data exclusive NOR operation)..... 7-27 WXNR (16-bit data non-exclusive logical sum operations)........................................................... 7-30 WXOR (16-bit exclusive OR operations) .....
Warranty Please confirm the following product warranty details before using this product. 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or Mitsubishi Service Company.
Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other countries. Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries. Ethernet is a trademark of Xerox Co., Ltd. in the United States. CompactFlash is a trademark of SanDisk Corporation. VxWorks, Tornado, WindPower, WindSh and WindView are registered trademarks of Wind River Systems, Inc.
SAFETY PRECAUTIONS (Always read these cautions before using the product) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
REVISIONS *The manual number is given on the bottom left of the back cover. Print Date *Manual Number Revision Dec., 2008 SH (NA)-080809ENG-A First edition Mar., 2009 SH (NA)-080809ENG-B Partial corrections Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7, 7.12.11, 7.12.25, 7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8 Jul.
INTRODUCTION This manual explains the common instructions required for programming of the QCPU. • The common instructions refer to all instructions except those dedicated to special function modules (such as AJ71QC24 and AJ71PT32-S3) and to AD57 models, as well as PID control instructions, SFC instructions and ST instructions.
CONTENTS SAFETY PRECAUTIONS ..................................................................................................................A - 1 REVISIONS .......................................................................................................................................A - 2 INTRODUCTION ...............................................................................................................................A - 3 CONTENTS ..........................................................
2.5.11 2.5.12 2.5.13 2.5.14 2.5.15 2.5.16 2.5.17 2.5.18 2.5.19 2.5.20 2.5.21 2.5.22 Character string processing instructions .................................................................... 2 - 43 Special function instructions ....................................................................................... 2 - 46 Data control instructions ............................................................................................. 2 - 49 Switching instructions ...................................
5.2.3 5.2.4 5.2.5 5.3 Output Instructions 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.4 5.6 5.7 Comparison Operation Instructions 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 A-6 6 - 1 to 6 - 168 6-2 BIN 16-bit data comparisons (=,<>,>,<=,<,>=) ............................................................. 6 - 2 BIN 32-bit data comparisons (D=,D<>,D>,D<=,D<,D>=) .............................................
6.2.10 Addition and subtraction of floating decimal point data (Double precision) (ED+(P),ED-(P)) ................................................................................................. 6 - 50 6.2.11 Multiplication and division of floating decimal point data (Single precision) (E*(P),E/(P)) ....................................................................................................... 6 - 54 6.2.
6.6 Program Execution Control Instructions 6.6.1 6.6.2 6.7 6.8 Interrupt disable/enable instructions, interrupt program mask (DI,EI,IMASK) .......... 6 - 133 Recovery from interrupt programs (IRET) ................................................................ 6 - 139 I/O Refresh Instructions 6.7.1 Logical operation instructions 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.2 7.3 7.4 7.5 A-8 7 - 46 7 - 59 Bit set and reset for word devices (BSET(P),BRST(P)) ..............................
7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14 7.5.15 7.6 Structure creation instructions 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.6.10 7.6.11 7.6.12 7.6.13 7.7 7.8.2 7.9 7 - 160 Reading 1-/2-word data from the intelligent function module (FROM(P),DFRO(P))........................................................................................ 7 - 160 Writing 1-/2-word data to intelligent function module (TO(P),DTO(P)) .....................
7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data (BCDDA(P),DBCDDA(P))................................................................................. 7 - 189 7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data (DABIN(P),DDABIN(P)).................................................................................... 7 - 192 7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data (HABIN(P),DHABIN(P))..............................................................
7.12.25 Common logarithm operation on floating-point data (Single precision) (LOG10(P))....................................................................................................... 7 - 300 7.12.26 Common logarithm operation on floating-point data (Double precision) (LOG10D(P)) .................................................................................................... 7 - 302 7.12.27 Random number generation and series updates (RND(P),SRND(P)) ..................... 7 - 304 7.12.
7.18.5 7.18.6 7.18.7 7.18.8 7.18.9 7.18.10 7.18.11 7.18.12 7.18.13 7.18.14 7.18.15 7.18.16 7.18.17 7.18.18 7.18.19 File register direct 1-byte write (ZRWRB(P)) ............................................................ 7 - 393 Indirect address read operations (ADRSET(P)) ....................................................... 7 - 395 Numerical key input from keyboard (KEY) ............................................................... 7 - 396 Batch save or recovery of index register (ZPUSH(P),ZPOP(P)) .
12.1.4 12.1.5 12.1.6 12.1.7 12.1.8 12.1.9 Error code list (2000 to 2999) ................................................................................... 12 - 16 Error code list (3000 to 3999) ................................................................................... 12 - 34 Error code list (4000 to 4999) ................................................................................... 12 - 51 Error code list (5000 to 5999) .....................................................................
MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following list. The numbers in the "CPU module" and the respective modules are as follows.
Related Manuals Manual name Description < Manual number (model code) > CC-Link IE Controller Network Reference Manual Specifications, procedures and settings before system operation, parameter < SH-080668ENG (13JV16) > setting, programming, and troubleshooting of the CC-Link IE controller network module Q Corresponding MELSECNET/H Network System Reference Explains the specifications for a MELSECNET/H network system for PLC to PLC Manual (PLC to PLC network) network.
MEMO A-16
8 7 INSTRUCTIONS FOR DATA LINK 7 7 7 Category Processing Details Reference 7 section Network refresh instructions Refreshes the specified network module. Section 8.1 Routing information Reading the data specified by routing parameters. Section 8.2.1 read/write instructions Writing routing data to the area specified by routing parameters. Section 8.2.2 7 7 Remark In this chapter, instruction names are abbreviated as follows if not specified particularly. • S(P)/J(P)/G(P).ZCOM • S(P)/Z(P).
ZCOM 8.1 Network refresh instructions 8.1.1 Refresh instruction for the designated module (S(P)/J(P)/G(P).ZCOM) ZCOM Basic High performance Process Redundant Universal Command S.ZCOM S.ZCOM Jn SP.ZCOM Jn S.ZCOM Un SP.ZCOM Un Command SP.ZCOM Command S.ZCOM Command SP.ZCOM Jn : Network No.
ZCOM (2) The ZCOM instruction does not perform the following processing. 1 (a) Communication processing between CPU module and programming tool (b) Monitor processing of other station 2 (c) Read processing of buffer memory of other intelligent function module by serial communication module.
ZCOM (4) Remote I/O network The link refresh of the remote master station is performed by the "END processing" of the CPU module. Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the program of the CPU module. When the ZCOM instruction is used at the remote master station, link refresh is performed at the point of ZCOM instruction execution, and link scan is performed at completion of link refresh.
ZCOM (6) Designating "Un" in the argument enables the target designation of the intelligent function as well as the network modules. In this case, the auto refresh is performed for the buffer memory of the intelligent function modules. (It replaces the FROM/TO instructions.) (7) Only with the universal model QCPU, interruption of processing is enabled during the execution of the ZCOM instruction. However, when refresh data are used in an interrupted program, the data can split. 1.
RTREAD 8.2 Reading/Writing Routing Information 8.2.1 Reading routing information (S(P)/Z(P).RTREAD) RTREAD Basic High performance Process Redundant Universal Command S.RTREAD S.RTREAD n D SP.RTREAD n D Command SP.RTREAD Setting Data n : Transfer destination network No.
RTREAD Program Example 1 (1) The following program reads the routing information for the network number specified by D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 [Operation] D0 1 D1 10 3 D2 D3 Dummy 4 [Content of routing parameter setting] Transfer Relay network Relay station destination number network number number 1 10 3 2 3 10 10 6 2 1 6 7 8 8.2 Reading/Writing Routing Information 8.2.1 Reading routing information (S(P)/Z(P).
RTWRITE 8.2.2 Registering routing information (S(P)/Z(P).RTWRITE) RTWRITE Basic High performance Process Redundant Universal Command S.RTWRITE S.RTWRITE n S SP.RTWRITE n S Command SP.RTWRITE Setting Data n : Transfer destination network No.
RTWRITE Program Example 1 (1) The following program writes the routing information specified by D1 to D3 to the network module of the network number specified by D0 when X0 is turned ON. [Ladder Mode] [List Mode] Step Instruction 2 Device 3 4 [Operation] D0 1 D1 20 D2 1 D3 Dummy [Content of routing parameter setting] 6 Transfer Relay network Relay station destination number network number number 20 1 1 2 3 10 10 2 1 6 7 8 8.2 Reading/Writing Routing Information 8.2.
MEMO 8-10
9 MULTIPLE CPU DEDICATED INSTRUCTION 9 7 7 7 7 7 Category Processing Details Writing to the CPU shared Writes device data of the host CPU to the CPU shared memory of host CPU memory of the host CPU module. Reading from the CPU shared Reads device data from the CPU shared memory of another memory of another CPU CPU module to the host CPU. Reference 7 section Section 9.1 Section 9.
9.1 Writing to the CPU Shared Memory of Host CPU The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the multiple CPU system. The following table indicates the usability of the S.TO and TO instructions. CPU Module Type Name Basic model QCPU Q00CPU, Q01CPU S.
(2) Operation of the TO instruction The TO instruction can write device memory data to the following memories. 9 • CPU shared memory of host CPU module • Buffer memory of intelligent function module The following figure shows the processing performed when the TO instruction is executed in CPU No. 1. 7 7 CPU No. 1 Device memory Data write Intelligent function module CPU No.
S(P).TO 9.1.1 Write to Host CPU Shared Memory (S(P).TO) S(P).TO Ver. Basic Ver. High performance Process Redundant Universal Basic model QCPU:The first 5 digits of serial No is "04122" or higher. Hight performance modele QCPU:Function version B or later. Command S.TO S.TO n1 n2 n3 n4 D SP.TO n1 n2 n3 n4 D Command SP.
S(P).
S(P).TO Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. (1) When the specified data is outside the following range (Error code: 4101) • When the number of write points (n4) is outside the specified range of the setting data.
TO(P), DTO(P) 9.1.2 Writing to host station CPU shared memory (TO(P), DTO(P)) 9 Ver. Basic High performance Process Redundant Universal Q00CPU/Q01CPU whose first 5 digits of the serial No. is "04122" or higher 7 TO(P), DTO(P) 7 indicates an instruction symbol of TO/DTO.
TO(P), DTO(P) When a constant is specified to S , writes the same data (value specified to of n3 words from the specified CPU shared memory.
TO(P), DTO(P) DTO (1) Writes device data of words S to (n3×2) to the CPU shared memory address specified by n2 of the host CPU module or later address. 9 Host CPU CPU shared memory of host CPU (n1) Device memory 7 n2 S n3 2 7 Writes the data of (n3 2) words When a constant is specified to S , writes the same data (value specified to of (n3×2) words from the specified CPU shared memory.
TO(P), DTO(P) Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. (1) When the specified data is outside the following range (Error code: 4101) • When the number of write points (n3) is outside the specified range of the setting data.
9.2 Reading from the CPU Shared Memory of another CPU 9 The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following memories. 7 • Buffer memory of intelligent function module • CPU shared memory of other CPU module • CPU shared memory of host CPU module (applicable for the Basic model QCPU and Universal model QCPU) 7 The following figure shows the processing performed when the FROM(P) instruction is executed in CPU No. 1. 7 7 CPU No. 1 Intelligent function module CPU No.
FROM(P),DFRO(P) 9.2.1 Reading from Other CPU Shared Memory (FROM(P), DFRO(P)) FROM(P),DFRO(P) Ver. Ver. High performance Basic Process Redundant Universal Basic model QCPU:The first 5 digits of serial No is "04122" or higher. High performance model QCPU:Function version B or later. (1) When Basic model QCPU, Universal model QCPU is used indicates an instruction symbol of FROM/DFRO.
FROM(P),DFRO(P) (a) CPU shared memory address of the Basic model QCPU CPU shared memory address 9 0(0H) Host CPU operation information area 96(60H) System area 192(C0H) Host CPU refresh area *4 7 Read designation permitted area User free area 7 511(1FFH) (b) CPU shared memory address of the Universal model QCPU*5 7 CPU shared memory address 0(0H) 512(200H) Host CPU operation information area 7 System area 2048(800H) *4 Host CPU refresh area 7 User free area 4096(1000H) Unusable 10000(2710
FROM(P),DFRO(P) (2) When 0 is specified in n3 as the number of data to be read, no processing is performed. (3) The number of data to be read changes depending on the target CPU module. CPU Module Number of Read Points Basic model QCPU 1 to 256 Universal model QCPU 1 to 7168 Read of data from the CPU shared memory can also be performed using the intelligent function module devices.
FROM(P),DFRO(P) Program Example 9 (1) The following program stores 10 points of data from address C0H of the CPU shared memory of CPU No. 2 into the area starting from D0 when X0 is turned ON. [Ladder Mode] 7 [List Mode] Step Instruction Device 7 (2) The following program stores 20 points of data from address 10000 of the CPU shared memory of CPU No. 4 into the area starting from D0 when X0 is turned ON.
FROM(P),DFRO(P) (2) When High Performance model QCPU, Process CPU is used Command FROM FROM n1 n2 D n3 FROMP n1 n2 D n3 Command FROMP n1 : Head I/O number of the reading target CPU module (BIN 16 bits) n2 : Head address of data to be read (BIN 16 bits) D : Head number of the devices where the read data is stored (BIN 16 bits) n3 : Number of read data (BIN 16 bits) Setting Data Internal Devices Bit n1 –– n2 –– D –– n3 –– J R, ZR Word \ Bit U Word \G Zn Constants K, H Oth
FROM(P),DFRO(P) Read of data from the CPU shared memory can also be performed using the intelligent function module devices. For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals). 9 7 7 Operation Error In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
MEMO 9-18
10 7 QCPU INSTRUCTIONS 10 7 7 7 7 Category Processing Details Write instruction to another CPU Writes devices to another CPU. Read instruction from another CPU Reads devices from another CPU. Reference 7 section Section 10.2 Section 10.
10.1 Overview The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data to/from the Universal model QCPU in another CPU. The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed transmission dedicated instruction. CPU No.2 CPU No.1 User program DP.
(2) Writable/readable devices (a) Writable/readable device names The following table shows the devices that can be written to/read from the Univesal model QCPU in another CPU with the multiple CPU high-speed transmission dedicated instruction. Category Type Device name Setting of target Internal user device X, Y, M, L, B, F, SB Word device T, ST, C, D, W, SW 10 Remarks device Requirements for the setting Bit device 7 • Digits are specified by 16 bits (4 digits).
Writable/readable device range in device specification Host CPU Another CPU D0 D0 Data register (12k points) Data register (16k points) D12287 Writable/readable D12287 D12288 Not writable/not readable D16383 (b) String specification The string specification is a method to specify a device in another CPU to be written/ read by character string. Program for string specification with the DP.DDWR instruction X0 DP.
(4) Managing the multiple CPU high speed transmission area (a) The multiple CPU high speed transmission area is managed by blocks in units of 16 words. The following table shows the number of blocks that can be used in each CPU and the number of blocks used in the instruction. System area C Number of CPU modules 2k points 2 46 110 3 22 54 4 14 35 7 *1: For setting of the system area, refer to the QCPU User's Manual (Multiple CPU System).
(6) The multiple CPU high-speed transmission dedicated instructions that can be executed concurrently For the Universal model QCPU, the multiple CPU high-speed transmission dedicated instructions can be concurrently executed within the range satisfying the following formula.
(7) Interlock when using the multiple CPU high-speed transmission dedicated instruction (a) Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction setting) can be used as an interlock for the multiple CPU high-speed transmission dedicated instruction. When executing the multiple CPU high-speed transmission dedicated instructions concurrently, use SM796 to SM799 as an interlock for the instructions.
(b) Program example when SM796 to SM799 are used as an interlock The following shows a program that executes the D.DDWR instruction to CPU No.2 at the rise of X0, and executes the D.DDWR instruction to CPU No.3 at the rise of X1. The maximum number of used blocks for multiple CPU hight speed transmission dedicated SM402 0 MOV K7 SD797 Turn-on for one scan after RUN Maximum number of used blocks (CPU No.2) MOV K7 SD798 Maximum number of used blocks (CPU No.
(8) Program example when the multiple CPU high-speed transmission dedicated instructions are executed to CPU modules by turns When the multiple CPU high-speed transmission dedicated instructions are executed to Universal model QCPUs by turns, release an interlock to prevent the concurrent execution. Use the cyclic transmission area device (from U3En¥G10000) as an interlock. The following shows a program example when the multiple CPU high-speed transmission dedicated instructions are executed at CPU No.
Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.2 SM402 MOV K1 Turn-on for one scan after RUN SD796 Maximum number of used blocks (CPU No.1) X20 SET M0 During execution the DDRD instruction Read instruction U3E1¥G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction. M0 U3E0¥G10000.0 SM796 SET During execution of the DDWR instruction CPU No.1 is during execution of the instruction U3E1¥ G10000.0 CPU No.
(a) Program example when one D(P).DDWR instruction is executThe following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. In the following program example, the next D.DDWR instruction is executed after the completion device of the D.DDWR instruction (M2) turns on so that only one D.DDWR instruction may be executed. 7 10 Program example when one D(P).
(b) Program example when the D(P).DDWR instructions are executed concurrently The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in CPU No.2 with the D.DDWR instruction. As shown on the program example, multiple CPU device write/read instructions can be executed concurrently.
D(P).DDWR 10.2 Writing Devices to Another CPU (D(P).DDWR) 7 D(P).DDWR Ver. Basic High performance Process Redundant Universal 10 Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer QnUDE(H)CPU. 7 Command D.DDWR D.DDWR n S1 S2 D1 D2 DP.DDWR n S1 S2 D1 D2 7 Command DP.
D(P).DDWR Control Data Device Item Setting data Setting range Set by –– System 1 to 100 User An execution result upon completion of the S1 +0 Completion status instruction is stored. 0000(H): No errors (normal completion) Other than 0000(H): Error code (error completion) S1 +1 Number of write points Set the number of write points in units of words.
D(P).DDWR (3) The number of blocks used for the instruction depends on the number of write points (refer to Section 12.1). Number of blocks used for the instruction Number of write points D(P).DDWR specified by the instruction instruction 1 to 4 1 5 to 20 2 21 to 36 3 37 to 52 4 53 to 68 5 69 to 84 6 85 to 100 7 7 10 7 (4) The instruction will be completed abnormally when there are no empty blocks in the multiple CPU high speed transmission area.
D(P).DDWR In any of the following cases, the instruction is completed abnormally, and an error code is stored into a device specified at completion status storage device ( S1 +0). (1) The request of the instruction to the target CPU is more than the acceptable value (no empty blocks exist in the multiple CPU high speed transmission area). (Error code: 0010H) (2) A device for another CPU specified at range.
D(P).DDRD 10.3 Reading Devices from Another CPU (D(P).DDRD) 7 D(P).DDRD Ver. High performance Basic Process Redundant Universal 10 Q03UDCPU, Q04UDHCPU, Q06UDHCPU: that the first 5 digits of serial number is 10012 or higer QnUDE(H)CPU. Command D.DDRD D.DDRD n S1 S2 D1 D2 DP.DDRD n S1 S2 D1 D2 7 7 Command DP.
D(P).DDRD Control Data Device Item Setting data Setting range Set by –– System 1 to 100 User An execution result upon completion of the S1 Completion status +0 instruction is stored. 0000(H): No errors (normal completion) Other than 0000(H): Error code (error completion) S1 Number of read +1 Set the number of read points in units of words.
D(P).DDRD Operation Error 7 In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into SD0. (1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated instruction cannot be used in the setting (Error code: 4350). • The reserved CPU has been specified. 10 7 • Unmounted CPU has been specified. • The result of dividing the start I/O number of another CPU by 16n is outside the range of 3E0H to 3E3H.
D(P).DDRD Program Example (1) This program stores data by 10 words starting from DO in CPU No.2 into W10 or later in host CPU when XO turns on. [Ladder mode] X0 MOVP K10 D101 D0 W10 M100 Execution command of the instruction DP.DDRD M100 H3E1 D100 M101 Normal completion Program Completion device M101 Error completion Program Caution (1) Digit specification of bit device is possible for n, specification of bit device is made to S2 or D1 S2 , and D1 .
11 7 QCPU INSTRUCTIONS 7 11 7 7 7 Category Processing Details Reference Switches between the control system and standby system at System switching instruction the END processing of the scan executed with the 7 section Section 11.1 SP.CONTSW instruction.
SP.CONTSW 11.1 System Switching Instruction (SP.CONTSW) SP.CONTSW Basic High performance Process Redundant Universal Command SP.CONTSW Setting Data S D SP.CONTSW S D S : Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits) D : Error completion device number (bits) Internal Devices Bit R, ZR Word –– J Bit \ Word U \G Zn Constants K, H Other –– *1 –– –– –– –– *1: The bit specification for the word device is available.
SP.CONTSW (5) The error completion device is turned ON by the control system CPU module when system switching by the SP.CONTSW instruction was unsuccessful. (a) When OPERATION ERROR is detected due to any of the following reasons at the execution of the SP.CONTSW instruction, the error completion device is turned ON during the instruction execution. • 0 is specified at S 7 of the executed SP.CONTSW instruction. • The "manual switching enable flag (SM1592)" is OFF. • The SP.
SP.CONTSW (2) If system switching was unsuccessful, the error flag (SM0) is turned ON and an error code is stored into SD0. • The tracking cable is disconnected or faulty. (Error code: 6220) • Hardware fault, power-off, reset or watchdog timer error occurred in the standby system. (Error code: 6220) • Watchdog timer error occurred in the control system. (Error code: 6220) • Preparations are being made for tracking transfer. (Error code: 6220) • Communication time-out occurred.
12 6 ERROR CODES 6 6 12 6 6 6 6 12-1
12.1 Error Code List The CPU module uses the self diagnostics function to display error information (on the LED) and stores the information into the special relay SM and special register SD, when an error occurs in the following situations: • When the Progammable Controller is powered ON. • When the CPU module is switched from STOP to RUN. • While the CPU module is running.
12.1.1 Error codes 1 Errors are detected by the self diagnostic function of the CPU module or detected during communication with the CPU module. The relation between the error detection pattern, error detection location and error code is shown in Table 12.1. 3 Table12.1Reference destination Error detection pattern Error detection location Error code Reference 12 Detection by the self diagnostics function of CPU CPU module 1000 to 10000*1*2 Section 12.1.3 to 12.1.
12.1.3 Error code list (1000 to 1999) The following shows the error messages from the error code 1000 to 1999, the contents and causes of the errors, and the corrective actions for the errors.
Error Code 1006 1007 1008 1009 Error Contents and Cause [MAIN CPU DOWN] Runaway or failure of CPU module or failure of main CPU • Malfunctioning due to noise or other reason • Hardware fault ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • Always [MAIN CPU DOWN] • A failure is detected on the power supply module, CPU module, main base unit, extension base unit or extension cable.
Error Code Error Contents and Cause Corrective Action 1101 [RAM ERROR] The sequence program storing program memory in the CPU module is faulty. ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • At power ON/ At reset/ When an END instruction executed • Take noise reduction measures. • Reset the CPU module and RUN it again. If the same error is displayed again,this suggests a CPU module hardware fault.(Contact your local Mitsubishi representative.
Error Code 1106 Error Contents and Cause [RAM ERROR] The battery is dead. The program memory in the CPU module is faulty. ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • STOP RUN/When an END instruction executed 1107 1108 1109 1110 1111 1113 *7 *8 *9 LED Status CPU Status • Check the battery to see if it is dead or not. If dead, replace the battery. • Take noise reduction measures.
Error Code Error Contents and Cause Corrective Action 1115 [TRK. CIR. ERROR] A fault was detected by the initial check of the tracking hardware. ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • At power ON/ At reset 1116 [TRK. CIR. ERROR] A tracking hardware fault was detected during running. • The tracking cable was disconnected and reinserted without the standby system being powered off or reset.
Error Code 1164 1200 Error Contents and Cause [RAM ERROR] The destruction of the data stored in the standard RAM is detected. ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • When instruction executed LED Status CPU Status Corresponding CPU 1 • Take noise reduction measures. If the same error is displayed again, the CPU module has hardware failure. Contact your local Mitsubishi representative, explaining a detailed description of the problem.
Error Code [FUSE BREAK OFF] There is an output module with a blown fuse. ■Collateral information • Common Information:Module No.(Slot No.) [For Remote I/O network]Network No./ Station No. • Individual Information:– ■Diagnostic Timing • Always 1300 1310 1311 • Check FUSE. LED of the output modules and replace the module whose LED is lit. (The module with a blown fuse can also be identified using GX Developer.
Error Code 1401 1402 1403 *2 LED Status CPU Status Corrective Action [SP. UNIT DOWN] • There was no response from the intelligent function module/special function module in the initial processing. • The size of the buffer memory of the intelligent function module/special function module is invalid. • The unsupported module is mounted. ■Collateral information • Common Information:Module No.(Slot No.
Error Code Error Contents and Cause [CONTROL-BUS. ERR.] The FROM/TO instruction is not executable, due to a control bus error with the intelligent function module/special function module. (On error occurring, the program error location is stored in the individual information.) ■Collateral information • Common Information:Module No. (Slot No.) • Individual Information:Program error location ■Diagnostic Timing • During execution of FROM/TO instruction set 1412 [CONTROL-BUS. ERR.
Error Code Error Contents and Cause Corrective Action LED Status CPU Status [CONTROL-BUS. ERR.] Fault of the main or extension base unit was detected. ■Collateral information • Common Information:Module No. (Slot No.) • Individual Information:– ■Diagnostic Timing • When an END instruction executed 1415 1416 [CONTROL-BUS. ERR.] Fault of the main or extension base unit was detected. ■Collateral information • Common Information:Module No. (Slot No.
Error Code Error Contents and Cause Corrective Action 1431 [MULTI-C.BUS ERR.] The communication error with other CPU is detected in the Multiple CPU high speed bus. ■Collateral information • Common Information:Module No. (CPU No.) • Individual Information:– ■Diagnostic Timing • At power ON/ At reset • Take noise reduction measures. • Check the main base unit mounting status of the CPU module. • Reset the CPU module and RUN it again.
Error Code 1510 1520 1600 1601 *3 *6 *12 *14 [SINGLE PS. DOWN] The power supply voltage of either of redundant power supply modules on the redundant base unit dropped. ■Collateral information • Common Information:Base No./ Power supply No. • Individual Information:– ■Diagnostic Timing • Always Corrective Action Check the power supplied to the redundant power supply modules mounted on the redundant base unit. Hardware fault of the redundant power supply module.
12.1.4 Error code list (2000 to 2999) The following shows the error messages from the error code 2000 to 2999, the contents and causes of the errors, and the corrective actions for the errors. Error Code (SD0) 2000 Replace the CPU module incompatible with the multiple CPU system with a CPU module compatible with the multiple CPU system. [UNIT VERIFY ERR.] The I/O module status is different from the I/O module information at power ON.
Error Code (SD0) Error Contents and Cause Corrective Action LED Status CPU Status Corresponding CPU 1 [BASE LAY ERROR] The QA1S6 B, QA6 B, or QA6ADP+A5 B/A6 B was used as the base unit. 2011 ■Collateral information • Common Information:Base No. • Individual Information:– ■Diagnostic Timing • At power ON/At reset Q00J/Q00/Q01*3 QnPH QnPRH QnU Do not use the QA1S6 B, QA6 B, or QA6ADP+A5 B/A6 B as the base unit.
Error Code (SD0) 2100 *3 [SP. UNIT LAY ERR.] The slot to which the QI60 is mounted is set to other than Inteli (intelligent function module) or Interrupt (interrupt module) in the I/O assignment of PLC parameter. ■Collateral information • Common Information:Module No. (Slot No.) • Individual Information:– ■Diagnostic Timing • At power ON/At reset Make setting again to match the PLC parameter I/O assignment with the actual loading status. Qn(H)*3 QnPH QnPRH [SP. UNIT LAY ERR.
Error Code (SD0) 2102 Error Contents and Cause [SP. UNIT LAY ERR.] Seven or more A1SD51S have been installed. ■Collateral information • Common Information:Module No. (Slot No.) • Individual Information:– ■Diagnostic Timing • At power ON/At reset [SP. UNIT LAY ERR.] • Two or more QI60/A1SI61 modules are mounted in a single CPU system. • Two or more QI60/A1SI61 modules are set to the same control CPU in a multiple CPU system. • Two or more A1SI61 modules are loaded in a multiple CPU system.
Error Code (SD0) 2106 *6 *7 *9 Error Contents and Cause Corrective Action Corresponding CPU [SP.UNIT LAY ERR.] • Two or more MELSECNET/H modules are mounted. • Two or more CC-Link IE controller network modules are mounted. • Two or more Ethernet modules are mounted. ■Collateral information • Common Information:Module No. • Individual Information:– ■Diagnostic Timing • At power ON/At reset • Reduce the number of MELSECNET/H modules to one.
Error Code (SD0) 2106 Error Contents and Cause Corrective Action Corresponding CPU 1 [SP. UNIT LAY ERR.] • Five or more MELSECNET/H modules have been installed. • Five or more Ethernet interface modules have been installed. ■Collateral information • Common Information:Module No. (Slot No.) • Individual Information:– ■Diagnostic Timing • At power ON/At reset • Reduce the number of MELSECNET/H modules to four or less. • Reduce the number of Ethernet modules to four or less. [SP. UNIT LAY ERR.
Error Code (SD0) Error Contents and Cause Corrective Action [SP. UNIT ERROR] • The location designated by the FROM/TO instruction set is not the intelligent function module/special function module. • The module that does not include buffer memory has been specified by the FROM/TO instruction. • The intelligent function module/special function module, Network module being accessed is faulty. • Station not loaded was specified using the instruction whose target was the CPU share memory.
Error Code (SD0) 2114 Error Contents and Cause 2117 RUN [SP. UNIT ERROR] • An instruction that does not allow the under the control of another CPU to be specified is being used for a similar task. • Instruction was executed for the A or QnA module under control of another CPU. ■Collateral information • Common Information:Module No. (Slot No.
Error Code (SD0) Error Contents and Cause Corrective Action LED Status CPU Status Corresponding CPU [SP. UNIT LAY ERR.] The locations of the Q5 B/Q6 B, QA1S6 B/ QA6 B, and QA6ADP+A5 B/A6 B are improper. ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • At power ON/At reset 2120 [SP. UNIT LAY ERR.] The CPU module is installed to other than the CPU slot and slots 0 to 2.
Error Code (SD0) 2124 Error Contents and Cause Corrective Action [SP. UNIT LAY ERR.] • A module is mounted on the 37th slot or later slot. • A module is mounted on the slot whose number is greater than the number of slots specified at [Slots] in [Standard setting] of the base setting. • A module is mounted on the slot whose number of I/O points exceeds 2048 points. • A module is mounted on the slot whose number of I/O points strides 2048 points.
Error Code (SD0) LED Status CPU Status Corresponding CPU Error Contents and Cause Corrective Action 2126 [SP. UNIT LAY. ERR.] CPU module locations in a multiple CPU system are either of the following. • There are empty slots between the QCPU and QCPU/motion controller. • A module other than the High Performance model QCPU/Process CPU (including the motion controller) is mounted on the left-hand side of the High Performance model QCPU/Process CPU. ■Collateral information • Common Information:Module No.
Error Code (SD0) Error Contents and Cause [MISSING PARA.] There is no parameter file in the drive specified as valid parameter drive by the DIP switches. ■Collateral information • Common Information:Drive Name • Individual Information:– ■Diagnostic Timing • At power ON/At reset/ STOP 2200 Corresponding CPU 1 • Check and correct the valid parameter drive settings made by the DIP switches. • Set the parameter file to the drive specified as valid parameter drive by the DIP switches.
Error Code (SD0) Error Contents and Cause Corrective Action 2221 [RESTORE ERROR] • The device information backuped by the device data backup function is incomplete. (Turning power supply OFF or reset is suspected.) Do not return the data when this error occurs. Also, delete the incomplete device information at the time of this error occurrence.
Error Code (SD0) Error Contents and Cause [ICM. OPE. ERROR] • The memory card has not been formatted. • Memory card format status is incorrect. • The QCPU file does not exist in the Flash card. ■Collateral information • Common Information:Drive name • Individual Information:– ■Diagnostic Timing • When memory card is inserted or removed/When memory card is inserted 2301 2302 *1 *3 *11 LED Status CPU Status Corresponding CPU 1 Qn(H) QnPH QnPRH • Format memory card. • Reformat memory card.
Error Code (SD0) Error Contents and Cause [FILE SET ERROR] Program memory capacity was exceeded by performing boot operation or automatic write to standard ROM. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • At power ON/At reset/ At writing to progurammable controller [FILE SET ERROR] Program memory capacity was exceeded by performing boot operation.
Error Code (SD0) 2411 2412 2413 Read the individual information of the error using the peripheral device, check to be sure that the program corresponds to the numerical values there (program location), and correct. [FILE OPE. ERROR] The SFC program file is one that cannot be designated by the sequence program.
Error Code (SD0) Error Contents and Cause [CAN'T EXE. PRG.] There are multiple program files although "none" has been set at the PLC parameter program settings. ■Collateral information • Common Information:File name/ Drive name • Individual Information:– ■Diagnostic Timing • At power ON/At reset/ STOP 2501 • At power ON/At reset/ STOP • At power ON/At reset/ STOP • At power ON/At reset/ STOP 2504 RUN Check whether the program version The function version is B or later. 12-32 QCPU is .
Error Code (SD0) 2700 2710 Error Contents and Cause Corrective Action [REMOTE PASS.FAIL] The count of remote password mismatches reached the upper limit. ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • Always Check for illegal accesses. If any illegal access is identified, take actions such as disabling communication of the connection. If no illegal access is identified, clear the error and perform the following.
12.1.5 Error code list (3000 to 3999) The following shows the error messages from the error code 3000 to 3999, the contents and causes of the errors, and the corrective actions for the errors. Error Code (SD0) Error Contents and Cause Corrective Action [PARAMETER ERROR] In a multiple CPU system, the intelligent function module under control of another CPU is specified in the interrupt pointer setting of the PLC parameter.
Error Code (SD0) 3001 Error Contents and Cause [PARAMETER ERROR] The parameter settings are corrupted.
Error Code (SD0) Error Contents and Cause [PARAMETER ERROR] The automatic refresh range of the multiple CPU system exceeded the file register capacity. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • When an END instruction executed [PARAMETER ERROR] The number of devices set at the PLC parameter device settings exceeds the possible CPU module range.
Error Code (SD0) 3007 Error Contents and Cause [PARAMETER ERROR] The parameter file in the drive specified as valid parameter drive by the DIP switches is inapplicable for the CPU module.
Error Code (SD0) Error Contents and Cause [PARAMETER ERROR] Multiple CPU auto refresh setting is any of the followings in a multiple CPU system. • When a bit device is specified as a refresh device, a number other than a multiple of 16 is specified for the refresh-starting device. • The device specified is other than the one that may be specified. • The number of send points is an odd number.
Error Code (SD0) 3015 Error Contents and Cause [PARAMETER ERROR] In a multiple CPU system configuration, the CPU verified is different from the one set in the parameter setting. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number/CPU No.
Error Code (SD0) Error Contents and Cause [LINK PARA. ERROR] In a multiple CPU system, the CC-Link IE controller network module controlled by another CPU is specified as the head I/O number of the CC-Link IE controller network module. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • At power-ON/ At reset/ STOP • At power-ON/ At reset/ STOP RUN [LINK PARA.
Error Code (SD0) Error Contents and Cause [LINK PARA. ERROR] • Although the CC-Link IE controller network module is mounted, network parameter for the CC-Link IE controller network module is not set. • Although the CC-Link IE controller network and MELSECNET/H modules are mounted, network parameter for the MELSECNET/H module is not set.
Error Code (SD0) Error Contents and Cause [LINK PARA. ERROR] The link refresh range exceeded the file register capacity. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • When an END instruction executed [LINK PARA. ERROR] • When the station number of the MELSECNET/H module is 0, the PLC-to-PLC network parameter has been set.
Error Code (SD0) Error Contents and Cause [LINK PARA. ERROR] • The system A of the MELSECNET/H remote master station has been set to other than Station No. 0. • The system B of the MELSECNET/H remote master station has been set to Station No. 0.
Error Code (SD0) Error Contents and Cause Corrective Action LED Status CPU Status [LINK PARA. ERROR] A CC-Link IE controller network parameter error was detected. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • At power ON/At reset/STOP RUN [LINK PARA. ERROR] • The network module detected a network parameter error. • A MELSECNET/H network parameter error was detected.
Error Code (SD0) 3102 Error Contents and Cause [LINK PARA. ERROR] • LB/LW own station send range at LB/LW4000 or later was set. • LB/LW setting (2) was performed. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • At power ON/At reset/STOP 3103 RUN 3104 *1 *7 *10 Examine the network range assignments for the network parameter in the control station.
Error Code (SD0) Error Contents and Cause [LINK PARA. ERROR] In a multiple CPU system, the CC-Link module under control of another station is specified as the head I/O number of the CC-Link network parameter. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • At power ON/At reset/STOP • At power ON/At reset/STOP RUN [LINK PARA.
Error Code (SD0) Error Contents and Cause [LINK PARA. ERROR] The CC-Link link refresh range exceeded the file register capacity. ■Collateral information • Common Information:File name/ Drive name • Individual Information:Parameter number ■Diagnostic Timing • When an END instruction executed 3106 [LINK PARA. ERROR] The network refresh parameter for CC-Link is out of range.
Error Code (SD0) Error Contents and Cause [SFC PARA. ERROR] The number of step relays specified in the device setting of the PLC parameter dialog box is less than that used in the program. ■Collateral information • Common Information:File name • Individual Information:Parameter number ■Diagnostic Timing 3202 • STOP RUN [SFC PARA. ERROR] The execution type of the SFC program specified in the program setting of the PLC parameter dialog box is other than scan execution.
Error Code (SD0) 3302 Error Contents and Cause [SP. PARA ERROR] The intelligent function module's refresh parameter are abnormal. ■Collateral information • Common Information:File name • Individual Information:Parameter number*2 ■Diagnostic Timing • At power-On/ At reset/ STOP Corrective Action LED Status CPU Status Corresponding CPU 1 Check the parameter setting. QCPU RUN/ 3 At writing to progurammable controller 3303 [SP.
Error Code (SD0) Error Contents and Cause [REMOTE PASS. ERR.] Position specified as the head I/O number of the remote password file is incorrect due to one of the following reasons: • Module is not loaded.
12.1.6 Error code list (4000 to 4999) The following shows the error messages from the error code 4000 to 4999, the contents and causes of the errors, and the corrective actions for the errors. 1 2 Error Code (SD0) 4000 Error Contents and Cause Corrective Action LED Status CPU Status [INSTRCT. CODE ERR] • The program contains an instruction code that cannot be decoded. • An unusable instruction is included in the program.
Error Code (SD0) Error Contents and Cause Corrective Action LED Status CPU Status [MISSING END INS.] There is no END (FEND) instruction in the program. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing 4010 • At power ON/At reset/STOP QCPU RUN [CAN'T SET(P)] The total number of internal file pointers used by the program exceeds the number of internal file pointers set in the parameters.
Error Code (SD0) Error Contents and Cause [OPERATION ERROR] • The number of setting data dealt with the instruction exceeds the applicable range. • The storage data and constant of the device specified by the instruction exceeds the applicable range. • When writing to the host CPU shared memory, the write prohibited area is specified for the write destination address. • The range of storage data of the device specified by the instruction is duplicated.
Error Code (SD0) Error Contents and Cause Corrective Action LED Status CPU Status Corresponding CPU [OPERATION ERROR] In a multiple CPU system, the link direct device (J \ ) was specified for the network module under control of another station. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • When instruction executed • Delete from the program the link direct device which specifies the network module under control of another CPU.
Error Code (SD0) Error Contents and Cause 4109 [OPERATION ERROR] With high speed interrupt setting PR, PRC, UDCNT1, UDCNT2, PLSY or PWM instruction is executed. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • When instruction executed 4111 [OPERATION ERROR] An attempt was made to perform write/read to/from the CPU shared memory write/read disable area of the host station CPU module with the instruction.
Error Code (SD0) 4122 Error Contents and Cause Corrective Action [OPERATION ERROR] • The dedicated instruction was executed to the module mounted on the extension base unit in the redundant system. • The instruction for accessing the intelligent function module mounted on the extension base unit from the standby system at separate mode was executed.
Error Code (SD0) Error Contents and Cause Corrective Action 4201 Read the common information of the error using the peripheral device, check error step corresponding to its numerical value (program error location), and correct the problem. 4202 [FOR NEXT ERROR] More than 16 nesting levels are programmed. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • When instruction executed Keep nesting levels at 16 or under.
Error Code (SD0) Error Contents and Cause 4220 [CAN'T EXECUTE(I)] Though an interrupt input occurred, the corresponding interrupt pointer does not exist. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • When instruction executed 4221 [CAN'T EXECUTE(I)] An IRET instruction does not exist in the executed interrupt program.
Error Code (SD0) 4235 Error Contents and Cause Corrective Action LED Status CPU Status Corresponding CPU 1 [INST. FORMAT ERR.] The configuration of the check conditions for the CHK instruction is incorrect. Alternatively, a CHK instruction has been used in a low speed execution type program. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • When instruction executed Qn(H) QnPH 3 [MULTI-COM.
Error Code (SD0) Error Contents and Cause 4353 [MULTI-COM.ERROR] The device which cannot be used for the multiple CPU high-speed transmission dedicated instruction specified by the program is specified. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • When instruction executed 4354 [MULTI-COM.ERROR] The character string which cannot be handled by the multiple CPU high-speed transmission dedicated instruction is specified.
Error Code (SD0) 4421 Error Contents and Cause [CAN'T SET(S)] Total number of steps in all SFC programs exceed the maximum. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • STOP 4422 [CAN'T SET(S)] Step number designations overlap in SFC program.
Error Code (SD0) Error Contents and Cause LED Status CPU Status Corresponding CPU [SFCP. FORMAT ERR.] The numbers of BLOCK and BEND instructions in an SFC program are not equal. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing 4500 • STOP RUN [SFCP. FORMAT ERR.] The configuration of the STEP* to TRAN* to TSET to SEND instructions in the SFC program is incorrect.
Error Code (SD0) 4505 Error Contents and Cause [SFCP. FORMAT ERR.] The structure of the SFC program is illegal. • In the operation output of a step, the SET Sn/ BLmSn or RST Sn/BLmSn instruction was specified for the host step. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing • STOP 4506 RUN [SFCP. FORMAT ERR.] The structure of the SFC program is illegal. • In a reset step, the host step number was specified as the destination step.
Error Code (SD0) Error Contents and Cause [SFCP. EXE. ERROR] The active step information at presumptive start of the SFC program is incorrect. ■Collateral information • Common Information:Program error location • Individual Information:– ■Diagnostic Timing 4610 • STOP RUN [SFCP. EXE. ERROR] Key-switch was reset during RUN when presumptive start was designated for SFC program.
Error Code (SD0) 4631 4632 4633 Error Contents and Cause [STEP EXE. ERROR] • Startup was attempted at the step that does not exist in the SFC program. Or, the step that does not exist in the SFC program was specified for end. • Forced transition was executed based on the transition condition that does not exit in the SFC program. Or, the transition condition for forced transition that does not exit in the SFC program was canceled.
12.1.7 Error code list (5000 to 5999) The following shows the error messages from the error code 5000 to 5999, the contents and causes of the errors, and the corrective actions for the errors. Error Code (SD0) 5000 5001 12-66 LED Status CPU Status Corresponding CPU Error Contents and Cause Corrective Action [WDT ERROR] • The scan time of the initial execution type program exceeded the initial execution monitoring time specified in the PLC RAS setting of the PLC parameter.
Error Code (SD0) Error Contents and Cause [PRG. TIME OVER] The program scan time exceeded the constant scan setting time specified in the PLC RAS setting of the PLC parameter. ■Collateral information • Common Information:Time (value set) • Individual Information:Time (value actually measured) ■Diagnostic Timing • Always 5010 5011 [PRG. TIME OVER] The low speed program execution time specified in the PLC RAS setting of the PLC parameter exceeded the excess time of the constant scan.
12.1.8 Error code list (6000 to 6999) The following shows the error messages from the error code 6000 to 6999, the contents and causes of the errors, and the corrective actions for the errors. Error Code (SD0) Error Contents and Cause Corrective Action LED Status CPU Status Corresponding CPU [FILE DIFF.] In a redundant system, the control system and standby system do not have the same programs and parameters.
Error Code (SD0) 6010 Error Contents and Cause [OPE. MODE DIFF.] The operational status of the control system and standby system in the redundant system is not the same. (This can be detected from the standby system of the redundant system.) ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • Always 6020 [OPE. MODE DIFF.] At power ON/reset, the RUN/STOP switch settings of the control system and standby system are not the same in a redundant system.
Error Code (SD0) Error Contents and Cause Corrective Action 6036 [UNIT LAY. DIFF.] A difference in the remote I/O configuration of the MELSECNET/H multiplexed remote I/O network between the control system and standby system of a redundant system was detected. (This can be detected from the control system or standby system of the redundant system.) ■Collateral information • Common Information:Module No.
Error Code (SD0) 6061 Error Contents and Cause [CPU MODE DIFF.] In a redundant system, the operation mode (backup/separate) differs between the control system and standby system. (This can be detected from the standby system of the redundant system.) ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • When an END instruction executed 6062 [CPU MODE DIFF.] Both System A and B are in the same system status (control system).
Error Code (SD0) Error Contents and Cause 6102 [TRK. TRANS. ERR.] A data sum value error occurred in tracking (data reception). (This can be detected from the control system or standby system of the redundant system.) ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • Always 6103 [TRK. TRANS. ERR.] • A data error (other than sum value error) occurred in tracking (data reception).
Error Code (SD0) Error Contents and Cause 6107 [TRK. TRANS. ERR.] A data sum value error occurred in tracking (data reception). (This can be detected from the control system or standby system of the redundant system.) ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • Always 6108 [TRK. TRANS. ERR.] • A data error (other than sum value error) occurred in tracking (data reception).
Error Code (SD0) 6120 6130 6140 6200 12-74 Error Contents and Cause Corrective Action [TRK. CABLE ERR.] • A start was made without the tracking cable being connected. • A start was made with the tracking cable faulty. • As the tracking hardware on the CPU module side was faulty, communication with the other system could not be made via the tracking cable. (This can be detected from the control system or standby system of the redundant system.
Error Code (SD0) 6210 6220 [STANDBY] The control system has been switched to the standby system in a redundant system. (Detected by the CPU that was switched from the control system to the standby system) Since this error code does not indicate the error information of the CPU module but indicates its status, the error code and error information are not stored into SD0 to 26, but are stored into the error log every system switching.
Error Code (SD0) 6310 6311 6312 6313 6400 12-76 Error Contents and Cause Corrective Action LED Status CPU Status [CONTROL SYS. DOWN] Any of the following errors was detected in the backup mode. • The control system has not started up in the redundant system. • The control system has developed a stop error in the redundant system. • The CPU module in the debug mode was connected to the operating standby system.
Error Code (SD0) 6410 6500 6501 Error Contents and Cause [MEM.COPY EXE] The memory copy from control system to standby system was executed. (This can be detected from the control system of the redundant system.) ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • At execution of the function of copying memory from control system to standby system Corrective Action LED Status CPU Status Corresponding CPU 1 – RUN: On ERR.: On 2 CPU Status: Continue [TRK.
12.1.9 Error code list (7000 to 10000) The following shows the error messages from the error code 7000 to 10000, the contents and causes of the errors, and the corrective actions for the errors. Error Code (SD0) 7000 Error Contents and Cause Corrective Action [MULTI CPU DOWN] • In the operating mode of a multiple CPU system, a CPU error occurred at the CPU where "All station stop by stop error of CPU " was selected.
Error Code (SD0) 7004 Error Contents and Cause Corrective Action [MULTI CPU DOWN] In a multiple CPU system, a data error occurred in communication between the CPU modules. ■Collateral information • Common Information:Module No.(CPU No.) • Individual Information:– ■Diagnostic Timing • Always • Check the system configuration to see if modules are mounted in excess of the number of I/O points. • When there are no problems in the system configuration, this indicates the CPU module hardware is faulty.
Error Code (SD0) Error Contents and Cause [MULTI EXE. ERROR] Either of the following settings was made in a multiple CPU system. • Multiple CPU automatic refresh setting was made for the inapplicable CPU module. • "I/O sharing when using multiple CPUs" setting was made for the inapplicable CPU module. ■Collateral information • Common Information:Module No.(CPU No.) • Individual Information:– ■Diagnostic Timing • At power ON/At reset • Correct the multiple CPU automatic refresh setting.
Error Code (SD0) Error Contents and Cause 7031 [CPU LAY. ERROR] An assignment error occurred within the range of the number of CPUs specified in the multiple CPU setting of the PLC parameter dialog box. ■Collateral information • Common Information:Module No.(CPU No.) • Individual Information:– ■Diagnostic Timing • At power ON/At reset 7032 [CPU LAY. ERROR] • The number of CPU modules mounted in a multiple CPU system is wrong. ■Collateral information • Common Information:Module No.(CPU No.
Error Code (SD0) [ERR ***-***] Error detected by the CHK instruction. ■Collateral information • Common Information:Program error location • Individual Information:Failure No. ■Diagnostic Timing • When instruction executed 9010 [BOOT OK] Storage of data onto ROM was completed normally in automatic write to standard ROM. (BOOT LED also flickers.) ■Collateral information • Common Information:– • Individual Information:– ■Diagnostic Timing • At power ON/At reset 9020 [CONT.
12.2 Canceling of Errors 1 Q series CPU module can perform the cancel operation for errors only when the errors allow the CPU module to continue its operation. To cancel the errors, follow the steps shown below. 1) Eliminate the cause of the error. 2) Store the error code to be canceled in the special register SD50. 3) Energize the special relay SM50 (OFF ON). 4) The error to be canceled is canceled.
MEMO 12-84
A 8 APPENDICES 8 8 8 A 8 8 8 App-1
Appendix 1 OPERATION PROCESSING TIME Appendix 1.1 Definition (1) Processing time taken by the QCPU is the total of the following processing times. • Total of each instruction processing time • END processing time (including I/O refresh time) • Processing time for the function that increases the scan time (2) Instruction processing time This is the total of processing time of each instruction shown in Appendix 1.2, 1.3 and 1.4.
Appendix 1.2 Operation Processing Time of Basic Model QCPU 8 The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate.
Instruction Y D0.0 OUT Processing Time (µs) Condition (Device) When not (OFF OFF) changed (ON ON) When (OFF ON) changed (ON OFF) When not (OFF OFF) changed (ON ON) When (OFF ON) changed (ON OFF) When OFF F App-4 20 19 0.55 1.1 0.88 0.55 When K When added D After time up When When added When When added When When not changed (ON executed When changed (OFF When changed (OFF 0.96 0.60 0.88 0.55 1.1 0.88 0.55 1.1 0.88 0.55 D 1.2 0.96 0.60 1.1 0.
Instruction Condition (Device) Processing Time (µs) Q00JCPU Q00CPU Q01CPU PLS 12 9.5 9.2 PLF 11 9.5 8.9 When not executed 0.68 0.40 0.25 When executed 7.5 6.2 5.7 When not executed 0.50 0.40 0.25 When executed 26 21 21 When not executed 0.48 0.40 0.25 Y FF DY0 DELTA DY0 DELTAP SFT SFTP When executed 58 45 43 When not executed 0.50 0.34 0.25 When executed 12 8.7 8.3 0.20 M0 0.40 0.32 D0.0 3.3 2.9 2.8 –– 0.20 0.16 0.
Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU 0.70 0.56 0.35 In conductive status 0.80 0.64 0.40 In non-conductive status 0.80 0.64 0.40 When not executed OR < > LD > When executed In conductive status 0.80 0.64 0.40 In non-conductive status 0.80 0.64 0.40 0.70 0.56 0.35 0.80 0.64 0.40 When not executed AND > When executed In conductive status In non-conductive status 0.80 0.64 0.40 0.70 0.56 0.35 In conductive status 0.80 0.64 0.
Instruction Condition (Device) When not executed ORD < > ANDD > 0.80 0.50 0.80 0.50 In conductive status 1.0 0.80 0.50 In non-conductive status 1.0 0.80 0.50 When not executed 0.80 0.64 0.40 1.0 0.80 0.50 In conductive status In non-conductive status 1.0 0.80 0.50 0.80 0.64 0.40 In conductive status 1.0 0.80 0.50 In non-conductive status 1.0 0.80 0.50 In conductive status 1.0 0.80 0.50 In non-conductive status 1.0 0.80 0.50 When not executed When executed 0.
Instruction BKCMP< S1 S2 Condition (Device) n D Processing Time (µs) Q00JCPU Q00CPU Q01CPU n=1 130 105 98 BKCMP
Instruction B* S1 S2 DB/ S1 S2 BK + P S1 S2 BK - S1 S2 BK - P S1 S2 DDEC DDECP BCD BCDP DBCDP BIN BINP DBIN DBINP DBL DBLP WORD WORDP GRY GRYP DGRY DGRYP GBIN GBINP DGBIN DGBINP NEG NEGP DNEG DNEGP 48 40 37 –– 140 120 110 –– 83 69 65 n=1 105 86 80 n = 96 185 155 140 n=1 105 86 80 n = 96 185 155 140 –– 0.70 0.56 0.35 –– 0.90 0.72 0.45 –– 0.70 0.56 0.35 –– 0.90 0.72 0.
Instruction BKBCD S BKBIN S n D BKBCDP S n D n D BKBINP S Condition (Device) D n MOV S MOVP S DMOV DMOVP S Q00JCPU Q00CPU Q01CPU n=1 78 63 57 n = 96 315 275 250 n=1 74 61 57 n = 96 285 255 230 = D1 0.70 0.56 0.35 = J1 \ W1 155 130 120 = D1 0.90 0.72 0.45 = J1 \ W1 165 135 120 = D0, = D0, S Processing Time (µs) D = D0, = D0, D D D $MOV 0 characters 46 38 35 $MOVP 32 characters 98 80 73 –– 0.70 0.56 0.35 –– 0.90 0.72 0.
(3) Application instructions The processing time when the instruction is not executed is calculated as follows: Q00JCPU ··················································· 0.20 (No. of steps for each instruction + 1) µs Q00CPU ····················································· 0.16 (No. of steps for each instruction + 1) µs Q01CPU ····················································· 0.10 (No.
Instruction Condition (Device) Processing Time (µs) Q00JCPU Q00CPU Q01CPU When executed 1.0 0.80 0.50 When executed 1.2 0.96 0.60 When executed 1.3 1.04 0.65 When executed 1.5 1.2 0.75 n=1 110 87 82 n = 96 185 155 140 ROR D n n=1 13 11 9.7 RORP D n n = 15 13 11 9.
Instruction Condition (Device) Processing Time (µs) Q00JCPU Q00CPU Q01CPU n=1 27 22 20 BSETP D n n = 15 27 22 20 BRST D n n=1 27 22 21 BRSTP D n n = 15 27 22 21 –– 35 30 27 –– 37 31 28 BKRST D n n=1 49 41 38 BKRSTP n = 96 64 54 50 56 54 42 BSET n D TEST S1 S2 D TESTP S1 S2 D DTEST S1 S2 D DTESTP S1 S2 SER S1 S2 DSER n D S1 S2 D 56 54 42 All match 280 240 220 None match 280 240 220 All match 71 67 53 None match 71 67 54 All matc
Instruction Condition (Device) n WTOB S D WTOBP S BTOW S n D BTOWP S D MAX S n D MAXP S MIN S n D n D DMAX S n D DMAXP S DMIN S n n D MINP S n D n D n D DMINP S n D SORT S1 n S2 D1 D2 DSORT S1 n S2 D1 D2 WSUM S n D Processing Time (µs) Q00JCPU Q00CPU Q01CPU n=1 56 46 42 n = 96 190 155 145 n=1 56 46 42 n = 96 190 155 145 n=1 48 40 36 n = 96 300 240 235 n=1 48 40 36 n = 96 300 240 235 n=1 52 43 39 n = 96 600 490 460 n=1 52 43
Instruction Condition (Device) Processing Time (µs) Q00JCPU Q00CPU Q01CPU COM –– 110 77 72 IX –– 65 54 51 IXEND –– 30 26 25 Number of contacts 1 145 120 110 Number of contacts 14 770 630 585 FIFW Number of data points 0 36 32 28 FIFWP Number of data points 96 36 32 28 FIFR Number of data points 1 45 41 36 FIFRP Number of data points 96 93 82 70 FPOP Number of data points 1 40 37 32 FPOPP Number of data points 96 40 37 32 IXDEV + IXSET FINS Number o
Instruction LIMIT LIMITP DLIMIT DLIMITP BAND BANDP DBAND DBANDP ZONE ZONEP DZONE DZONEP RSET RSETP DATERD DATERDP DATEWR DATEWRP DATE+ DATE+P DATE DATE - P SECOND SECONDP HOUR HOURP WDT WDTP DUTY ZRRDB ZRRDBP ZRWRB ZRWRBP ADRSET ADRSETP ZPUSH ZPUSHP ZPOP ZPOPP ZCOM Condition (Device) Processing Time (µs) Q00JCPU Q00CPU Q01CPU –– 34 28 26 –– 41 34 30 –– 33 28 25 –– 40 34 30 –– 31 25 24 –– 37 29 28 –– –– 18 16 –– 30 25 23 –– 69 57 54 No digit increase 47 39 36 Digi
(5) Instructions executable by the product with the first 5 digits of the serial No. "04122" or higher Instruction Processing Time (µs) Condition (Device) LDE = Single precision ANDE = Single precision Q00JCPU Q00CPU Q01CPU In conductive status 43.0 35.5 33.0 In non-conductive status 46.0 38.0 35.5 When not executed 1.5 1.2 1.0 In conductive status 35.5 29.5 26.5 In non-conductive status 42.0 35.0 32.5 1.5 1.2 1.0 In conductive status 42.0 35.0 32.
Instruction Condition (Device) Q00JCPU Q00CPU Q01CPU 1.5 1.2 1.0 In conductive status 45.0 38.5 34.5 In non-conductive status 37.5 31.0 28.
Instruction SIN SINP COS COSP TAN TANP RAD RADP DEG DEGP SQR SQRP EXP EXPP LOG LOGP Q00JCPU Q00CPU Q01CPU Single precision 204.0 173.0 157.0 Single precision 187.0 158.0 144.0 Single precision 224.0 190.0 173.0 Single precision 51.0 43.0 39.0 Single precision 51.0 43.0 39.0 Single precision 60.0 51.0 46.5 = - 10 306.0 259.0 235.0 S =1 306.0 259.0 235.0 S =1 73.0 61.5 56.0 = 10 301.0 255.0 232.0 –– 12.5 11.0 10.0 –– 13.5 12.0 11.
Instruction Condition/Number of Points Processed Name COM *2 –– 920 880 –– –– 150 135 n3 = 1 –– 100 90 (0.5k words assigned equally to all CPUs) memory of host CPU n3 = 320 –– 440 420 Read from CPU shared n3 = 1 –– 110 105 memory of another CPU n3 = 320 –– 305 290 n3 = 1 –– 100 95 n3 = 320 –– 440 425 n4 = 1 –– 205 195 n4 = 320 –– 545 525 Write to CPU shared memory of host CPU Write to CPU shared memory S.
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant CPU 8 The processing time for the individual instructions are shown in the table on the following pages. Operation processing time can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing times rather than as being strictly accurate.
Instruction Processing Time (µs) Condition (Device) When not changed When changed (OFF OFF) (ON ON) (OFF ON) (ON OFF) When OFF F When When added When added DELTA DELTAP When App-22 When executed When added When not changed (ON When changed (OFF ON) ON) When displayed Display completed When not changed (OFF When changed (ON 0.27 0.27 0.27 0.27 0.27 K 0.63 0.27 0.27 0.27 D 0.63 0.27 0.27 0.27 0.63 0.27 0.27 0.27 0.63 0.27 0.27 0.27 K 0.63 0.27 0.27 0.
Instruction SFT SFTP Condition (Device) Processing Time (µs) Qn QnH QnPH QnPRH When not executed 0.47 0.20 0.20 0.20 When executed 1.66 0.71 0.71 0.71 MC –– 0.24 0.10 0.10 0.10 MCR –– 0.079 0.034 0.034 0.034 Error check performed 380 150 150 500 380 150 150 500 –– 0.079 0.034 0.034 0.034 –– 0.079 0.034 0.034 0.
(2) Basic instructions The processing time when the instruction is not executed is calculated as follows: Q02CPU ·····················································0.079 (No. of steps for each instruction + 1) µs Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU 0.034 (No. of steps for each instruction + 1) µs Instruction LD = AND = Condition (Device) In conductive status LD < > AND < > LD > AND > LD < = AND < = App-24 QnPH QnPRH 0.10 0.10 0.
Instruction Condition (Device) Qn QnH QnPH QnPRH 0.24 0.10 0.10 0.10 In conductive status 0.24 0.10 0.10 0.10 In non-conductive status 0.24 0.10 0.10 0.10 0.24 0.10 0.10 0.10 When not executed OR < = LD < AND < When executed In conductive status In non-conductive status 0.24 0.10 0.10 0.10 When not executed 0.24 0.10 0.10 0.10 0.24 0.10 0.10 0.
Instruction Condition (Device) In conductive status LDD < ANDD < 0.24 0.24 0.24 0.17 0.17 In conductive status 0.55 0.24 0.24 0.24 In non-conductive status 0.55 0.24 0.24 0.24 0.39 0.17 0.17 0.17 0.55 0.24 0.24 0.24 0.55 0.24 0.24 0.24 0.55 0.24 0.24 0.24 In conductive status In non-conductive status In non-conductive status 0.55 0.24 0.24 0.24 When not executed 0.39 0.17 0.17 0.17 In conductive status 0.55 0.24 0.24 0.24 In non-conductive status 0.55 0.
Instruction Condition (Device) Single precision In conductive status In non-conductive status LDE<> *1 Double precision In conductive status In non-conductive status When not executed Single precision ANDE<> *1 When executed In conductive status In non-conductive status When not executed Double precision When executed In conductive status In non-conductive status When not executed Single precision ORE<> *1 When executed In conductive status In non-conductive status When not executed Double p
Instruction Condition (Device) When not executed Single precision ORE> *1 When executed In conductive status In non-conductive status When not executed Double precision Single precision When executed In conductive status In non-conductive status In conductive status In non-conductive status LDE<= *1 Double precision In conductive status In non-conductive status When not executed Single precision ANDE<= *1 When executed In conductive status In non-conductive status When not executed Double pr
Instruction Condition (Device) When not executed Single precision ANDE< *1 When executed In conductive status In non-conductive status When not executed Double precision When executed In conductive status In non-conductive status When not executed Single precision ORE< *1 executed In non-conductive status When not executed Double precision Single precision LDE>= When In conductive status When executed In conductive status In non-conductive status In conductive status In non-conductive statu
Instruction Condition (Device) When not executed Single precision When executed ORE>= *1 In non-conductive status When not executed Double precision When executed In conductive status In non-conductive status In conductive status LD$ = AND$ = In conductive status AND$ < > App-30 0.24 6.4 6.4 6.4 6.4 –– –– –– –– –– –– 16 16 92 40 14.9 6.4 92 40 14.9 6.4 0.55 0.24 92 40 14.9 6.4 92 40 14.9 6.4 38 16 15 15 15 0.23 0.23 0.
Instruction Condition (Device) When not executed AND$ > When executed When executed AND$ < = 14 14 14 17 17 17 0.56 0.24 0.24 0.24 32 14 14 14 In conductive status In non-conductive status 14 0.23 In conductive status 39 17 17 17 In non-conductive status 32 14 14 14 0.56 0.24 0.24 0.24 40 17 17 17 In conductive status 33 14 14 14 In conductive status In non-conductive status 32 14 14 14 In non-conductive status 40 17 17 17 When not executed 0.56 0.
Instruction + S D +P S D +P S1 S2 S -P D S D+ S D QnPRH When executed 0.39 0.17 0.17 0.17 When executed 0.47 0.20 0.20 0.20 When executed 0.39 0.17 0.17 0.17 When executed 0.47 0.20 0.20 0.20 When executed 0.71 0.31 0.31 0.31 When executed 0.79 0.34 0.34 0.34 When executed 0.71 0.30 0.30 0.30 When executed 0.79 0.34 0.34 0.34 When executed 0.47 0.20 0.20 0.20 –– 2.7 1.2 1.2 1.2 –– 7.9 3.4 3.4 3.4 –– 14 6.1 6.1 6.1 –– 2.2 1.0 1.0 1.
Instruction B/ S1 S2 Qn QnH QnPH QnPRH –– 3.8 1.6 1.6 1.6 –– 24 10 10 10 –– 27 12 12 12 1.8 0.78 0.78 0.78 1.8 0.78 0.78 0.78 D B/P S1 S2 D DB * S1 S2 DB/ S1 S2 D D DB/P S1 S2 S precision D S D Double precision S precision D E+P S1 S2 D Double precision Single E- S precision D E -P S D Double S precision D E -P S1 S2 D S1 precision D E*P S1 S2 D S1 S1 E/P S1 S2 precision D D S1 –– = 2127, D = 2127 203 87 –– –– = 0, S2 =0 2.4 1.
Instruction $+ S Condition (Device) Qn QnH QnPH QnPRH –– 68 29 29 29 –– 81 35 35 35 –– 0.32 0.14 0.14 0.14 –– 0.47 0.20 0.20 0.20 –– 0.32 0.14 0.14 0.14 –– 0.47 0.20 0.20 0.20 –– 1.1 0.48 0.48 0.48 –– 3.2 1.4 1.4 1.4 –– 1.0 0.44 0.44 0.44 –– 1.9 0.82 0.82 0.82 D $+P S D $+ S1 S2 $+P S1 S2 D D INC INCP DINC DINCP DEC DECP DDEC DDECP BCD BCDP DBCD DBCDP BIN BINP DBIN DBINP Single INT INTP S =0 3.2 1.4 1.4 1.4 S = 32766.5 3.2 1.4 1.4 1.
Instruction Condition (Device) Processing Time (µs) QnH QnPH QnPRH –– 4.5 1.9 1.9 1.9 –– 4.7 2.0 2.0 2.0 –– 4.7 2.0 2.0 2.0 –– 5.3 2.3 2.3 2.3 –– 18 7.7 7.7 7.7 –– 32 14 14 14 –– 3.6 1.6 1.6 1.6 –– 4.3 1.8 1.8 1.8 –– 3.9 1.7 1.7 1.7 n=1 38 17 17 17 n = 96 99 43 43 43 n=1 38 17 17 17 n = 96 99 43 43 43 0.24 0.10 0.10 0.10 MOV –– –– –– –– MOVP –– –– –– –– 140*1 60*1 60*1 60*1 0.47 0.20 0.20 0.
Instruction Condition (Device) Processing Time (µs) Qn QnH QnPH QnPRH n=1 17 7.1 7.1 7.1 n = 96 32 14 14 14 n=1 6.7 2.9 2.9 2.9 n = 96 14 6.1 6.1 6.1 –– 1.3 0.54 0.54 0.54 BXCH D1 D2 n n=1 31 13 13 13 BXCHP D1 D2 n n = 96 84 36 36 36 –– 3.7 1.6 1.6 1.6 CJ –– 3.2 1.4 1.4 1.4 SCJ –– 3.2 1.4 1.4 1.4 JMP –– 3.2 1.4 1.4 1.4 GOEND –– 0.39 0.34 0.34 0.34 DI –– 0.95 0.41 0.41 0.41 EI –– 1.3 0.54 0.54 0.54 IMASK –– 11 4.6 4.6 4.
(3) Application instructions The processing time when the instruction is not executed is calculated as follows: Q02CPU ·······················································0.079 (No. of steps for each instruction + 1) µs Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU ·0.034 (No. of steps for each instruction + 1) µs Instruction WAND S Condition (Device) D WANDP S When executed Processing Time ( µs) Qn QnH QnPH QnPRH 0.39 0.17 0.17 0.
Instruction Condition (Device) Processing Time (µs) Qn QnH QnPH QnPRH When executed 0.40 0.17 0.17 0.17 When executed 0.47 0.20 0.20 0.20 When executed 0.71 0.31 0.31 0.31 When executed 0.79 0.34 0.34 0.34 n=1 36 16 16 16 n = 96 74 32 32 32 ROR D n n=1 2.0 0.85 0.85 0.85 RORP D n n = 15 2.0 0.85 0.85 0.85 RCR D n n=1 1.6 0.68 0.68 0.68 RCRP D n n = 15 1.6 0.68 0.68 0.68 ROL D n n=1 2.0 0.85 0.85 0.85 ROLP D n n = 15 2.0 0.85 0.85 0.
Instruction Condition (Device) Processing Time (µs) Qn QnH QnPH QnPRH n=1 7.6 3.3 3.3 3.3 BSETP D n n = 15 7.6 3.3 3.3 3.3 BRST D n n=1 7.6 3.3 3.3 3.3 BRSTP D n n = 15 7.6 3.3 3.3 3.3 –– 8.2 3.5 3.5 3.5 –– 9.2 3.9 3.9 3.9 BKRST S n n=1 18 7.8 7.8 7.8 BKRSTP S n n = 96 19 8.2 8.2 8.2 BSET n D TEST S1 S2 D TESTP S1 S2 D DTEST S1 S2 D DTESTP S1 S2 SER S1 S2 DSERP n 22 9.6 9.6 9.6 21 8.9 8.9 8.
Instruction Condition (Device) n MAX S D MAXP S MIN S n D n D MINP S n D DMAX S DMAXP S DMIN S n D n D n D DMINP S n D SORT S1 n S2 D1 D2 DSORT S1 n S2 D1 D2 WSUM S n D Processing Time (µs) Qn QnH QnPH QnPRH n=1 17 7.1 7.1 7.1 n = 96 136 59 59 59 n=1 17 7.1 7.1 7.1 n = 96 159 69 69 69 n=1 27 12 12 12 n = 96 181 78 78 78 n=1 27 12 12 12 n = 96 112 48 48 48 n=1 16 7.1 7.1 7.1 n = 96 14 6.2 6.2 6.2 n=1 17 7.1 7.1 7.
Instruction Condition (Device) Qn QnH QnPH QnPRH 55 16 16 16 –– 12 5.2 5.2 5.2 –– 4.7 2.0 2.0 2.0 Number of contacts 1 48 21 21 21 COM –– IX IXEND IXDEV + IXSET Processing Time (µs) 93 40 40 40 Number of data points 0 11 4.5 4.5 4.5 FIFWP Number of data points 96 11 4.5 4.5 4.5 FIFR Number of data points 1 13 5.6 5.6 5.6 FIFRP Number of data points 96 32 14 14 14 FPOP Number of data points 1 16 7.0 7.0 7.0 FPOPP Number of data points 96 16 7.
Instruction LEDC LEDR Qn QnH QnPH QnPRH When displayed –– –– –– –– Display completed –– –– –– –– 0.40 0.17 0.17 0.17 103 44 44 44 5.8 2.5 2.5 2.5 No display no display LED instruction execution CHKST CHK 1 contact no error 24 10 10 10 150 contact no error 1676 721 721 721 1 contact error 88 38 38 38 10 steps 5.8 2.5 2.5 2.
Instruction Qn QnH QnPH QnPRH =1 16 6.9 6.9 6.9 = 9999 17 7.2 7.2 7.2 =1 25 11 11 11 = 99999999 29 13 13 13 –– 40 17 17 17 DABCD S DABCDP S DDABCD S DDABCDP S COMRD COMRDP 18 8.0 8.0 8.
Instruction Processing Time (µs) Condition (Device) Qn QnH QnPH QnPRH –– 527 227 227 227 –– 1656 713 713 713 SIN Single precision 115 50 50 50 SINP Double precision 1945 837 –– –– COS Single precision 122 53 53 53 COSP Double precision 2618 1127 –– –– TAN Single precision 123 53 53 53 TANP Double precision 2618 1127 –– –– ASIN Single precision 111 48 48 48 ASINP Double precision 2491 1072 –– –– ACOS Single precision 115 49 49 49 ACOSP D
Instruction Condition (Device) QnH QnPH QnPRH =0 6.2 2.7 2.7 2.7 = 9999 38 16 16 16 =0 6.2 2.7 2.7 2.7 = 99999999 38 16 16 16 –– 12 5.1 5.1 5.1 –– 12 5.2 5.2 5.2 –– 12 5.2 5.2 5.2 –– 20 8.7 8.7 8.7 –– 21 9.0 9.0 9.0 –– 22 9.6 9.6 9.6 –– 10 4.3 4.3 4.3 –– 11 4.7 4.7 4.7 –– 9.8 4.2 4.2 4.2 –– 11 4.9 4.9 4.9 –– 9.1 3.9 3.9 3.9 –– 11 4.6 4.6 4.6 –– 6.8 2.9 2.9 2.9 –– 205 88 88 88 –– 147 63 63 63 –– 13 5.5 5.
Instruction DATE+ DATE+P DATE DATE - P SECOND SECONDP HOUR HOURP MSG PKEY PSTOP PSTOPP POFF POFFP PSCAN PSCNAP PLOW PLOWP WDT WDTP DUTY ZRRDB ZRRDBP ZRWRB ZRWRBP ADRSET ADRSETP KEY ZPUSH ZPUSHP ZPOP ZPOPP EROMWR EROMWRP App-46 Condition (Device) Processing Time (µs) Qn QnH QnPH QnPRH No digit increase 13 5.4 5.4 5.4 Digit increase 13 5.4 5.4 5.4 No digit increase 12 5.2 5.2 5.2 Digit increase 12 5.2 5.2 5.2 –– 10 4.5 4.5 4.5 –– 12 5.2 5.2 5.2 1 character 3.0 1.3 1.
Instruction Processing Time (µs) Condition (Device) Qn QnH QnPH QnPRH ZCOM –– 691 289 289 289 READ –– –– –– –– –– SREAD –– –– –– –– –– WRITE –– –– –– –– –– SWRITE –– –– –– –– –– SEND –– –– –– –– –– RECV –– –– –– –– –– REQ –– –– –– –– –– ZNFR –– –– –– –– –– ZNTO –– –– –– –– –– MELSECNET/10 –– –– –– –– MELSECNET (II) –– –– –– –– MELSECNET/10 –– –– –– –– ZNRD ZNWR MELSECNET (II) –– –– –– –– RFRP –– –– –– –– –– RTOP
(b) Instructions available from function version B Instruction Processing Time (µs) Condition/Number of Points Processed Qn QnH QnPH QnPRH 720 660 660 –– 860 730 730 –– –– 43 20 20 20 n3 = 1 59 29 29 –– n3 = 1000 530 500 500 –– Refresh range: 2k words (0.
(6) Table of the time to be added when file register, module access device or link direct device is used Instruction data Bit When standard RAM is used Word Double word File register (ZR) When SRAM card is used (Q2MEM-1MBS, Q2MEM-2MBS) Bit Word Double word Bit Module access device (Un\G , U3En\G0 to G4095) Word Double word Bit Link direct device (Jn\ ) Word Double word Processing Time (µs) Device Specification Location Qn QnH QnPH QnPRH Source 5.56 2.40 2.40 2.40 Destination 4.44 1.
Appendix 1.4 Operation Processing Time of Universal Model QCPU The processing time for the individual instructions are shown in the table on the following pages. Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time rather than as being strictly accurate. Appendix 1.4.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. LD= In conductive status In non-conductive status Max. 0.360 Q00UCPU Min. Max. 0.240 Q01UCPU Min. Max. 0.180 Q02UCPU Min. Max. 0.120 8 When not executed AND= When executed In conductive status 0.360 0.240 0.180 0.120 In non-conductive status 8 When not executed OR= LD<> When executed In conductive status 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 A 0.360 0.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. LDD= In conductive status In non-conductive status Max. Q00UCPU Min. Max. Q01UCPU Min. Max. Q02UCPU Min. Max. 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.360 0.240 0.180 0.120 0.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. + S D + S1 S2 - S D D - S1 S2 D+ S D D D + S1 S2 D- S D D D - S1 S2 D Max. Q01UCPU Min. Max. Q02UCPU Min. Max. When executed 0.360 0.240 0.180 0.120 When executed 0.480 0.320 0.240 0.160 When executed 0.360 0.240 0.180 0.120 When executed 0.480 0.320 0.240 0.160 When executed 0.360 0.240 0.180 0.120 When executed 0.480 0.320 0.240 0.160 When executed 0.360 0.240 0.180 0.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. 0.220 0.180 0.140 =0 0.300 0.220 0.180 0.140 = 7FFFFFFFH 0.300 0.220 0.180 0.140 =0 0.300 0.220 0.180 0.140 = 32766.5 0.300 0.220 0.180 0.140 =0 0.300 0.220 0.180 0.140 = 1234567890.3 0.300 0.220 0.180 0.140 0.240 0.240 0.240 0.240 0.240 4.200 4.600 4.850 5.150 6.800 11.300 7.450 11.900 4.100 4.600 0.160 0.160 0.160 0.160 0.160 4.200 4.600 4.850 5.150 6.800 11.300 7.450 11.900 4.100 4.600 0.
Processing Time (µs) Category Instruction Condition (Device) ROR D n RCR D n ROL D n RCL D n DROR D n DRCR D n DROL D n Application DRCL D n instruction SFR D n SFL D n DSFR D n DSFL D n Min. Max. Min. Max. 2.250 10.800 2.250 10.800 2.250 10.800 2.300 7.800 2.250 10.800 2.350 10.800 2.350 10.800 2.400 7.800 n=1 2.250 10.800 2.250 10.800 2.250 10.800 2.300 3.900 n = 15 2.250 10.800 2.250 10.800 2.250 10.800 2.400 4.100 n=1 2.250 10.800 2.350 10.
(b) When using Q03UD(E)HCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU,Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. Max. Q04/Q06UD(E)HCPU Min. Max. Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. LD LDI AND ANI OR ORI LDP When executed 0.020 0.0095 0.0095 When executed 0.060 0.0285 0.0285 When executed 0.080 0.038 0.038 0.020 0.0095 0.0095 0.020 0.0095 0.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. LD= In conductive status In non-conductive status Max. Q04/ Q06UD(E)HCPU Min. Max. Q10/Q13/Q20/ Q26UD(E)HCPU Min. 8 Max. 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. LDD= In conductive status In non-conductive status Max. Q04/ Q06UD(E)HCPU Min. Max. Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.060 0.0285 0.0285 0.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. + S D + S1 S2 - S D D - S1 S2 D+ S D D D + S1 S2 D- S D D D - S1 S2 D Max. Min. When executed 0.060 0.0285 0.0285 When executed 0.080 0.038 0.038 When executed 0.060 0.0285 0.0285 When executed 0.080 0.038 0.038 When executed 0.060 0.0285 0.0285 When executed 0.080 0.038 0.038 When executed 0.060 0.0285 0.0285 When executed 0.080 0.038 0.038 When executed 0.120 0.057 0.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. FLT DFLT INT DINT = 7FFFH 0.100 0.0475 0.0475 =0 0.100 0.0475 0.0475 = 7FFFFFFFH 0.100 0.0475 0.0475 =0 0.100 0.0475 0.0475 = 32766.5 0.100 0.0475 0.0475 =0 0.100 0.0475 0.0475 = 1234567890.3 0.100 0.0475 0.0475 0.040 0.040 0.040 0.040 0.040 6.300 8.200 0.019 0.019 0.019 0.019 0.019 0.019 0.019 0.019 0.019 0.019 5.400 7.000 5.400 7.000 8.200 10.600 3.900 5.100 3.900 5.100 6.000 7.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. WAND S D WAND S1 S2 DAND S D D DAND S1 S2 WOR S D WOR S1 S2 DOR S WXOR S D D WXOR S1 S2 DXOR S D D WXNR S1 S2 DXNR S D D DXOR S1 S2 WXNR S D D Application DOR S1 S2 instruction D D D DXNR S1 S2 D Max. Q04/Q06UD(E)HCPU Min. Max. Q10/Q13/Q20/ Q26UD(E)HCPU Min. 8 Max. When executed 0.060 0.0285 0.0285 When executed 0.080 0.038 0.038 When executed 0.060 0.0285 0.0285 When executed 0.
Processing Time (µs) Category Instruction Condition (Device) n=1 ROR D n RCR D n ROL D n RCL D n DROR D n DRCR D n DROL D n Application DRCL D n instruction SFR D n SFL D n DSFR D n DSFL D n S Q04/Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. 2.300 3.100 1.700 2.500 1.700 2.500 n = 15 2.400 3.100 1.800 2.500 1.800 2.500 n=1 2.300 3.900 1.700 3.200 1.700 3.200 n = 15 2.400 4.100 1.700 3.200 1.700 3.200 n=1 2.400 3.300 1.800 3.
(2) Table of the time to be added when file register, module access device is used 8 (a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU Device name data Bit When standard RAM is used Word Double word Bit File register (R) When SRAM card is used (Q2MEM-1MBS, Q2MEM-2MBS) Word Double word Bit When SRAM card is used (Q3MEM-4MBS, Q3MEM-8MBS) Word Double word Bit When standard RAM is used Word Double word File register Bit (ZR)/ data register (D)/Extended When SRAM card is used (Q2MEM-1MBS, Q2M
(b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UDE(H)CPU,Q20UD(E)HCPU and Q26UD(E)HCPU Device name data Bit When standard RAM is used Word Double word Bit File register (R) When SRAM card is used (Q2MEM-1MBS, Q2MEM-2MBS) Word Double word Bit When SRAM card is used (Q3MEM-4MBS, Q3MEM-8MBS) Word Double word Bit When standard RAM is used Word Double word File register Bit (ZR)/ Extended data register (D)/Extended When SRAM card is used (Q2MEM-1MBS, Q2MEM-2MBS) link regi
(3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction 8 (a) When using Q00UJCPU, Q00UCPU, Q01UCPU amd Q02UCPU. Instruction name Device name Condition When not executed F When executed OUT When executed F When executed F 2.900 2.900 2.100 116.000 116.000 68.800 Display completed 116.000 116.000 116.000 61.600 0.360 0.240 0.180 0.120 After time up 0.360 0.240 0.180 0.120 When added 0.360 0.240 0.180 0.120 0.120 0.080 0.006 0.
Appendix 1.4.2 Processing time of instructions other than subset instruction The following table shows the processing time of instructions other than subset instructions. (1) Table of the processing time of instructions other than subset instructions (a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. Max. Q00UCPU Min. Max. Q01UCPU Min. Max. Q02UCPU Min. Max. ANB ORB MPS –– 0.120 0.080 0.060 0.040 0.120 0.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. Sequence instruction Q00UCPU Min. Max. Q01UCPU Min. Max. Q02UCPU Min. Max. 8 NOP NOPLF –– 0.120 0.080 0.060 0.040 PAGE LDE= ANDE= ORE= LDE< > ANDE< > ORE< > LDE> Basic Max. ANDE> instruction LDE<= ANDE<= ORE<= LDE< ANDE< ORE< In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100 precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.
Processing Time (µs) Category Instruction LDE>= ANDE>= ORE>= LDED= ANDED= ORED= LDED<> Basic ANDED<> instruction ORED<> LDED> ANDED> ORED> LDED<= ANDED<= ORED<= App-68 Condition (Device) Q00UJCPU Max. Min. Max. Min. Max. 20.900 4.400 20.900 4.400 20.900 4.700 12.200 20.900 4.400 20.900 4.400 20.900 4.700 11.800 Single In conductive status In non-conductive status 4.
Processing Time (µs) Category Instruction LDED< ANDED< ORED< LDED>= ANDED>= ORED>= LD$= Condition (Device) Basic instruction LD$> LD$<= 4.700 37.400 5.100 25.000 precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 24.100 Double precision Double precision When not executed 0.360 0.240 0.180 0.120 When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.400 executed In non-conductive status 4.500 34.700 4.500 34.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. When not executed OR$<= When executed LD$< 7.400 35.600 7.400 35.600 7.400 35.600 4.700 14.600 35.600 7.400 35.600 7.400 35.600 4.600 14.400 7.400 40.000 7.400 40.000 7.400 40.000 4.800 17.000 40.000 7.400 40.000 7.400 40.000 5.500 18.
Processing Time (µs) Category Instruction DB + S D DB + S1 S2 DB - S Condition (Device) D D Q00UJCPU Q00UCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. When executed 5.750 13.300 5.750 13.300 5.750 13.300 4.900 7.500 When executed 5.650 13.200 5.650 13.200 5.650 13.200 5.200 11.000 When executed 5.750 12.700 5.750 12.700 5.750 12.700 4.900 10.200 DB - S1 S2 D When executed 5.650 12.600 5.650 12.600 5.650 12.600 5.200 8.
Processing Time (µs) Category Instruction Condition (Device) Q00UCPU Q01UCPU Q02UCPU Max. Min. Max. Min. Max. Min. Max. DBL When executed 3.300 5.900 3.300 5.900 3.300 5.900 2.700 3.800 WORD When executed 3.000 7.250 3.000 7.250 3.000 7.250 2.900 7.000 GRY When executed 3.350 7.500 3.350 7.500 3.350 7.500 2.700 6.100 DGRY When executed 3.000 7.200 3.000 7.200 3.000 7.200 2.900 4.600 GBIN When executed 4.600 9.700 4.600 9.700 4.600 9.700 4.000 8.
Processing Time (µs) Category Instruction Condition (Device) BKAND S1 S2 n D BKOR S1 S2 n D BKXOR S1 S2 D n BKXNR S1 S2 D n BSFR D n BSFL D n SFTBR D n1 n2 SFTBL D n1 n2 SFTWR D n1 n2 SFTWL D n1 n2 Q00UCPU Q01UCPU Q02UCPU Max. Min. Max. Min. Max. Min. Max. n=1 13.600 28.500 13.600 28.500 13.600 28.500 12.100 20.100 n = 96 63.200 78.200 63.200 78.200 63.200 78.200 57.400 63.200 n=1 13.500 28.500 13.500 28.500 13.500 28.500 7.700 13.200 n = 96 63.
Processing Time (µs) Category Instruction DIS S UNI S n D n D Q00UCPU Q01UCPU Q02UCPU Max. Min. Max. Min. Max. Min. Max. n=1 6.500 14.800 6.500 14.800 6.500 14.800 5.000 10.900 n=4 6.900 15.200 6.900 15.200 6.900 15.200 5.400 11.300 n=1 6.800 15.100 6.800 15.100 6.800 15.100 5.500 8.900 n=4 7.500 15.900 7.500 15.900 7.500 15.900 6.200 9.600 When executed 4.750 18.700 4.750 18.700 4.750 18.700 11.000 16.300 NUNI When executed 4.750 18.700 4.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q01UCPU Q02UCPU Max. Min. Max. Min. Max. Min. Max. 18.100 89.100 18.100 89.100 18.100 89.100 12.800 79.000 33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000 33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000 78.600 231.000 78.600 231.000 78.600 231.000 54.000 212.000 78.600 231.000 78.600 231.000 78.600 231.000 54.000 212.000 18.100 89.000 18.100 89.000 18.
Processing Time (µs) Category Instruction Condition (Device) Min. Max. Min. Max. =1 5.050 13.400 5.050 13.400 5.050 13.400 4.400 5.900 = FFFFH 5.050 13.400 5.050 13.400 5.050 13.400 4.400 5.800 =1 5.600 13.900 5.600 13.900 5.600 13.900 5.200 6.700 = FFFFFFFFH 5.600 13.900 5.600 13.900 5.600 13.900 5.100 6.500 =1 4.850 13.200 4.850 13.200 4.850 13.200 4.300 5.800 = 9999 5.300 13.600 5.300 13.600 5.300 13.600 4.700 6.100 =1 5.300 13.600 5.
Processing Time (µs) Category Instruction Condition (Device) EVAL ASC S HEX S D D RIGHT S LEFT S D Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Decimal point format all 2-digit specification 23.900 70.400 23.900 70.400 23.900 70.400 23.300 36.500 Exponent format all 6-digit specification 23.700 70.300 23.700 70.300 23.700 70.300 23.300 36.400 n=1 10.200 41.800 10.200 41.800 10.200 41.800 5.600 19.700 n = 96 31.900 66.600 31.900 66.600 31.900 66.600 30.
Processing Time (µs) Category Instruction Double EXPD S LOG S Condition (Device) D Min. Max. Min. Max. = -10 15.800 52.700 15.800 52.700 15.800 52.700 8.800 27.600 S =1 15.400 52.500 15.400 52.500 15.400 52.500 8.500 27.300 S =1 5.800 14.900 5.800 14.900 5.800 14.900 4.100 8.100 = 10 7.450 16.500 7.450 16.500 7.450 16.500 6.200 10.300 =1 11.000 48.900 11.000 48.900 11.000 48.900 9.500 28.300 = 10 12.600 51.300 12.600 51.300 12.600 51.300 11.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8 Min. Max. Min. Max. Min. Max. Min. Max. 14.900 50.100 14.900 50.100 14.900 50.100 14.700 48.000 8 15.800 50.900 15.800 50.900 15.800 50.900 19.600 50.400 8 13.900 53.100 13.900 53.100 13.900 53.100 13.700 51.000 8 16.600 56.600 16.600 56.600 16.600 56.600 20.400 56.200 13.400 52.400 13.400 52.400 13.400 52.400 12.800 50.300 14.200 54.100 14.200 54.
Processing Time (µs) Category Instruction Condition (Device) RSET QDRSET Q00UJCPU Q01UCPU Q02UCPU Min. Max. Min. Max. Min. Max. Min. Max. Standard RAM 6.800 26.900 6.800 26.900 6.800 26.900 3.000 16.400 SRAM card –– –– –– –– –– –– 3.000 16.400 SRAM card to standard RAM –– –– –– –– –– –– 230.000 327.000 Standard RAM to SRAM card –– –– –– –– –– –– 997.000 1066.000 SRAM card to standard ROM –– –– –– –– –– –– 525.000 690.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Min. When not executed In conductive Comparison of specified ANDTM>= ciock status In nonconductive status In conductive Comparison of current ciock status In nonconductive status Max. 0.240 Min. Max. 0.160 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900 6.500 23.100 6.500 23.100 6.500 23.
Processing Time (µs) Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU 8 Min. Max. Min. Max. Min. Max. Min. Max. 29.400 91.700 29.400 91.700 29.400 91.700 20.600 55.000 8 29.500 91.600 29.500 91.600 29.500 91.600 20.600 66.100 8 79.900 214.000 79.900 214.000 79.900 214.000 102.000 180.000 When mounting CC-Link module (Master station side) When mounting CC-Link module (Local station side) When mounting MELSECNET/H, S.
Processing Time (µs) Category Instruction Condition (Device) Writing to host S.TO n1 n2 n3 n4 CPU shared D memory Writing to host TO n1 n2 CPU shared n3 S memory Writing to host DTO n1 n2 CPU shared n3 S memory Multiple Reading from CPU host CPU shared dedicated instruction memory FROM n1 n2 D n3 n3 Min. Max. Min. Max. Min. Max. Min. Max. 64.600 78.100 64.600 78.100 64.600 78.100 64.600 78.100 115.000 126.000 115.000 126.000 115.000 126.000 154.000 126.000 12.700 62.
(b) When using Q03UD(E)JCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU 8 Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. Max. Q04/Q06UD(E)HCPU Min. Max. Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. 8 ANB ORB MPS –– 0.020 0.0095 0.0095 8 0.020 0.0095 0.0095 8 0.020 0.0095 0.0095 0.020 0.0095 0.
Processing Time (µs) Category Instruction LDE= ANDE= ORE= LDE< > ANDE< > ORE< > LDE> Basic ANDE> instruction ORE> LDE<= ANDE<= ORE<= LDE< ANDE< ORE< App-90 Condition (Device) Single In conductive status precision In non-conductive status Single precision Single precision When not executed When Q03UD(E)CPU Q04/ Q06UD(E)HCPU Min. Max. Min. Max. Min. Max. 3.700 4.700 3.300 4.300 3.300 4.300 3.800 5.000 3.400 4.500 3.400 4.500 In conductive status 0.060 0.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. LDE>= ANDE>= ORE>= LDED= ANDED= ORED= LDED<> Basic ANDED<> instruction ORED<> ANDED> ORED> LDED<= ANDED<= ORED<= Min. Max. Single In conductive status 3.800 6.000 3.300 5.500 precision In non-conductive status 3.800 5.900 3.400 5.400 Single precision Single When not executed When In conductive status executed In non-conductive status When not executed Max. 0.0285 4.800 2.900 4.600 3.
Processing Time (µs) Category Instruction LDED< ANDED< ORED< LDED>= ANDED>= ORED>= LD$= AND$= Basic instruction Condition (Device) Double In conductive status precision In non-conductive status Double precision Double precision When not executed In conductive status When executed In non-conductive status When not executed When In conductive status executed In non-conductive status LD$< > AND$< > LD$> AND$> LD$<= AND$<= App-92 Min. Max. Min. Max. Min. Max. 4.300 8.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. When not executed OR$<= When executed LD$< 7.200 4.400 7.200 In non-conductive status 7.600 4.400 7.100 4.400 7.100 4.800 8.100 4.500 7.500 4.500 7.500 In non-conductive status 5.000 8.300 4.500 7.900 4.500 7.900 In conductive status 4.500 7.100 4.000 6.600 4.000 6.600 4.900 7.500 4.400 7.100 4.400 7.100 Basic instruction BKCMP<> S1 S2 4.100 7.200 4.100 7.
Processing Time (µs) Category Instruction DB + S D DB + S1 S2 DB - S Condition (Device) D D Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. When executed 4.900 7.000 4.600 6.400 4.600 6.400 When executed 5.200 7.300 4.800 6.700 4.800 6.700 When executed 4.900 6.600 4.700 6.000 4.700 6.000 DB - S1 S2 D When executed 5.200 7.500 4.800 6.600 4.800 6.600 DB * S1 S2 D When executed 8.300 12.100 8.100 11.600 8.100 11.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. DBL When executed 2.700 3.400 2.300 2.700 2.300 2.700 WORD When executed 2.900 4.300 2.600 3.600 2.600 3.600 GRY When executed 2.700 3.900 2.300 3.400 2.300 3.400 DGRY When executed 2.900 3.500 2.500 3.000 2.500 3.000 GBIN When executed 4.000 4.800 3.800 4.300 3.800 4.300 DGBIN When executed 5.500 6.100 5.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min. BKAND S1 S2 n D BKOR S1 S2 n D BKXOR S1 S2 D n BKXNR S1 S2 D n BSFR D n BSFL D n SFTBR D n1 n2 SFTBL D n1 n2 SFTWR D n1 n2 SFTWL D n1 n2 Min. Min. Max. Max. n=1 9.000 11.700 8.300 11.000 8.300 11.000 n = 96 57.400 63.100 43.800 47.300 43.800 47.300 n=1 7.700 10.000 7.700 9.500 7.700 9.500 n = 96 57.400 61.900 44.300 45.800 44.300 45.800 n=1 7.800 10.100 7.300 9.200 7.
Processing Time (µs) Category Instruction Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Max. Min. Max. Min. Max. n=1 4.400 5.300 3.800 4.600 3.800 4.600 n=4 4.800 5.700 4.000 5.000 4.000 5.000 n=1 5.000 5.300 3.500 4.800 3.500 4.800 n=4 5.600 6.000 4.000 5.100 4.000 5.100 NDIS When executed 11.000 13.100 11.000 13.200 11.000 13.200 NUNI When executed 10.600 12.700 7.300 13.200 7.300 13.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU When selecting I/O refresh only When selecting CC-Link refresh only (Master station side) When selecting CC-Link refresh only (Local station side) When selecting MELSECNET/H refresh only (Control station side) When selecting MELSECNET/H refresh only (Normal station side) When selecting intelli auto refresh only COM CCOM When selecting I/O outside the group only (Input only) When selecting I/O outside the group only (Output only)
Processing Time (µs) Category Instruction Condition (Device) Min. Max. Min. Max. =1 4.400 5.900 3.800 5.200 3.800 5.200 = FFFFH 4.400 5.800 3.700 5.200 3.700 5.200 =1 5.200 6.700 4.600 6.000 4.600 6.000 = FFFFFFFFH 5.100 6.500 4.600 6.000 4.600 6.000 =1 4.300 5.800 3.600 5.000 3.600 5.000 = 9999 4.700 6.100 4.100 5.400 4.100 5.400 =1 4.800 6.300 4.000 5.500 4.000 5.500 = 99999999 5.600 7.100 4.900 6.300 4.900 6.300 =1 6.500 8.500 5.800 7.
Processing Time (µs) Category Instruction Condition (Device) Decimal point format all 2-digit specification EVAL Exponent format all 6-digit specification ASC S D n HEX S D n RIGHT S LEFT S n D D n Q03UD(E)CPU Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. 23.300 30.400 22.800 29.000 22.800 29.000 23.300 30.500 22.500 29.000 22.500 29.000 n=1 5.600 9.000 5.400 8.300 5.400 8.300 n = 96 28.700 32.100 25.200 28.400 25.200 28.
Processing Time (µs) Category Instruction EXP S Condition (Device) Single D Min. Max. Min. Max. = -10 4.000 6.100 3.800 5.500 3.800 5.500 =1 4.000 6.100 3.800 5.600 3.800 5.600 = -10 8.700 13.900 8.200 13.500 8.200 13.500 S =1 8.400 13.600 8.000 13.200 8.000 13.200 S =1 4.100 6.900 3.800 6.400 3.800 6.400 = 10 5.600 8.200 5.200 7.700 5.200 7.700 =1 8.100 13.000 7.700 12.500 7.700 12.500 = 10 9.700 14.800 9.200 14.300 9.200 14.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. 13.200 23.600 12.300 22.500 12.300 22.500 13.300 23.600 12.600 22.700 12.600 22.700 12.000 23.100 11.400 22.200 11.400 22.200 14.100 25.300 12.800 23.900 12.800 23.900 12.800 23.800 11.900 23.000 11.900 23.000 12.900 23.900 12.100 23.000 12.100 23.000 11.500 22.400 10.900 21.500 10.900 21.500 13.800 24.
Processing Time (µs) Category Instruction Condition (Device) QCDSET Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. Standard RAM 3.000 6.300 2.700 5.900 2.700 5.900 SRAM card 3.000 6.400 2.600 5.800 2.600 5.800 SRAM card to standard RAM 120.000 134.000 115.000 134.000 115.000 134.000 RSET QDRSET Q03UD(E)CPU Standard RAM to SRAM card 533.000 560.000 520.000 553.000 520.000 553.000 SRAM card to standard ROM 306.000 346.000 305.000 346.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Min.
Processing Time (µs) Category Instruction Condition (Device) Comparison of specified date LDDT<= Comparison of current date In conductive status In nonconductive status In conductive status In nonconductive status Q03UD(E)CPU of specified ANDDT<= date Comparison of current date In conductive status In nonconductive status In conductive status In nonconductive status Max. Min. Max. Min. Max. 7.400 11.400 6.800 10.900 6.800 10.900 7.400 11.600 6.800 10.900 6.800 10.900 5.900 10.
Processing Time (µs) Category Instruction Condition (Device) Comparison of specified date LDDT>= Comparison of current date In conductive status In nonconductive status In conductive status In nonconductive status Q03UD(E)CPU of specified ANDDT>= date Comparison of current date In conductive status In nonconductive status In conductive status In nonconductive status Max. Min. Max. Min. Max. 7.400 11.400 6.800 10.900 6.800 10.900 7.400 11.600 6.800 10.900 6.800 10.900 5.900 10.
Processing Time (µs) Category Instruction Condition (Device) Comparison of specified ciock LDTM<> Comparison of current ciock In conductive status In nonconductive status In conductive status In nonconductive status Q03UD(E)CPU of specified ANDTM<> ciock Comparison of current ciock In conductive status In nonconductive status In conductive status In nonconductive status Max. Min. Max. Min. Max. 7.300 11.500 6.700 10.800 6.700 10.800 7.300 11.500 6.700 10.800 6.700 10.800 5.800 9.
Processing Time (µs) Category Instruction Condition (Device) Comparison of specified ciock LDTM<= Comparison of current ciock In conductive status In nonconductive status In conductive status In nonconductive status Q03UD(E)CPU of specified ANDTM<= ciock Comparison of current ciock In conductive status In nonconductive status In conductive status In nonconductive status Max. Min. Max. Min. Max. 7.300 11.500 6.700 10.800 6.700 10.800 7.300 11.500 6.700 10.800 6.700 10.800 5.800 9.
Processing Time (µs) Category Instruction Condition (Device) Comparison of specified ciock In conductive status In nonconductive status LDTM< Comparison of current ciock In conductive status In nonconductive status Q03UD(E)CPU of specified ANDTM< ciock In conductive status In nonconductive status Comparison of current ciock In conductive status In nonconductive status Max. Min. Max. Min. Max. 7.300 11.500 6.700 10.800 6.700 10.800 7.300 11.500 6.700 10.800 6.700 10.800 5.
Processing Time (µs) Category Instruction Condition (Device) Q03UD(E)CPU Q04/ Q06UD(E)HCPU Q10/Q13/Q20/ Q26UD(E)HCPU Min. Max. Min. Max. Min. Max. 19.600 26.500 19.300 26.000 19.300 26.000 19.600 26.500 19.100 26.200 19.100 26.200 53.500 73.500 53.000 72.700 53.000 72.700 29.800 41.200 29.800 40.600 29.800 40.600 5.900 11.000 5.400 10.500 5.400 10.
Processing Time (µs) Category Instruction Condition (Device) Writing to host S.TO n1 n2 n3 n4 CPU shared D memory Writing to host TO n1 n2 CPU shared n3 S memory Writing to host DTO n1 n2 CPU shared n3 S memory Multiple Reading from CPU host CPU shared dedicated instruction memory FROM n1 n2 D n3 Reading from n3 DP.DDWR n D.DDRD n 34.700 34.900 33.500 34.400 33.500 34.400 n4 = 320 85.900 87.600 75.200 75.500 75.200 75.500 n3 = 1 4.700 23.800 5.200 23.300 5.
(2) Table of the time to be added when file register, module access device or link direct device is used (a) When using Q00UJCPU, Q00UCPUI, Q01UCPU and Q02UCPU Device name data Bit When standard RAM is used Word Double word When SRAM File register (R) card is used (Q2MEM-1MBS, Q2MEM-2MBS) When SRAM card is used (Q3MEM-4MBS, Q3MEM-8MBS) Bit Word Double word Bit Word Double word Bit When standard RAM is used Word Double word When SRAM File register (ZR) card is used (Q2MEM-1MBS, Q2MEM-2MBS) When S
(b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU and Q26UD(E)HCPU Device name data Bit When standard RAM is used Word Double word When SRAM File register (R) card is used (Q2MEM-1MBS, Q2MEM-2MBS) When SRAM card is used (Q3MEM-4MBS, Q3MEM-8MBS) Bit Word Double word Bit Word Double word Bit When standard RAM is used Word Double word File rExtended Extended link register (W)) egister (ZR) card is used (Q2MEM-1MBS, Q2MEM-2MBS) When SRAM card is used (Q
Appendix 2 CPU PERFORMANCE COMPARISON Appendix 2.1 Comparison of Q with AnNCPU, AnACPU, and AnUCPU Appendix 2.1.1 Usable devices TableApp.2.
*1 *2 *3 : The number of device points can be changed at the parameters. : QCPU uses V as an edge relay. : Instructions that used accumulators with the AnNCPU, AnACPU, and AnUCPU have different formats with the QCPU. *4 : Can only be used by the $MOV instruction with the Q00JCPU, Q00CPU, and Q01CPU. *5 : The Q00JCPU does not have file registers. *6 : Applicable to products with the first 5 digits of the serial number 04122 or higher (Q00JCPU, Q00CPU, and QCPU).
Appendix 2.1.4 Timer comparison TableApp.2.4 Timer Comparison Function QCPU Measurement unit Change of measurement unit at the parameter is enabled. QCPU Low speed timer AnUCPU AnACPU AnNCPU 100ms (default value) Fixed at 100ms : 1 to 1000ms (1ms unit) K100 T0 Designation method K100 T0 10ms (default value) Change of measurement unit at the parameter is enabled. Measurement unit QnUCPU : 0.01 to 100ms (0.01ms unit) Fixed at 10ms QCPU(Other than QnUCPU) : 0.1 to 100ms (0.
Example 8 • For timers T0 to T2, the program is created in the order the timer operates later. T1 T0 X0 K1 T2 T2 timer starts measurement from the next scan after turning the contact of T1 ON. K1 T1 T1 timer starts measurement from the next scan after turning the contact of T0 ON. K1 T0 T0 timer starts measurement when X0 is turned ON. 8 8 8 • For timers T0 to T2, the program is created in the order of timer operation. X0 K1 T0 T0 A T0 timer starts measurement when X0 is turned ON.
Appendix 2.1.7 Instructions whose designation format has been changed (Except dedicated instructions for AnACPU and AnUCPU) Because the QCPU does not have accumulators (A0, A1), the format of AnUCPU, AnACPU and AnNCPU instructions that used accumulators has been changed. TableApp.2.7 Instructions Whose Expression Has Changed QCPU Function Instruction Format ROR D n 16-bit rotation to right n ROL D n • D : Rotation data ROL n RCL D n • D : Rotation data • SM700 is used for carry flag.
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions 8 (1) Method of expression of dedicated instructions Dedicated instructions based on the LEDA, LEDB, LEDC, SUB, and LEDR instructions, that are used with the AnACPU or AnUCPU have been changed for the same format as the basic instructions and the application instructions for the QCPU.
Appendix 3 SPECIAL RELAY LIST Special relays, SM, are internal relays whose applications are fixed in the Programmable Controller. For this reason, they cannot be used by sequence programs in the same way as the normal internal relays. However, they can be turned ON or OFF as needed in order to control the CPU module. The heading descriptions in the following special relay lists are shown in 3.1. TableApp.3.
(1) Diagnostic Information 8 TableApp.3.2 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM0 SM1 Diagnostic errors Self-diagnostic error OFF : No error ON : Error OFF : No self-diagnosis errors ON : Self-diagnosis • Turns ON if an error occurs as a result of diagnosis. (Includes when an annunciator is ON, and when an error is detected with CHK instruction) • Remains ON even if the condition is restored to normal thereafter.
TableApp.3.2 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM56 SM60 Operation error OFF : Normal ON : Operation error • ON when operation error is generated • Remains ON if the condition is restored to normal thereafter. S (Error) M9011 Blown fuse detection OFF : Normal ON : Module with blown fuse • Turns ON if there is at least one output module whose fuse has blown. • Remains ON if the condition is restored to normal thereafter.
(2) System information TableApp.3.
TableApp.3.3 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM240 SM241 SM242 SM243 SM244 SM245 No. 1 CPU reset flag OFF : No. 1 CPU reset cancel ON : No. 1 CPU resetting • Goes OFF when reset of the No. 1 CPU is canceled. • Comes ON when the No. 1 CPU is resetting (including the case where the CPU module is removed from the base). The other CPUs are also put in reset status. No. 2 CPU reset flag OFF : No. 2 CPU reset cancel ON : No.
TableApp.3.3 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU 8 M9 SM255 OFF : Operative network ON : Standby network • Goes ON for standby network(If no designation has been made concerning active or standby, active is assumed.) OFF : Reads ON : Does not read New • For refresh from link to CPU module (B, W, etc.) indicate whether to read from the link module.
TableApp.3.
(3) System clocks/counters 8 TableApp.3.4 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM400 Always ON ON OFF Always OFF ON OFF • Normally is ON S (Every END processing) • Normally is OFF S (Every END processing) M9036 QCPU SM401 SM402 After RUN, ON for 1 scan only • After RUN, ON for 1 scan only. • This connection can be used for scan execution type programs only.
TableApp.3.4 Special relay Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU M9 SM415 2n (ms) clock SM420 User timing clock No.0 SM421 User timing clock No.1 SM422 User timing clock No.2 SM423 User timing clock No.3 SM424 User timing clock No.4 • This relay alternates between ON and OFF at intervals of the time (unit: ms) specified in SD415.
(6) Memory cards TableApp.3.
TableApp.3.
(7) Instruction-Related Special Relays TableApp.3.
TableApp.3.8 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM734 XCALL instruction execution condition designation OFF : Not executed by execution condition risen ON : Executed by execution condition risen SM735 SFC comment readout instruction in execution flag OFF : SFC comment readout instruction is inactivated. ON : SFC comment readout instruction is activating. • Turns on the instructions, (S(P).
TableApp.3.8 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU 8 M9 SM796 Block information using multiple CPU high-speed transmission dedicated instruction (for CPU No.1) OFF : Block is secured ON : Block set by SD796 cannot be secured • Turns ON when the number of the remaining blocks of the dedicated instruction transmission area used for the multiple CPU high-speed transmission dedicated instruction(target CPU= CPU No.
(9) A to Q conversion correspondences Special relays SM1000 to SM1255 are the relays which correspond to ACPU special relays M9000 to M9255 after A to Q conversion. (However, the Basic model QCPU and Redundant CPU do not support the A to Q conversion.) These special relays are all set by the system, and cannot be set by the user program. To turn them ON/OFF by the user program, change the special relays in the program into those of QCPU.
TableApp.3.11 Special relay ACPU Special Relay Special Special Relay after Relay for Conversion Modification Name Meaning Details • Turns ON if an instantaneous power failure of within 20ms occurs during use of the AC power supply module. • Reset when the power supply is switched OFF, then ON.
TableApp.3.11 Special relay ACPU Special Relay Special Relay after Conversion Special Relay for Modification M9034 SM1034 – M9036 SM1036 – Name 2n minute clock(1 minute clock)*2 Always ON Meaning Details • Alternates between ON and OFF according to the seconds specified at SD414. (Default: n = 30) • Not turned on or off per scan but turned on and off even during scan if corresponding time has elapsed.
TableApp.3.
TableApp.3.11 Special relay ACPU Special Relay M9103 Special Relay after Conversion Special Relay for Modification SM1103 SM323 Presence/absence of continuous transition OFF : Continuous transition not effective ON : Continuous transition effective • Set whether continuous transition will be performed for the block where the "continuous transition bit" of the SFC information device is not set.
(11) Process control instructions 8 TableApp.3.13 Special relay Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU M9 SM1500 SM1501 Hold mode OFF : No-hold ON : Hold • Specifies whether or not to hold the output value when a range over occurs for the S.IN instruction range check. U Hold mode OFF : No-hold ON : Hold • Specifies whether or not the output value is held when a range over occurs for the S.OUT instruction range check.
TableApp.3.13 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 • Turns on when the CPU module is started up by the system switching (switching from the standby system to the control system). Remains OFF when the standby system is switched to the control system by a power-ON startup. S (Status change) New 1 scan • Turns ON once switch between standby system to control system, (ON for 1 scan only) occurs.
TableApp.3.
TableApp.3.13 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM1593 Setting to access extension base unit of standby system CPU OFF : Error ON : Ignored Sets the operation for the case accessing buffer memory of the intelligent function module mounted on the extension base unit from the standby system CPU in separate mode.
(14) For redundant system (tracking) Either the backup mode or the second mode is valid for SM1700 to SM1799. All is turned off for stand-alone system. 8 TableApp.3.15 Special relay Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU M9 SM1700 Transfer trigger completion flag OFF : Transfer not completed ON : Transfer completed • Turns on for one scan, once transfer of block 1 to block 64 is completed.
TableApp.3.
TableApp.3.
Appendix 4 SPECIAL REGISTER LIST The special registers, SD, are internal registers with fixed applications in the Programmable Controller. For this reason, it is not possible to use these registers in sequence programs in the same way that normal registers are used. However, data can be written as needed in order to control the CPU modules. Data stored in the special registers are stored as BIN values if no special designation has been made to the contrary.
(1) Diagnostic Information 8 TableApp.4.2 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 SD0 Diagnostic errors Diagnosis error code • Error codes for errors found by diagnosis are stored as BIN data. • Contents identical to latest fault history information. S (Error) D9008 format change 8 • Year (last two digits) and month that SD0 data was updated is stored as BCD 2-digit code.
TableApp.4.2 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU D9 • Common information corresponding to the error codes (SD0) is stored here. • The following ten types of information are stored here: • The error common information type can be judged by the "common information category code" in SD4. (The values of the "common information category code" stored in SD4 correspond to following 1) to 8).) 1) Slot No.
TableApp.4.2 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU 8 D9 8 SD5 8 SD6 3) Number SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD7 SD8 4) SD9 Error common information SD10 SD11 Error common information 8 Time (value set) Meaning Time : 1 s units (0 to 999 s) Time : 1ms units (0 to 65535ms) A (Empty) 8 Program error location Meaning Number SD5 File name SD6 (ASCII code: 8 characters) SD7 SD8 2EH(.
TableApp.4.
TableApp.4.2 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU 8 D9 8 SD5 8 SD6 8 SD7 A 8) Number SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD8 SD9 SD10 Tracking transmission data classification Stores the data classification during tracking.
TableApp.4.2 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • Individual information corresponding to error codes (SD0) is stored here. • There are the following eight different types of information are stored. • The error individual information type can be judged by the "individual information category code" in SD4. (The values of the "individual information category code" stored in SD4 correspond to following 1) to 8), 12), and 13).
*6 : Extensions are shown below. TableApp.4.
TableApp.4.
TableApp.4.2 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU 8 D9 SD50 Error reset Error number that performs error reset • Stores error number that performs error reset U 8 New • All corresponding bits go 1(ON) when battery voltage drops. • Subsequently, these remain 1(ON) even after battery voltage has been returned to normal.
TableApp.4.2 Special register Number Name Corresponding ACPU Explanation Set by (When Set) • The first annunciator number (F number) to be detected is stored here. S (Instruction execution) D9009 • Stores the number of annunciators searched.
TableApp.4.2 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU 8 D9 SD100 Transmission speed storage area Stores the transmission speed specified in the serial communication setting. 96 576 : 9.6kbps, : 57.6kbps, b15 SD101 Communication setting storage area Stores the communication setting specified in the serial communication setting. 192 1152 : 19.2kbps, : 115.2kbps 384 : 38.
TableApp.4.2 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • The numbers of output modules whose fuses have blown are input as a bit pattern (in units of 16 points). (If the module numbers are set by parameter, the parameter-set numbers are stored.
(2) System information 8 TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 8 • The CPU switch status is stored in the following format: b15 to b12 b11 to b8 b7 3) Status of switch Status of CPU switch b4 b3 2) Empty to b0 8 1) 0: RUN 1: STOP 2: L.
TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • Specify the LEDs to be turned off using this register, and turn SM202 from OFF to ON to turn off the specified LEDs. USER and BOOT can be specified as the LEDs to be turned off. • Specify the LEDs to be turned off in the following bit pattern. (Turned off at 1, not be turned off at 0.
TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU 8 D9 SD207 Priorities 1 to 4 SD208 Priorities 5 to 8 8 • When error is generated, the LED display (flicker) is made according to the error number setting priorities. (The Basic model QCPU supports only the annunciator (error item No. 7).
TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • The year (first two digits) and the day of the week are stored as BCD code as shown below.
TableApp.4.
TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 Number of modules installed SD254 SD256 SD257 SD258 SD259 MELSECNET/ 10. MELSECNET/H information Information from 1st module SD255 • Indicates the number of mounted MELSECNET/10 modules or MELSECNET/H modules. I/O No. • Indicates I/O number of mounted MELSECNET/10 module or MELSECNET/H module Network No. • Indicates network No.
TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU 8 D9 8 1) When Xn0 of the mounted CC-Link module turns ON, the bit of the corresponding station turns to 1 (ON). 2) When either Xn1 or XnF of the mounted CC-Link module turns OFF, the bit of the corresponding station turns to 1 (ON). 3) Turns to 1 (ON) when communication between the mounted CC-Link module and CPU module cannot be made.
TableApp.4.4 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU D9 16 bit modification Number of points assigned for Z Device assignment (Same as parameter contents) Number of points assigned for ZR (for extension) • Stores the number of ZR device points (except the number of points of extended data register (D) and extended link register (W)).
TableApp.4.
TableApp.4.4 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 Number of multiple CPUs SD393 Q00/Q01*9 QnU • The number of CPU modules that comprise the multiple CPU system is stored. (1 to 3, Empty also included) • The CPU module types of No. 1 CPU to 3 and whether the CPU modules are mounted or not are stored. SD394 b15 to b12 b11 to b8 b7 b0 to b4 b3 to Empty (0) CPU No.3 CPU No.2 CPU No.
(4) Scan information 8 TableApp.4.6 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU D9 SD500 Execution program No. Program No. in execution • Program number of program currently being executed is stored as BIN value. SD510 Low speed excution type program No. Low speed execution type program No. in execution • Program number of low speed excution type program No. currently being executed is stored as BIN value.
TableApp.4.
(5) Memory card 8 TableApp.4.7 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • Indicates the type of the memory card installed.
TableApp.4.7 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • Indicates the drive 3/4 type. b15 SD620 Drive 3/4 typs Drive 3/4 typs to 0 to b8 b7 b4 b3 to b0 Drive 3 (Standrd RAM) Fixed to 1 Drive 4 (Standrd ROM) Fixed to 3 S (Initial) New Qn(H) QnPH QnPRH QnU S (Initial) New Q00J/Q00/Q01 • Drive 3 capacity is stored in 1 k byte units. (Empty capacity after format is stored.
TableApp.4.
TableApp.4.7 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 SD670 Parameter enable drive information Parameter enable drive No. • Stores information of parameter storage destination drive which is enabled. 0: Drive 0 (Program memory) 1: Drive 1 (SRAM card) 2: Drive 2 (Flash card/ATA card) 4: Drive 4 (Standard ROM) (Only drive 0 and drive 4 are valid in the Q00UJCPU, Q00UCPU, and Q01UCPU.
Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • Stores the last 2 digits of year and month when data is restored in 2-digit BCD code. Restore time (Year and month) SD676 b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example: 8 July, 1993 9307H Year Month • Stores the day and time when data is restored in 2-digit BCD code. b15 to b12 b11 to b8 b7 to b4 b3 to Restore time (Day and time) SD677 8 b0 Example: 31st, 10 a.m.
Number Name Meaning Backup execution status Backup execution status display (Percentage) Explanation Set by (When Set) Corresponding ACPU Corresponding CPU D9 SD691 SD692 Restoration error factor • Displays the execution status of data backup to the memory card in percentage (0 to 100%). • "0" is set when the backup starts.
(6) Instruction-Related Registers TableApp.4.
TableApp.4.8 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 • Specify the limit of each PID loop as shown below.
TableApp.4.8 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 8 • Selects whether or not the data is refreshed when the COM, CCOM instruction is executed. • Designation of SD778 is made valid when SM775 turns ON.
TableApp.4.8 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU D9 SD796 SD797 SD798 SD799 Maximum number of blocks used for the multiple CPU highspeed transmission dedicated instruction setting (for CPU No.1) Maximum number of blocks used for the multiple CPU highspeed transmission dedicated instruction setting (for CPU No.2) Maximum number of blocks used for the multiple CPU highspeed transmission dedicated instruction setting (for CPU No.
(7) Debug TableApp.4.9 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU 8 Corresponding CPU D9 SD840 Debug function usage Debug function usage Stores the status of the debug function usage as shown below.
(10) A to Q conversion ACPU special registers D9000 to D9255 correspond to Q special registers SD1000 to SD1255 after A to Q/QnA conversion. (However, the Basic model QCPU and Redundant CPU do not support the A to Q conversion.) These special registers are all set by the system, and cannot be set by the user program. To set data by the user program, correct the program for use of the QCPU special registers.
TableApp.4.13 Special register ACPU Special Register D9000 Special Register after Conversion Special Register for Modification – SD1000 Name Fuse blown Meaning Number of module with blown fuse Corresponding CPU Details • When fuse blown modules are detected, the first I/O number of the lowest number of the detected modules is stored in hexadecimal.
TableApp.4.13 Special register ACPU Special Register D9009 D9010 D9011 D9014 Special Register after Conversion Special Register for Modification Name Meaning Corresponding CPU Details Annunciator detection F number at which external failure has occurred • When one of F0 to 2047 is turned on by OUT F or SET F instruction, the F number, which has been detected earliest among the F numbers which have turned on, is stored in BIN code. • SD1009 can be cleared by RST F or LEDR instruction.
TableApp.4.13 Special register ACPU Special Register D9016 Special Register after Conversion Special Register for Modification Name Program number SD1016 Meaning 0: Main program (ROM) 1: Main program (RAM) 2: Subprogram 1 (RAM) 3: Subprogram 2 (RAM) 4: Subprogram 3 (RAM) 5: Subprogram 1 (ROM) 6: Subprogram 2 (ROM) 7: Subprogram 3 (ROM) 8: Main program Corresponding CPU Details 8 8 8 • Indicates which sequence program is run presently. One value of 0 to B is stored in BIN code.
TableApp.4.13 Special register ACPU Special Register Special Register after Conversion Special Register for Modification Name Meaning Corresponding CPU Details • The day of the week is stored as BCD code as shown below. b15 D9028 D9035 D9036 – SD1028 SD1035 SD648 Clock data Extension file register to b8 b7 to b4 b3 to b0 Example: Friday H0005 Day of the week Clock data (day of week) Use block No.
TableApp.4.13 Special register ACPU Special Register Special Register after Conversion Special Register for Modification Name Meaning Corresponding CPU Details D9053 SD1053 Error transition Transition condition number where error occurred • Stores the transition condition number, where error code 84 occurred in an SFC program, in BIN value. Stores "0" when error code 80, 81, 82 or 83 occurred.
TableApp.4.13 Special register ACPU Special Register Special Register after Conversion D9100 SD1100 D9101 SD1101 D9102 SD1102 Special Register for Modification Name Meaning Corresponding CPU Details • Output module numbers (in units of 16 points), of which fuses have blown, are entered in bit pattern. (Preset output module numbers when parameter setting has been performed.
TableApp.4.13 Special register Special Register after Conversion Special Register for Modification D9125 SD1125 SD64 D9126 SD1126 SD65 D9127 SD1127 SD66 ACPU Special Register Name Meaning Corresponding CPU Details 8 • When any of F0 to 2047 is turned on by SET F instruction, the annunciator numbers (F numbers) that are turned on in order are registered into SD1125 to SD1132.
(11) QCPU with built-in Ethernet port TableApp.4.14 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 Operation result SD1270 Stores operationresult. Stores the operation result of the time setting function. 0: Not executed 1: Success FFFFH: Failure Stores years (last two digits of the Christian Era) and monthes by two digits of BCD code.
TableApp.4.15 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU 8 D9 8 Open completion status of connections (whose open system is socket communication) using socket communication functions is stored. All bits corresponding to connections using any communications other than the socket communication are fixed to "0".
(12) Fuse blown module TableApp.4.16 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 SD1300 SD1301 SD1302 SD1303 Bit pattern in units of 16 points, indicating the modules whose fuses have blown 0 : No blown fuse 1 : Blown fuse present SD1304 SD1305 SD1306 SD1307 Fuse blown module SD1308 SD1309 to SD1330 • The numbers of output modules whose fuses have blown are input as a bit pattern (in units of 16 points).
(15) For redundant systems (Host system CPU information *1) 8 SD1510 to SD1599 are only valid for redundant systems. They are all set to 0 for stand-alone systems. TableApp.4.
(16) For redundant systems (Other system CPU information *1) SD1600 to SD1659 is only valid during the back up mode for redundant systems, and refresh cannot be done when in the separate mode. SD1651 to SD1699 are valid in either the backup mode or separate mode. When a stand-alone system SD1600 to SD1699 are all 0. TableApp.4.
TableApp.4.20 Special register Number Name Set by (When Set) Meaning Explanation Error code of error to be cleared • Stores the error code of the error to be cleared by clearing a standby system error. • Stores the error code of the error to be cleared into this register and turn SM1649 from OFF to ON to clear the standby system error. • The value in the lowest digit (1 place) of the error code is ignored when stored into this register.
(17) For redundant systems (Trucking) SD1700 to SD1779 is valid only for redundant systems. These are all 0 for stand-alone systems. TableApp.4.21 Special register Number Name Meaning Explanation Set by (When Set) Corresponding ACPU Corresponding CPU D9 SD1700 SD1710 Tracking error detection count Waiting time for online program change (standby system) App-196 Tracking error detection count • When the tracking error is detected, count is added by one.
(18) Redundant power supply module information SD1780 to SD1789 are valid only for a redundant power supply system. The bits are all 0 for a singular power supply system. 8 TableApp.4.22 Special register Number Name Meaning Set by (When Set) Explanation Corresponding ACPU Corresponding CPU D9 8 • Stores the status of the redundant power supply module with input power OFF in the following bit pattern. • Stores 0 when the main base unit is not the redundant power main base unit (Q38RB).
Appendix 5 APPLICATION PROGRAM EXAMPLES Appendix 5.1 Concept of Programs which Perform Operations of Xn, n X (1) Concept of programs which perform operations of Xn Xn can be operated using e(nlogeX). For example, the operation of 101.2 is e(1.2 sequence program as shown below. loge10) , which is represented in the form of a Converts 10 into a real number format data and stores the result in D0 and D1. Executes Loge10 operation and stores the result in D2 and D3.
I INDEX I Index-1
[Symbols] - (BIN 16-bit subtraction operations).................... 6-22 $+ (Linking character strings) ...................... 6-65,6-67 $=, $<>, $>, $<=, $<, $>= (Character string data comparisons) ....................................................... 6-11 $MOV (Character string transfers) .................... 6-112 * (BIN 16-bit multiplication operations) ................ 6-30 + (BIN 16-bit addition operations)........................ 6-22 / (BIN 16-bit division operations) .........................
BCD 4-digit multiplication and division operations (B*, B/) ........................................................................ 6-42 BCD 4-digit square roots (BSQR)...................... 7-306 BCD 8-digit addition and subtraction operations (DB+, DB-) ..................................................................... 6-38 BCD 8-digit multiplication and division operations (DB*, DB/)............................................................ 6-44 BCD 8-digit square roots (BDSQR) ...................
CML (16-bit negation transfers) ......................... 6-114 COM (Refresh instruction) ............. 7-134,7-137,7-141 Common logarithm operation on floating-point data (Double precision) (LOG10D(P)) ....................... 7-302 Common logarithm operation on floating-point data (Single precision) (LOG10(P)) ........................... 7-300 Comparison operation instruction table ............... 2-10 Comparison operation instructions ........................ 6-2 Comparisons (BIN 16-bit data) ............
Conversion from hexadecimal BIN to ASCII (ASC) ........................................................................... 7-228 Conversion of Gray code to BIN 16-bit (GBIN).... 6-92 Conversion of Gray code to BIN 32-bit (DGBIN) ............................................................................. 6-92 Conversion to BIN BCD 4-digit to BIN 16-bit (BIN) ........................ 6-75 BCD 8-digit to BIN 32-bit (DBIN)......................
DI (Interrupt disable) .......................................... 6-133 Digit designation .................................................... 3-4 Digit designation of bit devices .............................. 3-4 DINC (Incrementing 32-bit BIN)........................... 6-71 DINT (Floating decimal point data to BIN 32-bit (Single precision)) ............................................................ 6-83 DINTD (Floating decimal point data to BIN 32-bit (Double precision)) ...............................
Expansion clock data subtraction operation (S.DATE-) ........................................................................... 7-366 EXPD (Exponent operation on floating-point data (Double precision)) ............................................ 7-294 Exponent operation on floating-point data (Double precision) (EXPD).............................................. 7-294 Exponent operation on floating-point data (Single precision) (EXP) ................................................
[J] JMP (Pointer branch)......................................... 6-129 Jump to END (GOEND)..................................... 6-132 [K] KEY (Numerical key input from keyboard)......... 7-396 [L] Ladder block parallel connections (ORB) ............ 5-10 Ladder block series connections (ANB) .............. 5-10 LD ($=, $<>, $>, $<=, $<, $>=) (Character string data comparisons) ....................................................... 6-11 LD (=, <>, >, <=, <, >=) (BIN 16-bit data comparisons) ...............
[O] Operation errors .................................................. 3-27 Operation results inversion (INV) ........................ 5-15 Operation results pop (MPP) ............................... 5-12 Operation results push (MPS) ............................. 5-12 Operation results read (MRD) ............................. 5-12 Operation start (LD, LDI) ....................................... 5-2 OR ($=, $<>, $>, $<=, $<, $>=) (Character string data comparisons) .........................................
RADD (Conversion from floating-point angle to radian (Double precision)) ............................................ 7-277 RAMP (Ramp signal) ......................................... 6-157 Ramp signal (RAMP) ......................................... 6-157 Random number generation (RND/SRND)........ 7-304 Random selection from and replacement in character strings (MIDR) ................................................... 7-235 Random selection replacement in character strings (MIDW) .......................
SIND (SIN operation on floating-point data (Double precision)).......................................................... 7-252 Single precision to Double precision conversion (ECON).............................................................. 6-102 SORT (BIN 16-bit data sort) ................................ 7-95 SP.CONTSW (System switching instruction) ...... 11-2 SP.DEVST (Writing data to standard ROM)...... 7-436 SP.FREAD (Reading data from designated file) ..............................................
S.TO................................................................... 9-4 TO ...................................................................... 9-7 WSUM (Calculation of totals for 16-bit data) ....... 7-99 WTOB (Data dissociation in byte units) ............... 7-85 WXNR (16-bit data exclusive NOR operation)..... 7-27 WXNR (16-bit data non-exclusive logical sum operations)........................................................... 7-30 WXOR (16-bit exclusive OR operations) .....
Warranty Please confirm the following product warranty details before using this product. 1. Gratis Warranty Term and Gratis Warranty Range If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term, the product shall be repaired at no cost via the sales representative or Mitsubishi Service Company.
Microsoft, Windows, Windows NT are registered trademarks of Microsoft Corporation in the United States and other countries. Pentium and Celeron are trademarks of Intel Corporation in the United States and other countries. Ethernet is a trademark of Xerox Co., Ltd. in the United States. CompactFlash is a trademark of SanDisk Corporation. VxWorks, Tornado, WindPower, WindSh and WindView are registered trademarks of Wind River Systems, Inc.
