User Guide

8965 N/B Maintenance
8965 N/B Maintenance
78
Compensation
Signal Name Pin # I/O Signal Description Power Plane
HRCOMP
F15 AI Host CPU Compensation. Connect 20.5 §Ù
1% resistor to ground. Used for Host CPU
interface I/O buffer calibration.
VTT
VLCOMPP
AM6 AI V-Link Compensation. Connect a 360Ω 1%
resistor to ground.
VCC15VL
AGPCOMPN
AB3 AI AGP N Compensation. Connect a 60.4Ω1%
resistor to VCC15AGP.
VCC15AGP
AGPCOMPP
AC6 AI AGP P Compensation. Connect a 60.4Ω1%
resistor to ground.
VCC15AGP
Reference Voltages
Signal Name Pin # I/O Signal Description Power Plane
GTLVREF
H17 P
Host CPU Interface AGTL+ Voltage
Reference. 2/3 VTT ±2% typically derived
using a resistive voltage divider. See Design
Guide.
VTT
HDVREF[0:3]
H11,
H14, K7,
J7
P Host CPU Data Voltage Reference. 2/3 VTT
±2% typically using a resistive voltage divider.
See Design Guide.
VTT
HAVREF[0:1]
H19, G22 P Host CPU Address Voltage Reference. 2/3
VTT ±2% typically derived using a resistive
voltage divider. See Design Guide.
VTT
HCOMPVREF
G14 P
Host CPU Compensation Voltage Reference.
1/3 VTT ±2% typically derived using a
resistive voltage divider. See Design Guide.
VTT
MEMVREF
[0:5]
J29, R29,
W29,
AE29,
AK22,
AK17
P Memory Voltage Reference. 0.5 VCC25MEM
±2% typically derived
using a resistive voltage divider. See Design
Guide.
VCC25MEM
VLVREF
AL7 P V-Link Voltage Reference. 0.625V ±2%
derived using a resistive voltage divider. See
Design Guide.
VCC15VL
AGPVREF[0:1]
AF7,
AD7
P AGP Voltage Reference. ½ VCC15AGP
(0.75V) for AGP 2.0 (4x transfer mode) and
0.23 VCC15AGP (0.35V) for AGP 3.0 (8x
transfer mode). See the Design Guide for
additional information and circuit
implementation details.
VCC15AGP
Analog Power / Ground
Signal Name Pin # I/O Signal Description
VCCA33HCK1
M4 P Power for Host CPU Clock PLL 1 (3.3V ±5%).
Host CPU Clock PLL 1 generates 400 MHz for
CPU / DRAM frequencies of multiples of 100,
133, and 200 MHz.
GNDAHCK1
M3 P Ground for Host CPU Clock PLL 1. Connect to
main ground plane through a ferrite bead.
VCCA33HCK2
L1 P Power for Host CPU Clock PLL 2 (3.3V ±5%).
Host CPU Clock PLL 2 generates 500 MHz for
CPU / DRAM frequencies of multiples of 166
MHz.
GNDAHCK2
L2 P Ground for Host CPU Clock PLL 2. Connect to
main ground plane through a ferrite bead.
VCCA33MCK
D31 P Power for Memory Clock PLL (3.3V ±5%)
GNDAMCK
E31 P Ground for Memory Clock PLL. Connect to
main ground plane through a ferrite bead.
VCCA33GCK
M1 P Power for AGP Clock PLL (3.3V ±5%)
GNDAGCK
M2 P Ground for AGP Clock PLL. Connect to main
ground plane through a ferrite bead.
VCCA15PLL1
P3 P Power for Graphics Controller PLL 1 (1.5V
±5%).
GNDAPLL1
P2 P
Ground for Graphics Controller PLL 1.
Connect to main ground plane through a ferrite
bead.
VCCA15PLL2
P6 P Power for Graphics Controller PLL 2 (1.5V
±5%).
GNDAPLL2
N6 P
Ground for Graphics Controller PLL 2.
Connect to main ground plane through a ferrite
bead.
VCCA15PLL3
N1 P Power for Graphics Controller PLL 3 (1.5V
±5%).
GNDAPLL3
N2 P
Ground for Graphics Controller PLL 3.
Connect to main ground plane through a ferrite
bead.
VCCA33DAC[1:2]
T5, P4 P Power for DAC. (3.3V ±5%)
GNDADAC[1:3]
T6, P5, R4 P Ground for DAC. Connect to main ground plane
through a ferrite bead.
5.2 PN800 North Bridge - 11
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