User Guide

8965 N/B Maintenance
8965 N/B Maintenance
77
Flat Panel Power Control (Muxed with AGP)
Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).
Signal Name AGP Name Pin # I/O Signal Description
ENAVDD
ST1 AE5 IO
Enable Panel VDD Power.
ENAVEE
ST0 AD6 IO
Enable Panel VEE Power.
ENABLT
ST2 AE6 IO
Enable Panel Back Light.
Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test
Signal Name Pin # I/O Signal Description Power Plane
HCLK+
M5 I Host Clock. This pin receives the host CPU
clock (100 / 133 / 166 / 200 / 266 MHz). This
clock is used by all PN800 logic that is in the
host CPU domain.
VTT
HCLK–
M6 I Host Clock Complement. Used for Quad Data
Transfer on host CPU bus.
VTT
MCLKOA
B31 O Memory (SDRAM) Clock A. Output from
internal clock generator to external memory
interface clock buffer (if required for fanout)
VCC25MEM
MCLKIA
A32 I Memory (SDRAM) Clock Feedback. Input
from MCLKOA.
VCC25MEM
MCLKOB
A31 O Memory (SDRAM) Clock B. Output from
internal clock generator to external memory
interface clock buffer (if required for fanout)
VCC25MEM
DISPCLKI
N3 I Dot Clock (Pixel Clock) In. Used for external
EMI reduction circuit if used. Connect to GND
if external EMI reduction circuit not
implemented.
VCC33GFX
DISPCLKO
N4 O Dot Clock (Pixel Clock) Out. Used for
external EMI reduction circuit if used. NC if
external EMI reduction circuit not
implemented.
VCC33GFX
GCLK
N7 I AGP Clock. Clock for AGP logic.
VCC15AGP
XIN
N5 I Reference Frequency Input. External
14.31818 MHz clock source. All internal
graphics controller clocks are synthesized on
chip using this frequency as a reference.
VCC33GFX
RESET#
AM13 I Reset. Input from the South Bridge chip. When
asserted, this signal resets the PN800 and sets
all register bits to the default value. The rising
edge of this signal is used to sample all
power-up strap options
VSUS15
PWROK
AP14 I Power OK. Connect to South Bridge and
Power Good circuitry.
VSUS15
SUSST#
AN14 I Suspend Status. For implementation of the
Suspend-to-DRAM feature. Connect to an
external pull-up to disable.
VSUS15
Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test
(Continued)
Signal Name Pin # I/O Signal Description Power Plane
AGPBUSY# /
NMI
AL14 O
AGP Interface Busy.
Connect to a South
Bridge GPIO pin for monitoring the status of
the internal AGP bus. See Design Guide for
details. Pin function selectable with Device 0
Function 0 RxBE[7] (default = NMI).
VCC25MEM
GPOUT
/
CAPD14
W5 O
General Purpose Output.
This pin reflects the
state of SRD[0].
VCC33GFX
GPO0
/ CAPD15 V5 O
General Output Port.
When SR1A[4] is
cleared, this pin reflects the state of CR5C[0].
VCC33GFX
INTA#
U2 O
Interrupt.
PCI interrupt output (handled by the
interrupt controller in the South Bridge)
VCC33GFX
TCLK
W6 I
Test Clock.
This pin is used for testing and
must be connected to GND through a 1K-4.7K
ohm resistor for all board designs.
VCC33GFX
TESTIN#
C31 I
Test In.
This pin is used for testing and must
be connected to VTT through a 1K-4.7K ohm
resistor for all board designs.
VCC25MEM
DFTIN#
D32 I
DFT In.
This pin is used for testing and must
be connected to VTT through a 1K-4.7K ohm
resistor for all board designs.
VCC25MEM
BISTIN
/
CAPAFLD
V6 I
BIST In.
This pin is used for testing and must
be tied to GND with a 1K-4.7K ohm resistor on
all board designs.
VCC33GFX
5.2 PN800 North Bridge - 10
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