User Guide

8965 N/B Maintenance
8965 N/B Maintenance
76
24-Bit / Dual 12-Bit Flat Panel Display Interface
Signal Name AGP Name Pin # I/O Signal Description
FPD23 /
FPD0D11,
FPD22 /
FPD0D10,
FPD21 /
FPD0D09,
FPD20 /
FPD0D08,
FPD19 /
FPD0D07,
FPD18 /
FPD0D06,
FPD17 /
FPD0D05,
FPD16 /
FPD0D04,
FPD15 /
FPD0D03,
FPD14 /
FPD0D02,
FPD13 /
FPD0D01,
FPD12 /
FPD0D00,
FPD11 /
FPD1D11,
FPD10 /
FPD1D10,
FPD09 /
FPD1D09,
FPD08 /
FPD1D08,
FPD07 /
FPD1D07,
FPD06 /
FPD1D06,
FPD05 /
FPD1D05,
GD11
GD13
GD14
GD15
GC#BE2
GD16
GD17
GD18
GD23
GD20
GD22
GADSTB1F
GD1
GD0
GD3
GD4
GD5
GD6
GD7
AM4
AN2
AL1
AP1
AK2
AJ3
AJ1
AJ4
AH3
AH1
AK4
AG3
AP2
AT2
AT5
AR4
AT1
AN5
AT4
O Flat Panel Data. For 24-bit or dual 12-bit flat
panel display modes.
Two FPD interface modes, 24-bit and dual 12-bit,
are supported.
Strapping pin DVP0D4 is used to select the
interface mode to theLVDS transmitter chip:
Strap High (3C5.12[4]=1): 24-bit
Strap Low (3C5.12[4]=0): Dual 12-bit
In “24-bit” mode, only one set of control pins is
required. However, in dual 12-bit mode, the
PN800 provides two sets of control signals that are
required for certain LVDS transmitter chips.
In 24-bit mode, two operating modes are
supported:
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0
Double data rate: each rising & falling clock edge
transmits a complete 24-bit pixel
3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1
Single data rate: each clock rising edge transmits a
complete 24-bit pixel
In dual 12-bit mode,
3C5.12[4]=0 & 3x5.88[2] = 1
Double data rate: each rising and falling clock
edge transmits half (12 bits) of two 24-bit pixels
24-Bit / Dual 12-Bit Flat Panel Display Interface (Continued)
Signal Name AGP Name Pin # I/O Signal Description
FPD04 /
FPD1D04,
FPD03 /
FPD1D03,
FPD02 /
FPD1D02,
FPD01 /
FPD1D01,
FPD00 /
FPD1D00
GADSTB0F
GC#BE0
GADSTB0S
GD10
GD12
AT3
AN4
AR3
AR1
AL2
O
FPHS
GFRAME AL4 O Flat Panel Horizontal Sync. 24-bit mode or port
0 in dual 12-bit mode.
FPVS
GDEVSEL AK1 O Flat Panel Vertical Sync. 24-
b
it mode or port 0 in
dual 12-bit mode.
FPDE
GD19 AK6 O Flat Panel Data Enable. 24-bit mode or port 0 in
dual 12-bit mode
FPDET
GADSTB1S AG1 I Flat Panel Detect. 24-bit mode or port 0 in dual
12-bit mode
FPCLK
GD21 AH2 O Flat Panel Clock. 24-bit mode or port 0 in dual
12-bit mode
FPCLK# GWBF AB2 O Flat Panel Clock Complement. 24-bit mode or
port 0 in dual 12-bit mode. For double-data-rate
data transfers.
FP1HS
GD9 AP3 O Flat Panel Horizontal Sync. For port 1 in dual
12-bit mode.
FP1VS
GPAR AN3 O Flat Panel Vertical Sync. For port 1 in dual 12-
b
it
mode.
FP1DE
GSERR AN1 O Flat Panel Data Enable. For port 1 in dual 12-bit
mode.
FP1DET /
GTVCLKIN
GD8 AM1 I Flat Panel Detect. For port 1 in dual 12-bit mode.
FP1CLK
GD2 AP4 O Flat Panel Clock. For port 1 in dual 12-bit mode.
FP1CLK#
GSTOP AM3 O Flat Panel Clock Complement. For port 1 in dual
12-bit mode. For double-data-rate data transfers.
5.2 PN800 North Bridge - 9
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