User Guide

8965 N/B Maintenance
8965 N/B Maintenance
74
CCIR601 / CCIR656 / VIP1.1 / VIP2.0 Video Capture Port (VCP)
Signal Name Pin # I/O Signal Description
CAPD15 / GPO0
CAPD14 / GPOUT
CAPD13 / SPDAT1
CAPD12 / SPCLK1,
CAPD11 / DVP0D11 /
TVD11,
CAPD10 / DVP0D10 /
TVD10 / strap,
CAPD9 / DVP0D9 / TVD9 /
strap,
CAPD8 / DVP0D8 / TVD8 /
strap,
CAPD7 / DVP0D7 / TVD7 /
strap,
CAPD6 / DVP0D6 / TVD6 /
strap,
CAPD5 / DVP0D5 / TVD5 /
strap,
CAPD4 / DVP0D4 / TVD4 /
strap,
CAPD3 / DVP0D3 / TVD3 /
strap,
CAPD2 / DVP0D2 / TVD2 /
strap,
CAPD1 / DVP0D1 / TVD1 /
strap,
CAPD0 / DVP0D0 / TVD0 /
strap
V5
W5
V4
V3
AA6
AB6
AB5
Y7
Y6
Y5
AA4
Y2
Y3
AA5
W2
W1
I Video Capture Data. To configure DVP0 as a
video capture port, pin DVP0D6 must be strapped
low.
Pin Function:
8-Bit Mode 16-Bit Mode
CAPBD7 CAPAD15
CAPBD6 CAPAD14
CAPBD5 CAPAD13
CAPBD4 CAPAD12
CAPBD3 CAPAD11
CAPBD2 CAPAD10
CAPBD1 CAPAD9
CAPBD0 CAPAD8
CAPAD7 CAPAD7
CAPAD6 CAPAD6
CAPAD5 CAPAD5
CAPAD4 CAPAD4
CAPAD3 CAPAD3
CAPAD2 CAPAD2
CAPAD1 CAPAD1
CAPAD0 CAPAD0
CAPHS / DVP0HS / TVHS W4 I Video Capture Horizontal Sync. For capture port
“A” (16-bit and 8-bit mode). Internally pulled
down.
CAPVS / DVP0VS / TVVS V1 I Video Capture Vertical Sync. For capture port
“A” (16-bit and 8-bit mode). Internally pulled
down.
CCIR601 / CCIR656 / VIP1.1 / VIP2.0 Video Capture Port (VCP)
(Continued)
Note: I/O pads for the pins on this page are powered by VCC33GFX (3.3V I/O)
Signal Name Pin # I/O Signal Description
CAPAFLD / BISTIN V6 I
Video Capture “A”-Channel TV Field
Indicator. For capture port “A” (16-bit and 8-bit
mode).
CAPBCLK / DVP0DET /
TVCLKIN
V2 I Video Capture Clock B. Port “B” (8-bit mode)
input clock from external video decoder. Internally
pulled down. Not used in 16-bit mode.
CAPACLK / DVP0CLK /
TVCLK
Y4 I Video Capture Clock A. Port “A” (16-bit and
8-bit mode) input clock from external video
decoder. Internally pulled down.
DDR SDRAM Interface – Address
Signal Name Pin # I/O Signal Description
MAA[13:0],
MAB[13:0]
(see pin
lists)
O Memory Address A and B. Two sets for additional drive.
Output drive strength may be set by Device 0
Function 3 RxE8 (MAA) and EA (MAB).
BAA[1:0],
BAB[1:0]
AT35,
AT31,
AF36,
AJ36
O Bank Address A and B. Two sets for additional drive.
Output drive strength may be set by Device 0 Function 3 RxE8
(BA) and EA (BB).
SRASA#,
SCASA#,
SWEA#,
SRASB#,
SCASB#,
SWEB#
AP26,
AN25,
AR26,
AL29,
AN28,
AN31
O
Row Address, Column Address and Write Enable
Command Indicators A and B. Two sets for additional drive.
Output drive strength may be set by Device 0 Function 3 Rx E8
(ScmdA) and EA (ScmdB).
Note: I/O pads for all SDRAM pins are powered by VCC25MEM. MD / DQS input voltage
levels are referenced to MEMVREF.
5.2 PN800 North Bridge - 7
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